---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.top_earlgrey.u_pinmux_aon.FpvSecCmBusIntegrity_A	0	0	133603549	0	0	0
tb.dut.top_earlgrey.u_pinmux_aon.PwrMgrStrapSampleOnce1_A	0	0	133603549	0	0	977
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexLockstepResetCountAlertCheck_A	0	0	529562655	0	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexPcMismatchCheck_A	0	0	529562655	0	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexRfEccErrCheck_A	0	0	529562655	0	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexStoreRespIntgErrCheck_A	0	0	529562655	0	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A	0	0	529562655	0	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A	0	0	529562655	0	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmRvCoreRegWeOnehotCheck_A	0	0	529562655	0	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.NoReadyValidNoGrant_A	0	0	529562655	0	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	529562655	0	0	1016
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	529562655	0	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.NoReadyValidNoGrant_A	0	0	529562655	0	0	0
tb.dut.top_earlgrey.u_rv_plic.FpvSecCmBusIntegrity_A	0	0	529562655	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.top_earlgrey.scanmodeKnown	0	0	536482604	536482604	0	0
tb.dut.top_earlgrey.u_pinmux_aon.AlertsKnown_A	0	0	133603549	132911476	0	0
tb.dut.top_earlgrey.u_pinmux_aon.AonWkupReqKnownO_A	0	0	1659087	1463027	0	0
tb.dut.top_earlgrey.u_pinmux_aon.DftJtagTckKnown_A	0	0	133603549	132911476	0	0
tb.dut.top_earlgrey.u_pinmux_aon.DftJtagTmsKnown_A	0	0	133603549	132911476	0	0
tb.dut.top_earlgrey.u_pinmux_aon.DftJtagTrstKnown_A	0	0	133603549	132911476	0	0
tb.dut.top_earlgrey.u_pinmux_aon.DftStrapsKnown_A	0	0	133603549	132911476	0	0
tb.dut.top_earlgrey.u_pinmux_aon.DioKnownO_A	0	0	133603549	132911476	0	0
tb.dut.top_earlgrey.u_pinmux_aon.DioOeKnownO_A	0	0	133603549	132911476	0	0
tb.dut.top_earlgrey.u_pinmux_aon.FpvSecCmRegWeOnehotCheck_A	0	0	133603549	5	0	0
tb.dut.top_earlgrey.u_pinmux_aon.LcJtagTckKnown_A	0	0	133603549	132911476	0	0
tb.dut.top_earlgrey.u_pinmux_aon.LcJtagTmsKnown_A	0	0	133603549	132911476	0	0
tb.dut.top_earlgrey.u_pinmux_aon.LcJtagTrstKnown_A	0	0	133603549	132911476	0	0
tb.dut.top_earlgrey.u_pinmux_aon.MioKnownO_A	0	0	133603549	132911476	0	0
tb.dut.top_earlgrey.u_pinmux_aon.MioOeKnownO_A	0	0	133603549	132911476	0	0
tb.dut.top_earlgrey.u_pinmux_aon.PinmuxWkupStable_A	0	0	1659087	4861	0	0
tb.dut.top_earlgrey.u_pinmux_aon.PwrMgrStrapSampleOnce0_A	0	0	133603549	1718	0	0
tb.dut.top_earlgrey.u_pinmux_aon.RvJtagTckKnown_A	0	0	133603549	132911476	0	0
tb.dut.top_earlgrey.u_pinmux_aon.RvJtagTmsKnown_A	0	0	133603549	132911476	0	0
tb.dut.top_earlgrey.u_pinmux_aon.RvJtagTrstKnown_A	0	0	133603549	132911476	0	0
tb.dut.top_earlgrey.u_pinmux_aon.TlAReadyKnownO_A	0	0	133603549	132911476	0	0
tb.dut.top_earlgrey.u_pinmux_aon.TlDValidKnownO_A	0	0	133603549	132911476	0	0
tb.dut.top_earlgrey.u_pinmux_aon.UsbWakeDetectActiveKnownO_A	0	0	1659087	1463027	0	0
tb.dut.top_earlgrey.u_pinmux_aon.UsbWkupReqKnownO_A	0	0	1659087	1463027	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.DftTapOff0_A	0	0	133603549	40829733	0	296
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnClear_A	0	0	133603549	11938667	0	15
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnSetRev0_A	0	0	133603549	1454	0	108
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnSetRev1_A	0	0	133603549	1454	0	108
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnSet_A	0	0	133603549	1454	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.RvTapOff0_A	0	0	133603549	264	0	216
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.RvTapOff1_A	0	0	133603549	38062770	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.TapStrapKnown_A	0	0	133603549	132911581	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.dft_strap0_idxRange_A	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.dft_strap1_idxRange_A	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap0_idxRange_A	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap1_idxRange_A	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tck_idxRange_A	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tdi_idxRange_A	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tdo_idxRange_A	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tms_idxRange_A	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.trst_idxRange_A	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync.OutputsKnown_A	0	0	133603549	132911581	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	133603549	132911581	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.FunctionCheck_A	0	0	133603549	132911581	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.OutputsKnown_A	0	0	133603549	132911581	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.NumCopiesMustBeGreaterZero_A	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.OutputsKnown_A	0	0	133603549	132911581	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_no_flops.OutputDelay_A	0	0	133603549	132911581	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.NumCopiesMustBeGreaterZero_A	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.OutputsKnown_A	0	0	133603549	132911581	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_no_flops.OutputDelay_A	0	0	133603549	132911581	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en.NumCopiesMustBeGreaterZero_A	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en.OutputsKnown_A	0	0	133603549	132911581	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en.gen_flops.OutputDelay_A	0	0	133603549	132904569	0	3054
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.NumCopiesMustBeGreaterZero_A	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.OutputsKnown_A	0	0	133603549	132911581	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.OutputDelay_A	0	0	133603549	132904569	0	3054
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en.NumCopiesMustBeGreaterZero_A	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en.OutputsKnown_A	0	0	133603549	132911581	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en.gen_flops.OutputDelay_A	0	0	133603549	132904569	0	3054
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en.NumCopiesMustBeGreaterZero_A	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en.OutputsKnown_A	0	0	133603549	132911581	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en.gen_flops.OutputDelay_A	0	0	133603549	132904569	0	3054
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.NumCopiesMustBeGreaterZero_A	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.OutputsKnown_A	0	0	133603549	132911581	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.gen_no_flops.OutputDelay_A	0	0	133603549	132911581	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic.selKnown0	0	0	983	851	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic.selKnown1	0	0	1763	748	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.en2addrHit	0	0	156586239	681645	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.reAfterRv	0	0	156586239	681645	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.rePulse	0	0	156586239	534830	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_chk.PayLoadWidthCheck	0	0	2936	2936	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.AllowedLatency_A	0	0	2936	2936	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.MatchedWidthAssert	0	0	2936	2936	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	2936	2936	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	2936	2936	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	2936	2936	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	2936	2936	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	2936	2936	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.BusySrcReqChk_A	0	0	156586239	124345	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.DstReqKnown_A	0	0	1897879	1672071	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.SrcAckBusyChk_A	0	0	156586239	273	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.SrcBusyKnown_A	0	0	156586239	155768523	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	1897879	39	0	986
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	1897879	39	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	156586239	312	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	1897879	173	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1897879	273	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	156586239	276	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.BusySrcReqChk_A	0	0	156586239	95581	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.DstReqKnown_A	0	0	1897879	1672071	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.SrcAckBusyChk_A	0	0	156586239	243	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.SrcBusyKnown_A	0	0	156586239	155768523	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	156586239	243	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1897879	243	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1897879	243	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	156586239	243	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.BusySrcReqChk_A	0	0	156586239	87159	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.DstReqKnown_A	0	0	1897879	1672071	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.SrcAckBusyChk_A	0	0	156586239	221	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.SrcBusyKnown_A	0	0	156586239	155768523	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	156586239	221	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1897879	221	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1897879	221	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	156586239	221	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.BusySrcReqChk_A	0	0	156586239	97026	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.DstReqKnown_A	0	0	1897879	1672071	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.SrcAckBusyChk_A	0	0	156586239	245	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.SrcBusyKnown_A	0	0	156586239	155768523	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	156586239	245	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1897879	245	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1897879	245	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	156586239	245	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.BusySrcReqChk_A	0	0	156586239	109578	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.DstReqKnown_A	0	0	1897879	1672071	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.SrcAckBusyChk_A	0	0	156586239	273	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.SrcBusyKnown_A	0	0	156586239	155768523	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	156586239	273	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1897879	273	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1897879	273	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	156586239	273	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.BusySrcReqChk_A	0	0	156586239	76692	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.DstReqKnown_A	0	0	1897879	1672071	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.SrcAckBusyChk_A	0	0	156586239	197	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.SrcBusyKnown_A	0	0	156586239	155768523	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	156586239	197	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1897879	197	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1897879	197	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	156586239	197	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.BusySrcReqChk_A	0	0	156586239	101393	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.DstReqKnown_A	0	0	1897879	1672071	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.SrcAckBusyChk_A	0	0	156586239	257	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.SrcBusyKnown_A	0	0	156586239	155768523	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	156586239	257	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1897879	257	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1897879	257	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	156586239	258	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.BusySrcReqChk_A	0	0	156586239	99236	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.DstReqKnown_A	0	0	1897879	1672071	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.SrcAckBusyChk_A	0	0	156586239	249	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.SrcBusyKnown_A	0	0	156586239	155768523	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	156586239	249	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1897879	249	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1897879	249	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	156586239	249	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.BusySrcReqChk_A	0	0	156586239	84170	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.DstReqKnown_A	0	0	1897879	1672071	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.SrcAckBusyChk_A	0	0	156586239	216	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.SrcBusyKnown_A	0	0	156586239	155768523	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	156586239	216	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1897879	216	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1897879	216	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	156586239	216	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.BusySrcReqChk_A	0	0	156586239	96247	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.DstReqKnown_A	0	0	1897879	1672071	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.SrcAckBusyChk_A	0	0	156586239	244	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.SrcBusyKnown_A	0	0	156586239	155768523	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	156586239	244	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1897879	244	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1897879	244	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	156586239	244	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.BusySrcReqChk_A	0	0	156586239	97838	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.DstReqKnown_A	0	0	1897879	1672071	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.SrcAckBusyChk_A	0	0	156586239	247	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.SrcBusyKnown_A	0	0	156586239	155768523	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	156586239	247	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1897879	247	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1897879	245	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	156586239	247	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.BusySrcReqChk_A	0	0	156586239	83179	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.DstReqKnown_A	0	0	1897879	1672071	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.SrcAckBusyChk_A	0	0	156586239	213	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.SrcBusyKnown_A	0	0	156586239	155768523	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	156586239	213	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1897879	213	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1897879	213	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	156586239	213	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.BusySrcReqChk_A	0	0	156586239	107656	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.DstReqKnown_A	0	0	1897879	1672071	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.SrcAckBusyChk_A	0	0	156586239	270	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.SrcBusyKnown_A	0	0	156586239	155768523	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	156586239	270	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1897879	270	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1897879	270	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	156586239	270	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.BusySrcReqChk_A	0	0	156586239	97320	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.DstReqKnown_A	0	0	1897879	1672071	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.SrcAckBusyChk_A	0	0	156586239	246	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.SrcBusyKnown_A	0	0	156586239	155768523	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	156586239	246	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1897879	246	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1897879	246	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	156586239	246	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.BusySrcReqChk_A	0	0	156586239	83591	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.DstReqKnown_A	0	0	1897879	1672071	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.SrcAckBusyChk_A	0	0	156586239	213	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.SrcBusyKnown_A	0	0	156586239	155768523	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	156586239	213	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1897879	213	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1897879	213	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	156586239	213	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.BusySrcReqChk_A	0	0	156586239	100318	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.DstReqKnown_A	0	0	1897879	1672071	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.SrcAckBusyChk_A	0	0	156586239	254	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.SrcBusyKnown_A	0	0	156586239	155768523	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	156586239	254	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1897879	254	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1897879	254	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	156586239	254	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.BusySrcReqChk_A	0	0	156586239	92653	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.DstReqKnown_A	0	0	1897879	1672071	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.SrcAckBusyChk_A	0	0	156586239	237	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.SrcBusyKnown_A	0	0	156586239	155768523	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	156586239	237	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1897879	237	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1897879	237	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	156586239	237	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.BusySrcReqChk_A	0	0	156586239	96154	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.DstReqKnown_A	0	0	1897879	1672071	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.SrcAckBusyChk_A	0	0	156586239	243	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.SrcBusyKnown_A	0	0	156586239	155768523	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	156586239	243	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1897879	243	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1897879	242	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	156586239	246	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.BusySrcReqChk_A	0	0	156586239	84013	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.DstReqKnown_A	0	0	1897879	1672071	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.SrcAckBusyChk_A	0	0	156586239	213	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.SrcBusyKnown_A	0	0	156586239	155768523	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	156586239	213	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1897879	213	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1897879	213	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	156586239	213	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.BusySrcReqChk_A	0	0	156586239	91429	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.DstReqKnown_A	0	0	1897879	1672071	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.SrcAckBusyChk_A	0	0	156586239	232	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.SrcBusyKnown_A	0	0	156586239	155768523	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	156586239	232	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1897879	232	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1897879	232	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	156586239	233	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.BusySrcReqChk_A	0	0	156586239	76322	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.DstReqKnown_A	0	0	1897879	1672071	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.SrcAckBusyChk_A	0	0	156586239	196	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.SrcBusyKnown_A	0	0	156586239	155768523	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	156586239	196	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1897879	196	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1897879	196	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	156586239	196	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.BusySrcReqChk_A	0	0	156586239	87169	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.DstReqKnown_A	0	0	1897879	1672071	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.SrcAckBusyChk_A	0	0	156586239	221	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.SrcBusyKnown_A	0	0	156586239	155768523	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	156586239	221	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1897879	221	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1897879	221	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	156586239	222	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.BusySrcReqChk_A	0	0	156586239	103186	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.DstReqKnown_A	0	0	1897879	1672071	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.SrcAckBusyChk_A	0	0	156586239	262	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.SrcBusyKnown_A	0	0	156586239	155768523	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	156586239	262	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1897879	262	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1897879	262	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	156586239	262	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.BusySrcReqChk_A	0	0	156586239	90682	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.DstReqKnown_A	0	0	1897879	1672071	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.SrcAckBusyChk_A	0	0	156586239	230	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.SrcBusyKnown_A	0	0	156586239	155768523	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	156586239	230	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1897879	230	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1897879	230	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	156586239	230	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.BusySrcReqChk_A	0	0	156586239	96222	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.DstReqKnown_A	0	0	1897879	1672071	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.SrcAckBusyChk_A	0	0	156586239	243	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.SrcBusyKnown_A	0	0	156586239	155768523	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	156586239	243	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1897879	243	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1897879	243	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	156586239	243	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.wePulse	0	0	156586239	146815	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.WakeDetectActiveAonKnown_A	0	0	1659087	1463027	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable0_A	0	0	529562655	8	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable1_A	0	0	529562655	24854582	0	104
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable2_A	0	0	529562655	65431653	0	90
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable3Rev_A	0	0	529562655	459422856	0	2032
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable3_A	0	0	529562655	459424741	0	1918
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexInstrIntgErrCheck_A	0	0	529562655	77	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexLoadRespIntgErrCheck_A	0	0	529562655	597	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmRegWeOnehotCheck_A	0	0	529562655	3	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.DataKnown_A	0	0	529562655	43568159	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.DepthKnown_A	0	0	529562655	529456194	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.RvalidKnown_A	0	0	529562655	529456194	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.WreadyKnown_A	0	0	529562655	529456194	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.DataKnown_A	0	0	529562655	36765969	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.DepthKnown_A	0	0	529562655	529456194	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.RvalidKnown_A	0	0	529562655	529456194	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.WreadyKnown_A	0	0	529562655	529456194	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.DataKnown_A	0	0	529562655	61148478	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.DepthKnown_A	0	0	529562655	529456194	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.RvalidKnown_A	0	0	529562655	529456194	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.WreadyKnown_A	0	0	529562655	529456194	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.DataKnown_A	0	0	529562655	47449343	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.DepthKnown_A	0	0	529562655	529456194	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.RvalidKnown_A	0	0	529562655	529456194	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.WreadyKnown_A	0	0	529562655	529456194	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.g_instr_intg_err_assert_signals.AssertConnected_A	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.g_pc_mismatch_alert_o_assert_signals.AssertConnected_A	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.g_rf_ecc_err_comb_assert_signals.AssertConnected_A	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A	0	0	529562655	134	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A	0	0	529562655	182	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.DontExceeedMaxReqs	0	0	529562655	43526171	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.u_cmd_intg_gen.PayMaxWidthCheck_A	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.u_rsp_chk.PayLoadWidthCheck	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.DontExceeedMaxReqs	0	0	529562655	61148478	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.u_cmd_intg_gen.PayMaxWidthCheck_A	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.u_rsp_chk.PayLoadWidthCheck	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.CheckHotOne_A	0	0	529562655	521978955	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.CheckNGreaterZero_A	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.GntImpliesReady_A	0	0	529562655	3192	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.GntImpliesValid_A	0	0	529562655	3192	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.GrantKnown_A	0	0	529562655	521978955	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.IdxKnown_A	0	0	529562655	521978955	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.IndexIsCorrect_A	0	0	529562655	3192	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.Priority_A	0	0	529562655	3192	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.ReadyAndValidImplyGrant_A	0	0	529562655	3192	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.ReqAndReadyImplyGrant_A	0	0	529562655	3192	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.ReqImpliesValid_A	0	0	529562655	3192	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.ValidKnown_A	0	0	529562655	521978955	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.gen_data_port_assertion.DataFlow_A	0	0	529562655	3192	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.DataOutputDiffFromPrev_A	0	0	528911906	101387994	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.DataOutputValid_A	0	0	529562655	4359	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	0	0	529562655	4359	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	0	0	529562655	4359	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckAckNeedsReq	0	0	529562655	4359	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckHoldReq	0	0	529562655	4359	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.CheckHotOne_A	0	0	529562655	521978955	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.CheckNGreaterZero_A	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.GntImpliesReady_A	0	0	529562655	5197	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.GntImpliesValid_A	0	0	529562655	5197	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.GrantKnown_A	0	0	529562655	521978955	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.IdxKnown_A	0	0	529562655	521978955	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.IndexIsCorrect_A	0	0	529562655	5197	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.Priority_A	0	0	529562655	5197	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.ReadyAndValidImplyGrant_A	0	0	529562655	5197	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.ReqAndReadyImplyGrant_A	0	0	529562655	5197	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.ReqImpliesValid_A	0	0	529562655	5197	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.ValidKnown_A	0	0	529562655	521978955	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.gen_data_port_assertion.DataFlow_A	0	0	529562655	5197	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.NumCopiesMustBeGreaterZero_A	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.OutputsKnown_A	0	0	529562655	529456194	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.gen_flops.OutputDelay_A	0	0	529562655	529448626	0	3048
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	0	0	529562655	32	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	0	0	529562655	32	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckAckNeedsReq	0	0	132255281	32	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckHoldReq	0	0	529562655	32	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.NumCopiesMustBeGreaterZero_A	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.OutputsKnown_A	0	0	529562655	529456194	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.gen_flops.OutputDelay_A	0	0	529562655	529448626	0	3048
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.en2addrHit	0	0	621707365	43801	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.reAfterRv	0	0	621707365	43801	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.rePulse	0	0	621707365	36180	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_chk.PayLoadWidthCheck	0	0	2936	2936	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.AllowedLatency_A	0	0	2936	2936	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.MatchedWidthAssert	0	0	2936	2936	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.u_err.dataWidthOnly32_A	0	0	2936	2936	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	2936	2936	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	2936	2936	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_rsp_intg_gen.DataWidthCheck_A	0	0	2936	2936	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	2936	2936	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.NotOverflowed_A	0	0	621707365	621584936	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.DataKnown_A	0	0	621707365	98910	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.DepthKnown_A	0	0	621707365	621584936	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.RvalidKnown_A	0	0	621707365	621584936	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.WreadyKnown_A	0	0	621707365	621584936	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	2936	2936	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.DataKnown_A	0	0	621707365	101809	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.DepthKnown_A	0	0	621707365	621584936	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.RvalidKnown_A	0	0	621707365	621584936	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.WreadyKnown_A	0	0	621707365	621584936	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	2936	2936	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A	0	0	621707365	51482	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A	0	0	621707365	621584936	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A	0	0	621707365	621584936	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A	0	0	621707365	621584936	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	2936	2936	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A	0	0	621707365	51482	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A	0	0	621707365	621584936	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A	0	0	621707365	621584936	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A	0	0	621707365	621584936	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	2936	2936	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A	0	0	621707365	47428	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A	0	0	621707365	621584936	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A	0	0	621707365	621584936	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A	0	0	621707365	621584936	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	2936	2936	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A	0	0	621707365	50327	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A	0	0	621707365	621584936	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A	0	0	621707365	621584936	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A	0	0	621707365	621584936	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	2936	2936	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.maxN	0	0	2936	2936	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.wePulse	0	0	621707365	7621	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_sim_win_rsp.u_intg_gen.DataWidthCheck_A	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_sim_win_rsp.u_intg_gen.PayLoadWidthCheck	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_rv_plic.FpvSecCmRegWeOnehotCheck_A	0	0	529562655	4	0	0
tb.dut.top_earlgrey.u_rv_plic.Irq0Tied_A	0	0	529562655	529456194	0	0
tb.dut.top_earlgrey.u_rv_plic.IrqKnownO_A	0	0	529562655	529456194	0	0
tb.dut.top_earlgrey.u_rv_plic.MsipKnownO_A	0	0	529562655	529456194	0	0
tb.dut.top_earlgrey.u_rv_plic.TlAReadyKnownO_A	0	0	529562655	529456194	0	0
tb.dut.top_earlgrey.u_rv_plic.TlDValidKnownO_A	0	0	529562655	529456194	0	0
tb.dut.top_earlgrey.u_rv_plic.gen_irq_id_known[0].IrqIdKnownO_A	0	0	529562655	529456194	0	0
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.MaxComputationInvalid_A	0	0	529562655	527726726	0	0
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.MaxComputation_A	0	0	529562655	1729468	0	0
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.MaxIndexComputationInvalid_A	0	0	529562655	527726726	0	0
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.MaxIndexComputation_A	0	0	529562655	1729468	0	0
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.NumSources_A	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.ValidInImpliesValidOut_A	0	0	529562655	529456194	0	0
tb.dut.top_earlgrey.u_rv_plic.onehot0Claim	0	0	529562655	529456194	0	0
tb.dut.top_earlgrey.u_rv_plic.onehot0Complete	0	0	529562655	529456194	0	0
tb.dut.top_earlgrey.u_rv_plic.u_reg.en2addrHit	0	0	621707365	247930	0	0
tb.dut.top_earlgrey.u_rv_plic.u_reg.reAfterRv	0	0	621707365	247930	0	0
tb.dut.top_earlgrey.u_rv_plic.u_reg.rePulse	0	0	621707365	180235	0	0
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_chk.PayLoadWidthCheck	0	0	2936	2936	0	0
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.AllowedLatency_A	0	0	2936	2936	0	0
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.MatchedWidthAssert	0	0	2936	2936	0	0
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	2936	2936	0	0
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	2936	2936	0	0
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	2936	2936	0	0
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	2936	2936	0	0
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	2936	2936	0	0
tb.dut.top_earlgrey.u_rv_plic.u_reg.wePulse	0	0	621707365	67695	0	0
tb.dut.top_earlgrey.u_sensor_ctrl_aon.FpvSecCmRegWeOnehotCheck_A	0	0	132255281	4	0	0
tb.dut.top_earlgrey.u_sensor_ctrl_aon.NumAlertsMatch_A	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_init_intr.IntrTKind_A	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_io_intr.IntrTKind_A	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.en2addrHit	0	0	132255281	5512	0	0
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.reAfterRv	0	0	132255281	5512	0	0
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.rePulse	0	0	132255281	3986	0	0
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_chk.PayLoadWidthCheck	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.AllowedLatency_A	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.MatchedWidthAssert	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1025	1025	0	0
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.wePulse	0	0	132255281	1526	0	0
tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown0	0	0	48	36	0	0
tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown1	0	0	114	97	0	0
tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic.selKnown0	0	0	4611	4593	0	0
tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic.selKnown1	0	0	2967	2947	0	0
tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown0	0	0	49	37	0	0
tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown1	0	0	111	93	0	0
tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic.selKnown0	0	0	4604	4585	0	0
tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic.selKnown1	0	0	119	101	0	0
tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown0	0	0	69	46	0	0
tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown1	0	0	131	116	0	0
tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic.selKnown0	0	0	4814	4791	0	0
tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic.selKnown1	0	0	499	485	0	0
tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown0	0	0	69	47	0	0
tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown1	0	0	125	107	0	0
tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic.selKnown0	0	0	4802	4779	0	0
tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic.selKnown1	0	0	412	398	0	0
tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_dio_pads[5].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_dio_pads[8].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic.selKnown0	0	0	158	129	0	0
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic.selKnown1	0	0	4488	4457	0	0
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown0	0	0	154	125	0	0
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown1	0	0	4479	4448	0	0
tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic.selKnown0	0	0	548	527	0	0
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic.selKnown1	0	0	29842	29807	0	0
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown0	0	0	541	520	0	0
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown1	0	0	29839	29804	0	0
tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic.selKnown0	0	0	587	543	0	0
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic.selKnown1	0	0	29840	29804	0	0
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown0	0	0	582	538	0	0
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown1	0	0	29841	29805	0	0
tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[34].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[43].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[44].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[45].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[46].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic.selKnown0	0	0	2969	2946	0	0
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic.selKnown1	0	0	4478	4450	0	0
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown0	0	0	2970	2947	0	0
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown1	0	0	4478	4450	0	0
tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1025	1025	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.top_earlgrey.u_pinmux_aon.PwrMgrStrapSampleOnce1_A	0	0	133603549	0	0	977
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.DftTapOff0_A	0	0	133603549	40829733	0	296
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnClear_A	0	0	133603549	11938667	0	15
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnSetRev0_A	0	0	133603549	1454	0	108
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnSetRev1_A	0	0	133603549	1454	0	108
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.RvTapOff0_A	0	0	133603549	264	0	216
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en.gen_flops.OutputDelay_A	0	0	133603549	132904569	0	3054
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.OutputDelay_A	0	0	133603549	132904569	0	3054
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en.gen_flops.OutputDelay_A	0	0	133603549	132904569	0	3054
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en.gen_flops.OutputDelay_A	0	0	133603549	132904569	0	3054
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	1897879	39	0	986
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable1_A	0	0	529562655	24854582	0	104
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable2_A	0	0	529562655	65431653	0	90
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable3Rev_A	0	0	529562655	459422856	0	2032
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable3_A	0	0	529562655	459424741	0	1918
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	529562655	0	0	1016
tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.gen_flops.OutputDelay_A	0	0	529562655	529448626	0	3048
tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.gen_flops.OutputDelay_A	0	0	529562655	529448626	0	3048

Assertions Excluded:

ASSERTIONS	CATEGORY	SEVERITY	EXCLUSION	SRC
tb.dut.u_padring.gen_dio_pads[0].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	Excluded
tb.dut.u_padring.gen_dio_pads[3].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	Excluded
tb.dut.u_padring.gen_dio_pads[4].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	Excluded
tb.dut.u_padring.gen_dio_pads[6].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	Excluded
tb.dut.u_padring.gen_dio_pads[7].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	Excluded