Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.02	95.41	93.69	95.42		94.52	97.53	99.58

Total tests in report: 2936

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
39.66	39.66	44.82	44.82	42.89	42.89	32.71	32.71			57.90	57.90	59.27	59.27	0.39	0.39	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2536795900
48.98	9.32	50.16	5.35	56.75	13.86	32.99	0.28			68.11	10.21	84.44	25.17	1.42	1.03	/workspace/coverage/cover_reg_top/17.chip_csr_rw.2376180421
55.25	6.27	57.86	7.70	59.33	2.58	35.05	2.06			68.69	0.58	84.44	0.00	26.12	24.70	/workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.3780665304
61.29	6.04	70.44	12.57	67.80	8.47	38.86	3.81			80.11	11.42	84.44	0.00	26.12	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.1052881397
64.90	3.61	74.97	4.53	70.47	2.67	47.41	8.55			81.97	1.87	88.46	4.02	26.12	0.00	/workspace/coverage/default/2.chip_sw_power_virus.2301790302
68.02	3.12	77.64	2.67	71.21	0.73	51.86	4.46			82.18	0.21	88.46	0.00	36.75	10.63	/workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.4175929110
70.90	2.88	77.64	0.00	71.21	0.00	51.86	0.00			82.18	0.00	88.46	0.00	54.02	17.27	/workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.2624286265
73.40	2.51	82.44	4.80	75.02	3.82	55.07	3.20			83.82	1.64	90.03	1.57	54.02	0.00	/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2519792807
75.63	2.23	82.44	0.00	75.02	0.00	68.46	13.39			83.82	0.00	90.03	0.00	54.02	0.00	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.1103132384
77.65	2.02	82.44	0.00	75.02	0.00	68.46	0.00			83.82	0.00	90.03	0.00	66.11	12.09	/workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.2522754083
79.54	1.89	84.69	2.25	77.42	2.39	72.67	4.21			85.58	1.76	90.73	0.70	66.11	0.00	/workspace/coverage/default/0.rom_e2e_self_hash.631317007
80.99	1.45	84.85	0.15	77.52	0.10	80.80	8.13			85.75	0.17	90.91	0.17	66.11	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.1268459266
82.41	1.42	87.24	2.39	80.53	3.01	80.93	0.13			88.75	3.00	90.91	0.00	66.11	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.744288096
83.81	1.40	87.24	0.00	80.89	0.36	80.93	0.00			88.75	0.00	90.91	0.00	74.13	8.01	/workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.3438058315
84.93	1.12	87.24	0.00	80.89	0.00	80.93	0.00			88.75	0.00	90.91	0.00	80.86	6.73	/workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.2410870449
85.88	0.95	87.24	0.00	80.89	0.00	80.93	0.00			88.75	0.00	90.91	0.00	86.56	5.70	/workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.630693004
86.70	0.82	87.96	0.72	81.06	0.17	80.94	0.01			88.93	0.18	94.76	3.85	86.56	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.4261417475
87.51	0.81	88.99	1.03	81.85	0.79	81.38	0.44			89.91	0.98	96.33	1.57	86.61	0.05	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3233584783
88.26	0.75	89.71	0.72	84.26	2.41	81.49	0.11			90.55	0.63	96.33	0.00	87.22	0.61	/workspace/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.202691975
88.94	0.68	89.71	0.00	84.56	0.30	81.49	0.00			90.56	0.02	96.33	0.00	90.96	3.75	/workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.3225332040
89.58	0.65	90.93	1.22	85.56	1.00	81.98	0.49			91.73	1.17	96.33	0.00	90.96	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.563562802
90.10	0.52	91.74	0.81	86.34	0.78	82.92	0.94			92.28	0.54	96.33	0.00	91.02	0.06	/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3333714150
90.60	0.50	91.79	0.05	86.40	0.06	83.93	1.01			92.28	0.00	96.33	0.00	92.88	1.86	/workspace/coverage/default/1.chip_sw_alert_test.309146927
90.99	0.39	91.79	0.00	86.55	0.16	83.93	0.00			92.31	0.03	96.33	0.00	95.05	2.17	/workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.380875569
91.38	0.38	91.79	0.00	86.55	0.00	86.23	2.31			92.31	0.00	96.33	0.00	95.05	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.3619033627
91.75	0.37	92.38	0.59	86.58	0.03	87.78	1.54			92.31	0.00	96.33	0.00	95.14	0.08	/workspace/coverage/cover_reg_top/43.xbar_error_random.2081958047
92.04	0.29	92.88	0.50	87.06	0.48	88.05	0.27			92.77	0.46	96.33	0.00	95.14	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.2061412059
92.32	0.28	92.88	0.01	88.72	1.66	88.05	0.00			92.77	0.00	96.33	0.00	95.17	0.04	/workspace/coverage/cover_reg_top/14.chip_tl_errors.3419760826
92.59	0.27	92.91	0.03	88.82	0.11	89.33	1.28			92.83	0.06	96.50	0.17	95.17	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2769736527
92.85	0.26	93.49	0.57	89.15	0.33	89.72	0.39			93.08	0.25	96.50	0.00	95.17	0.00	/workspace/coverage/default/1.chip_sw_gpio.447061239
93.11	0.26	93.49	0.00	89.15	0.00	89.72	0.00			93.08	0.00	96.50	0.00	96.71	1.54	/workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.1055286992
93.27	0.16	93.49	0.00	89.21	0.06	89.72	0.00			93.10	0.02	96.50	0.00	97.60	0.89	/workspace/coverage/cover_reg_top/9.xbar_random_large_delays.4048307746
93.43	0.16	93.53	0.05	89.61	0.40	89.77	0.05			93.53	0.44	96.50	0.00	97.60	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3352331357
93.58	0.15	93.64	0.11	90.38	0.77	89.78	0.01			93.55	0.02	96.50	0.00	97.60	0.00	/workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.3383497059
93.72	0.15	93.85	0.21	90.70	0.32	90.13	0.35			93.55	0.00	96.50	0.00	97.60	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4071432941
93.86	0.14	93.90	0.06	90.71	0.01	90.89	0.76			93.56	0.01	96.50	0.00	97.60	0.00	/workspace/coverage/default/0.rom_e2e_jtag_debug_rma.1979412028
94.00	0.13	93.91	0.01	90.72	0.01	91.68	0.79			93.56	0.00	96.50	0.00	97.60	0.00	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.3351795022
94.11	0.12	93.91	0.00	90.72	0.00	92.34	0.66			93.56	0.00	96.50	0.00	97.64	0.04	/workspace/coverage/default/1.chip_sw_alert_handler_entropy.1755515773
94.21	0.10	93.91	0.00	90.72	0.00	92.95	0.61			93.56	0.00	96.50	0.00	97.64	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.1673521649
94.31	0.09	94.09	0.18	90.93	0.22	92.95	0.00			93.73	0.17	96.50	0.00	97.64	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.2777643513
94.39	0.09	94.09	0.00	91.46	0.53	92.95	0.00			93.73	0.00	96.50	0.00	97.64	0.00	/workspace/coverage/cover_reg_top/5.chip_tl_errors.1791881923
94.48	0.08	94.09	0.00	91.46	0.00	93.44	0.50			93.73	0.00	96.50	0.00	97.64	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1951031364
94.55	0.07	94.09	0.00	91.63	0.17	93.44	0.00			93.73	0.00	96.50	0.00	97.90	0.26	/workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.3484321677
94.62	0.07	94.23	0.14	91.73	0.10	93.52	0.08			93.83	0.11	96.50	0.00	97.90	0.00	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.2873501006
94.68	0.06	94.23	0.00	91.80	0.07	93.52	0.00			93.83	0.00	96.50	0.00	98.20	0.31	/workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.562270205
94.74	0.06	94.23	0.00	91.96	0.16	93.52	0.01			94.01	0.18	96.50	0.00	98.20	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.573093126
94.79	0.06	94.23	0.00	91.96	0.00	93.86	0.34			94.01	0.00	96.50	0.00	98.20	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.428692315
94.85	0.05	94.24	0.01	91.99	0.03	93.94	0.08			94.03	0.02	96.68	0.17	98.21	0.01	/workspace/coverage/default/46.chip_sw_all_escalation_resets.1005373677
94.90	0.05	94.29	0.06	92.03	0.04	93.94	0.00			94.05	0.02	96.85	0.17	98.23	0.01	/workspace/coverage/default/9.chip_sw_all_escalation_resets.3327521939
94.94	0.05	94.35	0.06	92.10	0.07	94.01	0.07			94.13	0.07	96.85	0.00	98.23	0.00	/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3743576987
94.99	0.04	94.38	0.03	92.12	0.02	94.02	0.01			94.15	0.02	97.03	0.17	98.23	0.00	/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.2775500023
95.03	0.04	94.38	0.00	92.12	0.00	94.27	0.25			94.15	0.00	97.03	0.00	98.23	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.3130807236
95.07	0.04	94.39	0.01	92.15	0.02	94.27	0.00			94.17	0.02	97.20	0.17	98.24	0.01	/workspace/coverage/default/63.chip_sw_all_escalation_resets.1135087748
95.11	0.04	94.39	0.01	92.16	0.01	94.27	0.01			94.18	0.01	97.38	0.17	98.25	0.01	/workspace/coverage/default/3.chip_sw_all_escalation_resets.961375599
95.14	0.03	94.39	0.00	92.26	0.10	94.27	0.00			94.20	0.02	97.38	0.00	98.33	0.08	/workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.2188087224
95.17	0.03	94.46	0.07	92.26	0.00	94.37	0.10			94.21	0.01	97.38	0.00	98.33	0.00	/workspace/coverage/default/2.chip_tap_straps_rma.3358582567
95.20	0.03	94.46	0.00	92.26	0.00	94.37	0.00			94.21	0.00	97.55	0.17	98.33	0.00	/workspace/coverage/default/1.chip_sw_data_integrity_escalation.926362558
95.22	0.03	94.53	0.07	92.28	0.03	94.39	0.01			94.26	0.05	97.55	0.00	98.33	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1838298982
95.25	0.03	94.53	0.00	92.44	0.16	94.39	0.00			94.26	0.00	97.55	0.00	98.33	0.00	/workspace/coverage/cover_reg_top/21.chip_tl_errors.3795466751
95.28	0.03	94.55	0.01	92.46	0.02	94.50	0.12			94.26	0.01	97.55	0.00	98.33	0.00	/workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.3727413070
95.30	0.02	94.55	0.00	92.46	0.00	94.65	0.15			94.26	0.00	97.55	0.00	98.33	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1805391497
95.32	0.02	94.61	0.07	92.51	0.05	94.65	0.00			94.30	0.03	97.55	0.00	98.33	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.3883211567
95.35	0.02	94.68	0.07	92.56	0.05	94.65	0.00			94.33	0.03	97.55	0.00	98.33	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.3776108894
95.37	0.02	94.68	0.00	92.59	0.04	94.65	0.00			94.33	0.00	97.55	0.00	98.44	0.11	/workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.1137925420
95.40	0.02	94.68	0.01	92.65	0.06	94.65	0.00			94.39	0.06	97.55	0.00	98.44	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.2001896236
95.42	0.02	94.69	0.01	92.70	0.05	94.70	0.05			94.42	0.02	97.55	0.00	98.44	0.00	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.35417885
95.44	0.02	94.71	0.02	92.72	0.01	94.79	0.09			94.43	0.01	97.55	0.00	98.44	0.00	/workspace/coverage/default/0.chip_sw_usbdev_dpi.4037418851
95.46	0.02	94.71	0.00	92.72	0.01	94.79	0.00			94.43	0.00	97.55	0.00	98.55	0.12	/workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.3368572404
95.48	0.02	94.71	0.00	92.82	0.10	94.79	0.00			94.43	0.00	97.55	0.00	98.55	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.3349809230
95.49	0.02	94.71	0.00	92.91	0.09	94.79	0.00			94.43	0.00	97.55	0.00	98.55	0.00	/workspace/coverage/cover_reg_top/20.chip_tl_errors.2324920505
95.51	0.01	94.71	0.00	92.91	0.00	94.88	0.08			94.43	0.00	97.55	0.00	98.55	0.00	/workspace/coverage/default/1.chip_sw_inject_scramble_seed.3612869683
95.52	0.01	94.71	0.00	92.94	0.03	94.88	0.00			94.44	0.02	97.55	0.00	98.59	0.04	/workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.2616213417
95.53	0.01	94.71	0.00	92.94	0.00	94.95	0.07			94.44	0.00	97.55	0.00	98.59	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.2377337521
95.54	0.01	94.71	0.00	93.01	0.07	94.95	0.00			94.44	0.00	97.55	0.00	98.59	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.2947213377
95.55	0.01	94.71	0.00	93.02	0.01	95.01	0.06			94.44	0.00	97.55	0.00	98.59	0.00	/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.1990980194
95.56	0.01	94.71	0.00	93.03	0.01	95.06	0.05			94.44	0.00	97.55	0.00	98.59	0.00	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1810688948
95.57	0.01	94.71	0.00	93.06	0.03	95.06	0.00			94.44	0.00	97.55	0.00	98.61	0.02	/workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.1068396343
95.58	0.01	94.71	0.00	93.11	0.05	95.06	0.00			94.44	0.00	97.55	0.00	98.61	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.3480323607
95.59	0.01	94.73	0.02	93.12	0.01	95.07	0.01			94.46	0.02	97.55	0.00	98.61	0.00	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.110569182
95.60	0.01	94.75	0.02	93.12	0.01	95.07	0.01			94.47	0.02	97.55	0.00	98.61	0.00	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.824479562
95.61	0.01	94.78	0.02	93.13	0.01	95.07	0.01			94.49	0.02	97.55	0.00	98.61	0.00	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.4033834848
95.61	0.01	94.79	0.02	93.16	0.02	95.07	0.00			94.49	0.00	97.55	0.00	98.61	0.00	/workspace/coverage/cover_reg_top/13.chip_csr_rw.142611476
95.62	0.01	94.79	0.00	93.17	0.02	95.07	0.00			94.49	0.00	97.55	0.00	98.64	0.02	/workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.166502729
95.63	0.01	94.80	0.01	93.20	0.03	95.08	0.01			94.49	0.00	97.55	0.00	98.64	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.3290495346
95.63	0.01	94.80	0.00	93.20	0.00	95.12	0.04			94.49	0.00	97.55	0.00	98.64	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3868089673
95.64	0.01	94.80	0.01	93.22	0.02	95.13	0.01			94.50	0.01	97.55	0.00	98.64	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.2891175305
95.65	0.01	94.80	0.00	93.25	0.04	95.13	0.00			94.50	0.00	97.55	0.00	98.64	0.00	/workspace/coverage/cover_reg_top/18.chip_tl_errors.4010559849
95.65	0.01	94.80	0.00	93.29	0.04	95.13	0.00			94.50	0.00	97.55	0.00	98.64	0.00	/workspace/coverage/cover_reg_top/22.xbar_stress_all.675024568
95.66	0.01	94.80	0.00	93.29	0.00	95.13	0.00			94.50	0.00	97.55	0.00	98.67	0.04	/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.3280683090
95.66	0.01	94.80	0.00	93.29	0.00	95.13	0.00			94.50	0.00	97.55	0.00	98.71	0.04	/workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.1148044299
95.67	0.01	94.80	0.00	93.31	0.02	95.14	0.01			94.50	0.00	97.55	0.00	98.71	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.259912819
95.67	0.01	94.80	0.00	93.31	0.00	95.16	0.02			94.50	0.00	97.55	0.00	98.72	0.01	/workspace/coverage/default/68.chip_sw_all_escalation_resets.1862804518
95.68	0.01	94.80	0.00	93.31	0.00	95.20	0.03			94.50	0.00	97.55	0.00	98.72	0.00	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.997687252
95.69	0.01	94.80	0.00	93.31	0.00	95.23	0.03			94.50	0.00	97.55	0.00	98.72	0.00	/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.1626192496
95.69	0.01	94.80	0.00	93.34	0.03	95.23	0.00			94.50	0.00	97.55	0.00	98.72	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.2415545563
95.70	0.01	94.80	0.00	93.37	0.03	95.23	0.00			94.50	0.00	97.55	0.00	98.72	0.00	/workspace/coverage/cover_reg_top/94.xbar_access_same_device.639165557
95.70	0.01	94.80	0.00	93.37	0.00	95.26	0.03			94.50	0.00	97.55	0.00	98.72	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2528156664
95.70	0.01	94.80	0.00	93.37	0.01	95.26	0.00			94.50	0.00	97.55	0.00	98.74	0.02	/workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.3022238669
95.71	0.01	94.80	0.00	93.40	0.02	95.26	0.00			94.50	0.00	97.55	0.00	98.74	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx.2624168317
95.71	0.01	94.80	0.00	93.40	0.00	95.26	0.00			94.50	0.00	97.55	0.00	98.77	0.02	/workspace/coverage/default/2.chip_sw_all_escalation_resets.2920841388
95.72	0.01	94.80	0.00	93.42	0.02	95.26	0.00			94.50	0.00	97.55	0.00	98.77	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.1419942717
95.72	0.01	94.80	0.00	93.44	0.02	95.26	0.00			94.50	0.00	97.55	0.00	98.77	0.00	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.647858988
95.72	0.01	94.80	0.00	93.44	0.00	95.27	0.01			94.50	0.00	97.55	0.00	98.78	0.01	/workspace/coverage/default/35.chip_sw_all_escalation_resets.247131785
95.73	0.01	94.80	0.00	93.44	0.00	95.29	0.02			94.50	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3375884628
95.73	0.01	94.80	0.00	93.46	0.01	95.29	0.01			94.50	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3007173809
95.73	0.01	94.80	0.00	93.46	0.00	95.31	0.02			94.50	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.2547494354
95.74	0.01	94.80	0.00	93.47	0.02	95.31	0.00			94.50	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/cover_reg_top/93.xbar_stress_all.2097084766
95.74	0.01	94.80	0.00	93.49	0.02	95.31	0.00			94.50	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.2884132336
95.74	0.01	94.80	0.00	93.49	0.00	95.31	0.01			94.50	0.00	97.55	0.00	98.79	0.01	/workspace/coverage/default/33.chip_sw_all_escalation_resets.3081493981
95.74	0.01	94.82	0.01	93.49	0.00	95.32	0.01			94.50	0.00	97.55	0.00	98.79	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.978939230
95.75	0.01	94.82	0.00	93.49	0.00	95.32	0.01			94.51	0.01	97.55	0.00	98.79	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.3998223420
95.75	0.01	94.82	0.00	93.51	0.01	95.32	0.00			94.51	0.00	97.55	0.00	98.79	0.00	/workspace/coverage/cover_reg_top/0.chip_tl_errors.2283241230
95.75	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	98.80	0.01	/workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.1595123363
95.75	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	98.81	0.01	/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.346083520
95.76	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	98.83	0.01	/workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.1581280201
95.76	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	98.84	0.01	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.4949883
95.76	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	98.85	0.01	/workspace/coverage/default/0.chip_sw_all_escalation_resets.2813903891
95.76	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	98.86	0.01	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2353668243
95.76	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	98.87	0.01	/workspace/coverage/default/1.chip_sw_all_escalation_resets.1769799688
95.76	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	98.88	0.01	/workspace/coverage/default/10.chip_sw_all_escalation_resets.990033173
95.77	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	98.90	0.01	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2135906242
95.77	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	98.91	0.01	/workspace/coverage/default/11.chip_sw_all_escalation_resets.3150695126
95.77	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	98.92	0.01	/workspace/coverage/default/12.chip_sw_all_escalation_resets.2014071856
95.77	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	98.93	0.01	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.3599563810
95.77	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	98.94	0.01	/workspace/coverage/default/13.chip_sw_all_escalation_resets.893793121
95.78	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	98.95	0.01	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.1617482390
95.78	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	98.97	0.01	/workspace/coverage/default/14.chip_sw_all_escalation_resets.1437889707
95.78	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	98.98	0.01	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.2034913160
95.78	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	98.99	0.01	/workspace/coverage/default/16.chip_sw_all_escalation_resets.454834746
95.78	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.00	0.01	/workspace/coverage/default/18.chip_sw_all_escalation_resets.295228608
95.79	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.01	0.01	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1538374277
95.79	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.02	0.01	/workspace/coverage/default/20.chip_sw_all_escalation_resets.175063776
95.79	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.04	0.01	/workspace/coverage/default/21.chip_sw_all_escalation_resets.2107607942
95.79	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.05	0.01	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1208462223
95.79	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.06	0.01	/workspace/coverage/default/22.chip_sw_all_escalation_resets.2051194470
95.80	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.07	0.01	/workspace/coverage/default/23.chip_sw_all_escalation_resets.4040688611
95.80	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.08	0.01	/workspace/coverage/default/24.chip_sw_all_escalation_resets.3386310764
95.80	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.10	0.01	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.1115622011
95.80	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.11	0.01	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3664962175
95.80	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.12	0.01	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.1871038595
95.81	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.13	0.01	/workspace/coverage/default/27.chip_sw_all_escalation_resets.74542998
95.81	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.14	0.01	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1347815979
95.81	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.15	0.01	/workspace/coverage/default/29.chip_sw_all_escalation_resets.3528051264
95.81	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.17	0.01	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.1107699067
95.81	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.18	0.01	/workspace/coverage/default/34.chip_sw_all_escalation_resets.421417772
95.82	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.19	0.01	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2325551934
95.82	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.20	0.01	/workspace/coverage/default/36.chip_sw_all_escalation_resets.2289522778
95.82	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.21	0.01	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3681299786
95.82	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.22	0.01	/workspace/coverage/default/37.chip_sw_all_escalation_resets.390945012
95.82	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.24	0.01	/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3353971258
95.83	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.25	0.01	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.849593276
95.83	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.26	0.01	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2393702221
95.83	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.27	0.01	/workspace/coverage/default/42.chip_sw_all_escalation_resets.261392524
95.83	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.28	0.01	/workspace/coverage/default/43.chip_sw_all_escalation_resets.2066010830
95.83	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.30	0.01	/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3626754585
95.84	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.31	0.01	/workspace/coverage/default/47.chip_sw_all_escalation_resets.2627059667
95.84	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.32	0.01	/workspace/coverage/default/48.chip_sw_all_escalation_resets.3382855967
95.84	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.33	0.01	/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2909677937
95.84	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.34	0.01	/workspace/coverage/default/49.chip_sw_all_escalation_resets.2598349751
95.84	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.35	0.01	/workspace/coverage/default/5.chip_sw_all_escalation_resets.2508484135
95.85	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.37	0.01	/workspace/coverage/default/52.chip_sw_all_escalation_resets.209904167
95.85	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.38	0.01	/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2184645461
95.85	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.39	0.01	/workspace/coverage/default/55.chip_sw_all_escalation_resets.2046463891
95.85	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.40	0.01	/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.162290383
95.85	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.41	0.01	/workspace/coverage/default/59.chip_sw_all_escalation_resets.3818538073
95.85	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.42	0.01	/workspace/coverage/default/6.chip_sw_all_escalation_resets.69576999
95.86	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.44	0.01	/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.403610505
95.86	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.45	0.01	/workspace/coverage/default/62.chip_sw_all_escalation_resets.3820406273
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95.86	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.47	0.01	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1975495072
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95.87	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.49	0.01	/workspace/coverage/default/78.chip_sw_all_escalation_resets.1196388720
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95.87	0.01	94.82	0.00	93.51	0.00	95.32	0.00			94.51	0.00	97.55	0.00	99.54	0.01	/workspace/coverage/default/84.chip_sw_all_escalation_resets.2514333895
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95.88	0.01	94.82	0.00	93.52	0.01	95.32	0.00			94.51	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/63.xbar_access_same_device.918909460
95.88	0.01	94.82	0.00	93.53	0.01	95.32	0.00			94.51	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.3982754438
95.89	0.01	94.82	0.00	93.54	0.01	95.32	0.00			94.51	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_gpio.651461202
95.89	0.01	94.82	0.00	93.55	0.01	95.32	0.00			94.51	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.2327846070
95.89	0.01	94.82	0.00	93.56	0.01	95.32	0.00			94.51	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2621897566
95.89	0.01	94.82	0.00	93.57	0.01	95.32	0.00			94.51	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/2.chip_sw_gpio.876671518
95.89	0.01	94.82	0.01	93.57	0.00	95.33	0.01			94.51	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/50.chip_sw_all_escalation_resets.1785419207
95.89	0.01	94.83	0.01	93.57	0.01	95.33	0.00			94.51	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.3953630139
95.90	0.01	94.83	0.00	93.57	0.00	95.34	0.01			94.51	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2774480180
95.90	0.01	94.83	0.00	93.57	0.00	95.35	0.01			94.51	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2009081526
95.90	0.01	94.83	0.00	93.57	0.00	95.36	0.01			94.51	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.1359244189
95.90	0.01	94.83	0.00	93.57	0.00	95.36	0.00			94.52	0.01	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2401861253
95.90	0.01	94.83	0.00	93.58	0.01	95.36	0.00			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/1.chip_tl_errors.2871753011
95.90	0.01	94.83	0.00	93.59	0.01	95.36	0.00			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/13.xbar_stress_all.811910739
95.90	0.01	94.83	0.00	93.59	0.01	95.36	0.00			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.1465398104
95.91	0.01	94.83	0.00	93.60	0.01	95.36	0.00			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.1343950971
95.91	0.01	94.83	0.00	93.61	0.01	95.36	0.00			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.2398345995
95.91	0.01	94.83	0.00	93.61	0.01	95.36	0.00			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.3291653538
95.91	0.01	94.83	0.00	93.62	0.01	95.36	0.00			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_pattgen_ios.418664139
95.91	0.01	94.83	0.00	93.63	0.01	95.36	0.00			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.1665760267
95.91	0.01	94.83	0.00	93.63	0.00	95.37	0.01			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2447803298
95.91	0.01	94.83	0.01	93.63	0.00	95.37	0.01			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2257414984
95.91	0.01	94.83	0.00	93.63	0.00	95.37	0.01			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.1152240705
95.91	0.01	94.83	0.00	93.63	0.00	95.38	0.01			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.3326582886
95.91	0.01	94.83	0.00	93.63	0.00	95.38	0.01			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.3121176905
95.92	0.01	94.83	0.00	93.63	0.00	95.39	0.01			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.1008273200
95.92	0.01	94.83	0.00	93.63	0.00	95.39	0.01			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.1649898943
95.92	0.01	94.83	0.00	93.63	0.00	95.40	0.01			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.2671977538
95.92	0.01	94.83	0.00	93.63	0.00	95.40	0.01			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3753536472
95.92	0.01	94.83	0.00	93.63	0.00	95.41	0.01			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3027207419
95.92	0.01	94.83	0.00	93.63	0.00	95.41	0.01			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1611787943
95.92	0.01	94.83	0.00	93.63	0.01	95.41	0.00			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/10.chip_tl_errors.77741650
95.92	0.01	94.83	0.00	93.64	0.01	95.41	0.00			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.4180564015
95.92	0.01	94.83	0.00	93.64	0.01	95.41	0.00			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.2510854585
95.92	0.01	94.83	0.00	93.64	0.01	95.41	0.00			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.2530078326
95.92	0.01	94.83	0.00	93.65	0.01	95.41	0.00			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.322751486
95.92	0.01	94.83	0.00	93.65	0.01	95.41	0.00			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.3236511590
95.92	0.01	94.83	0.00	93.65	0.01	95.41	0.00			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.1854080199
95.92	0.01	94.83	0.00	93.66	0.01	95.41	0.00			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.1262958954
95.92	0.01	94.83	0.00	93.66	0.01	95.41	0.00			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.1264829764
95.92	0.01	94.83	0.00	93.66	0.01	95.41	0.00			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.3312455253
95.93	0.01	94.83	0.00	93.67	0.01	95.41	0.00			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.3800360393
95.93	0.01	94.83	0.00	93.67	0.01	95.41	0.00			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.50507073
95.93	0.01	94.83	0.00	93.67	0.01	95.41	0.00			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1907786416
95.93	0.01	94.83	0.00	93.68	0.01	95.41	0.00			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.4150621040
95.93	0.01	94.83	0.00	93.68	0.01	95.41	0.00			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.3595989887
95.93	0.01	94.83	0.00	93.69	0.01	95.41	0.00			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.1663438445
95.93	0.01	94.83	0.00	93.69	0.01	95.41	0.00			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.3005503281
95.93	0.01	94.83	0.00	93.69	0.00	95.41	0.01			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_aon_timer_irq.2652663820
95.93	0.01	94.83	0.00	93.69	0.00	95.42	0.01			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.490261027
95.93	0.01	94.83	0.00	93.69	0.00	95.42	0.01			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.1195621945
95.93	0.01	94.83	0.00	93.69	0.00	95.42	0.01			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.4249608191
95.93	0.01	94.83	0.00	93.69	0.00	95.42	0.01			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1648213818
95.93	0.01	94.83	0.00	93.69	0.00	95.42	0.01			94.52	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1874760926

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.3001716153
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.1890275503
/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.3703302119
/workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.2059547865
/workspace/coverage/cover_reg_top/0.chip_csr_rw.2847247442
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.2676307457
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.1685876724
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.2122805826
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2993422540
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.425562348
/workspace/coverage/cover_reg_top/0.xbar_error_random.1626068531
/workspace/coverage/cover_reg_top/0.xbar_random.3617849871
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.625209162
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.1546735760
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.1466154020
/workspace/coverage/cover_reg_top/0.xbar_same_source.560180642
/workspace/coverage/cover_reg_top/0.xbar_smoke.2927652791
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.2016415493
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2889934309
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3597842443
/workspace/coverage/cover_reg_top/0.xbar_stress_all.1432001462
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.3571772283
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.2250084764
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.4221244408
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.3324543258
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.850663971
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.2843671510
/workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.2213302048
/workspace/coverage/cover_reg_top/1.chip_csr_rw.79521497
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.4210212559
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2358830370
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.8347940
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.3781596602
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.384244872
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1801802153
/workspace/coverage/cover_reg_top/1.xbar_error_random.2080095668
/workspace/coverage/cover_reg_top/1.xbar_random.105486955
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2352759092
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.2655598715
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.3471520567
/workspace/coverage/cover_reg_top/1.xbar_same_source.1044679930
/workspace/coverage/cover_reg_top/1.xbar_smoke.851963550
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.3423954903
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.440753967
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.334201446
/workspace/coverage/cover_reg_top/1.xbar_stress_all.505640098
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.76739295
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.622804819
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.4039867920
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.594723290
/workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.1113051540
/workspace/coverage/cover_reg_top/10.chip_csr_rw.3207351733
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.3057370140
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.560356336
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.209510513
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.959533895
/workspace/coverage/cover_reg_top/10.xbar_error_random.1206604300
/workspace/coverage/cover_reg_top/10.xbar_random.2591902747
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.3591551891
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.1547774311
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.2321115196
/workspace/coverage/cover_reg_top/10.xbar_same_source.3369924713
/workspace/coverage/cover_reg_top/10.xbar_smoke.2109476649
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.2553066364
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.179693749
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.905608668
/workspace/coverage/cover_reg_top/10.xbar_stress_all.2599458265
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.156557621
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1660425905
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1350399638
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.1568918480
/workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.1247807270
/workspace/coverage/cover_reg_top/11.chip_csr_rw.2679440864
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.489851921
/workspace/coverage/cover_reg_top/11.chip_tl_errors.1732813957
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.3470031773
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3531043154
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.1361106812
/workspace/coverage/cover_reg_top/11.xbar_error_random.2914092419
/workspace/coverage/cover_reg_top/11.xbar_random.3605197869
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3534519161
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.88424031
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.2340922749
/workspace/coverage/cover_reg_top/11.xbar_same_source.4167797201
/workspace/coverage/cover_reg_top/11.xbar_smoke.3693859219
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.2892073218
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.1671145446
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.310934523
/workspace/coverage/cover_reg_top/11.xbar_stress_all.2073888690
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.641749841
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2408493475
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.2660273687
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.2807177332
/workspace/coverage/cover_reg_top/12.chip_csr_rw.1674300398
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.2127231820
/workspace/coverage/cover_reg_top/12.chip_tl_errors.1570548879
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.739826104
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2424580795
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.555963620
/workspace/coverage/cover_reg_top/12.xbar_error_random.1664152732
/workspace/coverage/cover_reg_top/12.xbar_random.639935336
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.3236280796
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.1530263825
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.3797976345
/workspace/coverage/cover_reg_top/12.xbar_same_source.785526408
/workspace/coverage/cover_reg_top/12.xbar_smoke.1788377252
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.854471163
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/workspace/coverage/default/96.chip_sw_all_escalation_resets.254271973
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/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2875197593
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3774935257
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3261889369
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2221629467
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3921074240

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Total test records in report: 2936

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.128726496			Aug 17 07:15:26 PM PDT 24	Aug 17 07:23:12 PM PDT 24	6582872356 ps
T2	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2536795900			Aug 17 07:23:46 PM PDT 24	Aug 17 07:43:57 PM PDT 24	14037729789 ps
T3	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.3619033627			Aug 17 07:05:33 PM PDT 24	Aug 17 08:23:24 PM PDT 24	42756656258 ps
T84	/workspace/coverage/default/2.chip_sw_aes_smoketest.1107957784			Aug 17 07:27:43 PM PDT 24	Aug 17 07:32:05 PM PDT 24	2572409480 ps
T20	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.1785554018			Aug 17 07:11:51 PM PDT 24	Aug 17 08:05:51 PM PDT 24	20209985535 ps
T4	/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1239143318			Aug 17 07:08:37 PM PDT 24	Aug 17 07:16:14 PM PDT 24	7039829576 ps
T85	/workspace/coverage/default/0.chip_sw_rv_timer_irq.1172923867			Aug 17 07:10:24 PM PDT 24	Aug 17 07:14:22 PM PDT 24	2515829902 ps
T5	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1805391497			Aug 17 07:08:25 PM PDT 24	Aug 17 07:23:32 PM PDT 24	7328500792 ps
T86	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2769736527			Aug 17 07:06:38 PM PDT 24	Aug 17 07:16:27 PM PDT 24	4256244278 ps
T43	/workspace/coverage/default/0.rom_e2e_jtag_debug_rma.1979412028			Aug 17 07:13:29 PM PDT 24	Aug 17 07:50:16 PM PDT 24	11357367017 ps
T181	/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3374776843			Aug 17 07:26:11 PM PDT 24	Aug 17 07:34:04 PM PDT 24	4764134040 ps
T48	/workspace/coverage/default/1.chip_tap_straps_prod.739121696			Aug 17 07:19:41 PM PDT 24	Aug 17 07:22:25 PM PDT 24	2934409098 ps
T46	/workspace/coverage/default/2.chip_tap_straps_rma.3358582567			Aug 17 07:25:26 PM PDT 24	Aug 17 07:40:23 PM PDT 24	9092355642 ps
T256	/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1261998297			Aug 17 07:12:09 PM PDT 24	Aug 17 07:18:15 PM PDT 24	3188664894 ps
T61	/workspace/coverage/default/61.chip_sw_all_escalation_resets.771084135			Aug 17 07:37:38 PM PDT 24	Aug 17 07:47:47 PM PDT 24	5646919684 ps
T257	/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3828971789			Aug 17 07:24:29 PM PDT 24	Aug 17 07:36:55 PM PDT 24	4563985750 ps
T222	/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3333714150			Aug 17 07:34:29 PM PDT 24	Aug 17 07:41:01 PM PDT 24	4095987968 ps
T13	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1248332898			Aug 17 07:20:33 PM PDT 24	Aug 17 07:29:24 PM PDT 24	3772745779 ps
T651	/workspace/coverage/default/1.chip_sw_aes_masking_off.892529345			Aug 17 07:15:34 PM PDT 24	Aug 17 07:21:12 PM PDT 24	2734506078 ps
T62	/workspace/coverage/default/35.chip_sw_all_escalation_resets.247131785			Aug 17 07:33:11 PM PDT 24	Aug 17 07:43:26 PM PDT 24	5457217752 ps
T44	/workspace/coverage/default/0.rom_e2e_self_hash.631317007			Aug 17 07:13:32 PM PDT 24	Aug 17 08:46:02 PM PDT 24	25501601928 ps
T118	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.449882420			Aug 17 07:09:01 PM PDT 24	Aug 17 07:18:55 PM PDT 24	5609222503 ps
T10	/workspace/coverage/default/2.chip_sw_power_virus.2301790302			Aug 17 07:31:46 PM PDT 24	Aug 17 07:54:24 PM PDT 24	5830033200 ps
T6	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.1673521649			Aug 17 07:15:01 PM PDT 24	Aug 17 07:21:27 PM PDT 24	4899770252 ps
T359	/workspace/coverage/default/68.chip_sw_all_escalation_resets.1862804518			Aug 17 07:35:46 PM PDT 24	Aug 17 07:44:16 PM PDT 24	4288525100 ps
T119	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.259912819			Aug 17 07:12:05 PM PDT 24	Aug 17 07:23:18 PM PDT 24	4081760950 ps
T16	/workspace/coverage/default/0.chip_sw_usbdev_dpi.4037418851			Aug 17 07:05:36 PM PDT 24	Aug 17 07:50:39 PM PDT 24	11570196360 ps
T333	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.956343384			Aug 17 07:31:57 PM PDT 24	Aug 17 07:37:46 PM PDT 24	4128671668 ps
T375	/workspace/coverage/default/87.chip_sw_all_escalation_resets.3995112562			Aug 17 07:38:22 PM PDT 24	Aug 17 07:47:49 PM PDT 24	5443817284 ps
T379	/workspace/coverage/default/2.chip_sw_aes_entropy.3829748641			Aug 17 07:23:43 PM PDT 24	Aug 17 07:27:37 PM PDT 24	3024290760 ps
T357	/workspace/coverage/default/88.chip_sw_all_escalation_resets.2686852898			Aug 17 07:37:10 PM PDT 24	Aug 17 07:49:42 PM PDT 24	5718827132 ps
T45	/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.334176630			Aug 17 07:11:51 PM PDT 24	Aug 17 07:59:47 PM PDT 24	11136582872 ps
T209	/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.1230752081			Aug 17 07:08:48 PM PDT 24	Aug 17 07:13:22 PM PDT 24	2483311478 ps
T246	/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.4156546607			Aug 17 07:14:25 PM PDT 24	Aug 17 07:20:24 PM PDT 24	3746320666 ps
T369	/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1327888268			Aug 17 07:36:37 PM PDT 24	Aug 17 07:42:45 PM PDT 24	3156608328 ps
T151	/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3139942524			Aug 17 07:29:07 PM PDT 24	Aug 17 07:39:54 PM PDT 24	3568000500 ps
T452	/workspace/coverage/default/76.chip_sw_all_escalation_resets.3225424667			Aug 17 07:37:13 PM PDT 24	Aug 17 07:46:30 PM PDT 24	5146150840 ps
T878	/workspace/coverage/default/1.chip_sw_example_flash.3129322333			Aug 17 07:09:44 PM PDT 24	Aug 17 07:12:13 PM PDT 24	2352248360 ps
T120	/workspace/coverage/default/1.chip_sw_clkmgr_jitter.2073092498			Aug 17 07:16:35 PM PDT 24	Aug 17 07:20:49 PM PDT 24	3279825286 ps
T14	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.2777643513			Aug 17 07:19:00 PM PDT 24	Aug 17 07:24:29 PM PDT 24	3656267672 ps
T99	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.686174538			Aug 17 07:31:40 PM PDT 24	Aug 17 07:51:19 PM PDT 24	6902206220 ps
T100	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2604219748			Aug 17 07:06:10 PM PDT 24	Aug 17 08:01:34 PM PDT 24	35697921370 ps
T40	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1810688948			Aug 17 07:13:21 PM PDT 24	Aug 17 08:18:24 PM PDT 24	14503843420 ps
T101	/workspace/coverage/default/1.chip_sw_aon_timer_irq.2260710157			Aug 17 07:11:21 PM PDT 24	Aug 17 07:18:12 PM PDT 24	4498136872 ps
T102	/workspace/coverage/default/34.chip_sw_all_escalation_resets.421417772			Aug 17 07:33:57 PM PDT 24	Aug 17 07:45:55 PM PDT 24	4879913832 ps
T15	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.1209596828			Aug 17 07:19:15 PM PDT 24	Aug 17 07:28:00 PM PDT 24	3820442080 ps
T103	/workspace/coverage/default/2.chip_sw_edn_boot_mode.793466174			Aug 17 07:24:03 PM PDT 24	Aug 17 07:34:32 PM PDT 24	3406242296 ps
T104	/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.955393980			Aug 17 07:31:01 PM PDT 24	Aug 17 08:17:10 PM PDT 24	11573064857 ps
T105	/workspace/coverage/default/2.chip_plic_all_irqs_0.1052881397			Aug 17 07:23:49 PM PDT 24	Aug 17 07:40:10 PM PDT 24	6692500360 ps
T213	/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3743576987			Aug 17 07:29:51 PM PDT 24	Aug 17 07:41:30 PM PDT 24	4283268376 ps
T696	/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3834163065			Aug 17 07:37:45 PM PDT 24	Aug 17 07:43:19 PM PDT 24	3587316088 ps
T879	/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1748215617			Aug 17 07:09:47 PM PDT 24	Aug 17 07:13:24 PM PDT 24	2706721868 ps
T697	/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.772003730			Aug 17 07:30:37 PM PDT 24	Aug 17 07:38:05 PM PDT 24	4171995096 ps
T376	/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.3967649034			Aug 17 07:35:45 PM PDT 24	Aug 17 07:41:11 PM PDT 24	3550484908 ps
T384	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.2034913160			Aug 17 07:32:12 PM PDT 24	Aug 17 07:37:34 PM PDT 24	3494296110 ps
T247	/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1268009038			Aug 17 07:22:57 PM PDT 24	Aug 17 07:34:42 PM PDT 24	5462078100 ps
T312	/workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.1308030274			Aug 17 07:12:52 PM PDT 24	Aug 17 07:36:20 PM PDT 24	7962110712 ps
T67	/workspace/coverage/default/4.chip_tap_straps_dev.3582865545			Aug 17 07:28:22 PM PDT 24	Aug 17 07:52:12 PM PDT 24	11764629320 ps
T385	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.3599563810			Aug 17 07:32:21 PM PDT 24	Aug 17 07:38:16 PM PDT 24	3740926470 ps
T78	/workspace/coverage/default/46.chip_sw_all_escalation_resets.1005373677			Aug 17 07:34:14 PM PDT 24	Aug 17 07:45:56 PM PDT 24	5871547976 ps
T91	/workspace/coverage/default/2.chip_sival_flash_info_access.550963171			Aug 17 07:18:24 PM PDT 24	Aug 17 07:22:58 PM PDT 24	3298113190 ps
T92	/workspace/coverage/default/1.chip_sw_aes_smoketest.1050697813			Aug 17 07:18:37 PM PDT 24	Aug 17 07:24:36 PM PDT 24	2916339760 ps
T68	/workspace/coverage/default/3.chip_tap_straps_prod.1018854807			Aug 17 07:28:22 PM PDT 24	Aug 17 07:50:32 PM PDT 24	13674542640 ps
T34	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4100016698			Aug 17 07:12:23 PM PDT 24	Aug 17 07:21:43 PM PDT 24	5569499532 ps
T93	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.4116158907			Aug 17 07:24:43 PM PDT 24	Aug 17 08:18:54 PM PDT 24	14469590800 ps
T94	/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.4069676977			Aug 17 07:34:07 PM PDT 24	Aug 17 08:26:01 PM PDT 24	15596735086 ps
T95	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.35417885			Aug 17 07:30:11 PM PDT 24	Aug 17 07:55:57 PM PDT 24	9519123024 ps
T47	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.1268459266			Aug 17 07:20:16 PM PDT 24	Aug 17 08:41:41 PM PDT 24	49525343154 ps
T96	/workspace/coverage/default/1.chip_sw_kmac_entropy.2256662950			Aug 17 07:12:05 PM PDT 24	Aug 17 07:16:53 PM PDT 24	2886017544 ps
T652	/workspace/coverage/default/0.chip_sw_aes_masking_off.2464500268			Aug 17 07:14:19 PM PDT 24	Aug 17 07:19:31 PM PDT 24	2525817458 ps
T60	/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.3130807236			Aug 17 07:08:08 PM PDT 24	Aug 17 07:10:29 PM PDT 24	2987162584 ps
T236	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3947242485			Aug 17 07:28:05 PM PDT 24	Aug 17 07:57:34 PM PDT 24	20541833817 ps
T162	/workspace/coverage/default/67.chip_sw_all_escalation_resets.937966356			Aug 17 07:35:25 PM PDT 24	Aug 17 07:46:07 PM PDT 24	6240574620 ps
T391	/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3094922836			Aug 17 07:36:35 PM PDT 24	Aug 17 07:43:02 PM PDT 24	3925688836 ps
T121	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1701871836			Aug 17 07:15:14 PM PDT 24	Aug 17 07:27:35 PM PDT 24	4678584594 ps
T288	/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3581051815			Aug 17 07:11:35 PM PDT 24	Aug 17 07:20:03 PM PDT 24	3673653560 ps
T248	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1565244425			Aug 17 07:32:35 PM PDT 24	Aug 17 07:40:11 PM PDT 24	3561829528 ps
T214	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.1115361399			Aug 17 07:07:14 PM PDT 24	Aug 17 07:17:09 PM PDT 24	3963861576 ps
T289	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.2063843866			Aug 17 07:19:31 PM PDT 24	Aug 17 07:33:12 PM PDT 24	4881177448 ps
T210	/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1529387386			Aug 17 07:36:12 PM PDT 24	Aug 17 07:42:15 PM PDT 24	3752230464 ps
T295	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.2749914003			Aug 17 07:24:43 PM PDT 24	Aug 17 07:34:16 PM PDT 24	5805242820 ps
T124	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2528156664			Aug 17 07:09:25 PM PDT 24	Aug 17 07:19:03 PM PDT 24	4044188160 ps
T296	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.2154608060			Aug 17 07:05:47 PM PDT 24	Aug 17 07:18:43 PM PDT 24	5042091832 ps
T65	/workspace/coverage/default/0.chip_jtag_csr_rw.2677200915			Aug 17 06:59:19 PM PDT 24	Aug 17 07:24:29 PM PDT 24	10277147276 ps
T216	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1258489232			Aug 17 07:07:24 PM PDT 24	Aug 17 07:16:06 PM PDT 24	4820120966 ps
T297	/workspace/coverage/default/33.chip_sw_all_escalation_resets.3081493981			Aug 17 07:33:51 PM PDT 24	Aug 17 07:42:50 PM PDT 24	4466325000 ps
T451	/workspace/coverage/default/0.chip_sw_kmac_entropy.176026935			Aug 17 07:08:20 PM PDT 24	Aug 17 07:12:07 PM PDT 24	2392226266 ps
T79	/workspace/coverage/default/1.chip_sw_alert_handler_entropy.1755515773			Aug 17 07:14:31 PM PDT 24	Aug 17 07:21:10 PM PDT 24	3909339716 ps
T122	/workspace/coverage/default/0.rom_volatile_raw_unlock.1342949938			Aug 17 07:14:00 PM PDT 24	Aug 17 07:15:55 PM PDT 24	2444209094 ps
T219	/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.11608661			Aug 17 07:14:30 PM PDT 24	Aug 17 07:53:17 PM PDT 24	31504332944 ps
T326	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.3982754438			Aug 17 07:09:04 PM PDT 24	Aug 17 07:20:34 PM PDT 24	3390424622 ps
T342	/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.861097599			Aug 17 07:32:08 PM PDT 24	Aug 17 07:43:04 PM PDT 24	4508505224 ps
T713	/workspace/coverage/default/83.chip_sw_all_escalation_resets.2399968305			Aug 17 07:39:40 PM PDT 24	Aug 17 07:48:42 PM PDT 24	6256197192 ps
T153	/workspace/coverage/default/2.chip_sw_power_idle_load.1073658368			Aug 17 07:28:49 PM PDT 24	Aug 17 07:39:24 PM PDT 24	5033697104 ps
T450	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3958393199			Aug 17 07:31:43 PM PDT 24	Aug 17 07:37:11 PM PDT 24	4159174318 ps
T41	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.1486574705			Aug 17 07:15:41 PM PDT 24	Aug 17 08:10:27 PM PDT 24	10998180482 ps
T261	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.3351795022			Aug 17 07:14:20 PM PDT 24	Aug 17 07:57:09 PM PDT 24	11777202064 ps
T127	/workspace/coverage/default/1.chip_sw_edn_kat.4103952017			Aug 17 07:14:54 PM PDT 24	Aug 17 07:25:28 PM PDT 24	3784609364 ps
T311	/workspace/coverage/default/45.chip_sw_all_escalation_resets.1689139460			Aug 17 07:33:59 PM PDT 24	Aug 17 07:41:50 PM PDT 24	4397703688 ps
T461	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3238676095			Aug 17 07:20:40 PM PDT 24	Aug 17 07:44:41 PM PDT 24	10920019122 ps
T782	/workspace/coverage/default/55.chip_sw_all_escalation_resets.2046463891			Aug 17 07:36:33 PM PDT 24	Aug 17 07:50:12 PM PDT 24	5107238320 ps
T880	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.4204363716			Aug 17 07:23:08 PM PDT 24	Aug 17 08:18:16 PM PDT 24	14639832476 ps
T42	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.2935335542			Aug 17 07:18:14 PM PDT 24	Aug 17 08:13:21 PM PDT 24	14331759891 ps
T881	/workspace/coverage/default/2.chip_sw_kmac_smoketest.2698789034			Aug 17 07:30:29 PM PDT 24	Aug 17 07:35:36 PM PDT 24	2845055758 ps
T177	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.2377337521			Aug 17 07:20:57 PM PDT 24	Aug 17 08:32:59 PM PDT 24	44574217500 ps
T313	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.3121176905			Aug 17 07:08:35 PM PDT 24	Aug 17 07:24:19 PM PDT 24	4933874452 ps
T167	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1147042079			Aug 17 07:12:08 PM PDT 24	Aug 17 07:14:00 PM PDT 24	2694087289 ps
T715	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.1077145003			Aug 17 07:07:12 PM PDT 24	Aug 17 07:19:44 PM PDT 24	6650309748 ps
T123	/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.1626192496			Aug 17 07:17:54 PM PDT 24	Aug 17 07:31:37 PM PDT 24	12696648682 ps
T882	/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.3624442106			Aug 17 07:14:40 PM PDT 24	Aug 17 07:18:04 PM PDT 24	3299826100 ps
T358	/workspace/coverage/default/16.chip_sw_all_escalation_resets.454834746			Aug 17 07:33:57 PM PDT 24	Aug 17 07:44:01 PM PDT 24	4978691248 ps
T378	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3478420781			Aug 17 07:22:46 PM PDT 24	Aug 17 08:30:54 PM PDT 24	15241500760 ps
T883	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1367228337			Aug 17 07:12:22 PM PDT 24	Aug 17 08:10:59 PM PDT 24	15059626492 ps
T884	/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.1938094409			Aug 17 07:27:48 PM PDT 24	Aug 17 07:31:11 PM PDT 24	2636700000 ps
T152	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.2373924540			Aug 17 07:10:35 PM PDT 24	Aug 17 07:22:03 PM PDT 24	4395649810 ps
T747	/workspace/coverage/default/47.chip_sw_all_escalation_resets.2627059667			Aug 17 07:34:03 PM PDT 24	Aug 17 07:45:30 PM PDT 24	5058155012 ps
T220	/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.2846122175			Aug 17 07:25:38 PM PDT 24	Aug 17 08:11:25 PM PDT 24	32443434701 ps
T316	/workspace/coverage/default/3.chip_sw_all_escalation_resets.961375599			Aug 17 07:28:01 PM PDT 24	Aug 17 07:38:22 PM PDT 24	4321494632 ps
T224	/workspace/coverage/default/2.chip_sw_alert_handler_escalation.1526680427			Aug 17 07:22:34 PM PDT 24	Aug 17 07:31:00 PM PDT 24	5136125232 ps
T319	/workspace/coverage/default/0.chip_sw_aon_timer_irq.2652663820			Aug 17 07:08:34 PM PDT 24	Aug 17 07:15:19 PM PDT 24	4103756544 ps
T223	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.1103132384			Aug 17 07:13:58 PM PDT 24	Aug 17 07:48:47 PM PDT 24	8987314916 ps
T320	/workspace/coverage/default/0.chip_sw_hmac_smoketest.3074150203			Aug 17 07:09:31 PM PDT 24	Aug 17 07:14:07 PM PDT 24	3358467960 ps
T321	/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.3674518228			Aug 17 07:23:29 PM PDT 24	Aug 17 07:27:19 PM PDT 24	2904102380 ps
T7	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3352331357			Aug 17 07:15:24 PM PDT 24	Aug 17 07:21:07 PM PDT 24	2907390288 ps
T322	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2196779329			Aug 17 07:12:48 PM PDT 24	Aug 17 07:34:17 PM PDT 24	13902634085 ps
T323	/workspace/coverage/default/63.chip_sw_all_escalation_resets.1135087748			Aug 17 07:37:15 PM PDT 24	Aug 17 07:47:19 PM PDT 24	6201256168 ps
T106	/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.2124401836			Aug 17 07:25:54 PM PDT 24	Aug 17 07:34:52 PM PDT 24	4492431976 ps
T392	/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.403610505			Aug 17 07:35:22 PM PDT 24	Aug 17 07:40:41 PM PDT 24	3368242538 ps
T439	/workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.354198765			Aug 17 07:26:50 PM PDT 24	Aug 17 07:32:57 PM PDT 24	3818541662 ps
T225	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.2854087888			Aug 17 07:06:26 PM PDT 24	Aug 17 07:28:10 PM PDT 24	8176785344 ps
T37	/workspace/coverage/default/2.chip_sw_spi_device_tpm.364852337			Aug 17 07:20:12 PM PDT 24	Aug 17 07:25:41 PM PDT 24	3426929121 ps
T176	/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.2584558038			Aug 17 07:28:36 PM PDT 24	Aug 17 07:43:25 PM PDT 24	12205950517 ps
T290	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3070637933			Aug 17 07:14:10 PM PDT 24	Aug 17 07:24:00 PM PDT 24	4869278712 ps
T440	/workspace/coverage/default/2.chip_sw_example_rom.2056315843			Aug 17 07:18:02 PM PDT 24	Aug 17 07:19:48 PM PDT 24	2326951016 ps
T128	/workspace/coverage/default/1.chip_sw_edn_boot_mode.3940456213			Aug 17 07:12:48 PM PDT 24	Aug 17 07:22:54 PM PDT 24	3118898256 ps
T441	/workspace/coverage/default/2.chip_sw_example_concurrency.1142746577			Aug 17 07:19:58 PM PDT 24	Aug 17 07:24:08 PM PDT 24	2704736824 ps
T885	/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1519570726			Aug 17 07:09:10 PM PDT 24	Aug 17 07:19:44 PM PDT 24	4580019440 ps
T886	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.4268042514			Aug 17 07:16:50 PM PDT 24	Aug 17 08:19:56 PM PDT 24	14306229444 ps
T215	/workspace/coverage/default/0.chip_sw_pattgen_ios.2505344539			Aug 17 07:06:29 PM PDT 24	Aug 17 07:10:15 PM PDT 24	2657889208 ps
T887	/workspace/coverage/default/1.chip_sw_aes_idle.1163886018			Aug 17 07:13:42 PM PDT 24	Aug 17 07:18:01 PM PDT 24	3073592840 ps
T888	/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2095405304			Aug 17 07:08:02 PM PDT 24	Aug 17 07:17:29 PM PDT 24	4374544080 ps
T314	/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.1651161359			Aug 17 07:25:01 PM PDT 24	Aug 17 07:45:22 PM PDT 24	9568535810 ps
T367	/workspace/coverage/default/17.chip_sw_all_escalation_resets.336730745			Aug 17 07:32:23 PM PDT 24	Aug 17 07:44:02 PM PDT 24	5717974904 ps
T889	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.1719476203			Aug 17 07:14:23 PM PDT 24	Aug 17 07:21:27 PM PDT 24	3817741872 ps
T658	/workspace/coverage/default/95.chip_sw_all_escalation_resets.1036328324			Aug 17 07:39:00 PM PDT 24	Aug 17 07:46:26 PM PDT 24	5932732192 ps
T180	/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.1523960510			Aug 17 07:21:20 PM PDT 24	Aug 17 08:28:11 PM PDT 24	15559947282 ps
T211	/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2109142188			Aug 17 07:36:46 PM PDT 24	Aug 17 07:42:29 PM PDT 24	3916535464 ps
T315	/workspace/coverage/default/3.chip_sw_uart_tx_rx.2246506178			Aug 17 07:31:41 PM PDT 24	Aug 17 07:40:57 PM PDT 24	4199005210 ps
T890	/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.1807112293			Aug 17 07:33:24 PM PDT 24	Aug 17 07:37:09 PM PDT 24	2674072056 ps
T338	/workspace/coverage/default/0.chip_sw_uart_tx_rx.2624168317			Aug 17 07:04:54 PM PDT 24	Aug 17 07:15:47 PM PDT 24	3921226232 ps
T891	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.796466340			Aug 17 07:25:05 PM PDT 24	Aug 17 07:29:48 PM PDT 24	2397650807 ps
T31	/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.885348975			Aug 17 07:11:01 PM PDT 24	Aug 17 07:15:20 PM PDT 24	3218367080 ps
T186	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1648213818			Aug 17 07:06:52 PM PDT 24	Aug 17 07:12:42 PM PDT 24	4537244084 ps
T187	/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.1470582044			Aug 17 07:12:40 PM PDT 24	Aug 17 07:21:10 PM PDT 24	3813470416 ps
T892	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.1216011329			Aug 17 07:20:31 PM PDT 24	Aug 17 07:37:58 PM PDT 24	6555262959 ps
T893	/workspace/coverage/default/1.chip_sw_csrng_smoketest.2605205794			Aug 17 07:18:09 PM PDT 24	Aug 17 07:21:47 PM PDT 24	2196429024 ps
T147	/workspace/coverage/default/1.chip_sw_inject_scramble_seed.3612869683			Aug 17 07:10:37 PM PDT 24	Aug 17 10:11:20 PM PDT 24	65632333816 ps
T894	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.2185630698			Aug 17 07:12:38 PM PDT 24	Aug 17 07:22:39 PM PDT 24	8018746583 ps
T895	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.743692634			Aug 17 07:14:42 PM PDT 24	Aug 17 07:23:29 PM PDT 24	3749102156 ps
T17	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3233584783			Aug 17 07:26:00 PM PDT 24	Aug 17 07:33:27 PM PDT 24	7416975288 ps
T433	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1423437635			Aug 17 07:13:57 PM PDT 24	Aug 17 07:19:53 PM PDT 24	3369928886 ps
T243	/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.2775500023			Aug 17 07:22:39 PM PDT 24	Aug 17 07:30:04 PM PDT 24	5358768524 ps
T185	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.428692315			Aug 17 07:10:09 PM PDT 24	Aug 17 08:32:32 PM PDT 24	43419829010 ps
T115	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3753536472			Aug 17 07:10:27 PM PDT 24	Aug 17 08:12:05 PM PDT 24	24732751127 ps
T269	/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.3842416822			Aug 17 07:31:11 PM PDT 24	Aug 17 07:55:13 PM PDT 24	7787297640 ps
T270	/workspace/coverage/default/5.chip_sw_all_escalation_resets.2508484135			Aug 17 07:34:53 PM PDT 24	Aug 17 07:42:10 PM PDT 24	5187411168 ps
T271	/workspace/coverage/default/58.chip_sw_all_escalation_resets.2882771223			Aug 17 07:34:11 PM PDT 24	Aug 17 07:41:42 PM PDT 24	5487581924 ps
T272	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.399419323			Aug 17 07:33:32 PM PDT 24	Aug 17 07:40:31 PM PDT 24	3697037850 ps
T273	/workspace/coverage/default/0.rom_e2e_asm_init_prod.4104576852			Aug 17 07:16:32 PM PDT 24	Aug 17 08:18:19 PM PDT 24	16171312880 ps
T274	/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.739379504			Aug 17 07:35:31 PM PDT 24	Aug 17 07:44:34 PM PDT 24	4000072332 ps
T154	/workspace/coverage/default/1.chip_sw_power_idle_load.2786402205			Aug 17 07:20:50 PM PDT 24	Aug 17 07:30:57 PM PDT 24	3818603500 ps
T21	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.3580334417			Aug 17 07:10:17 PM PDT 24	Aug 17 07:16:59 PM PDT 24	4003036808 ps
T22	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.2873501006			Aug 17 07:22:31 PM PDT 24	Aug 17 07:52:07 PM PDT 24	23661001720 ps
T129	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2004011308			Aug 17 07:17:46 PM PDT 24	Aug 17 07:28:45 PM PDT 24	6319597300 ps
T896	/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.3129530865			Aug 17 07:33:43 PM PDT 24	Aug 17 07:40:22 PM PDT 24	6022528273 ps
T897	/workspace/coverage/default/2.chip_sw_example_flash.1796814898			Aug 17 07:22:37 PM PDT 24	Aug 17 07:27:19 PM PDT 24	2992097648 ps
T898	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.2696483470			Aug 17 07:10:22 PM PDT 24	Aug 17 07:21:56 PM PDT 24	9153213180 ps
T711	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1452540148			Aug 17 07:33:27 PM PDT 24	Aug 17 07:38:34 PM PDT 24	3705694570 ps
T366	/workspace/coverage/default/79.chip_sw_all_escalation_resets.3460994373			Aug 17 07:37:28 PM PDT 24	Aug 17 07:48:59 PM PDT 24	4790692304 ps
T8	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.573093126			Aug 17 07:18:42 PM PDT 24	Aug 17 07:23:36 PM PDT 24	3019255621 ps
T339	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.3290495346			Aug 17 07:06:31 PM PDT 24	Aug 17 07:17:56 PM PDT 24	4564352070 ps
T899	/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.2328362324			Aug 17 07:29:00 PM PDT 24	Aug 17 07:38:03 PM PDT 24	6295735198 ps
T252	/workspace/coverage/default/1.chip_sw_plic_sw_irq.872022073			Aug 17 07:14:40 PM PDT 24	Aug 17 07:17:49 PM PDT 24	2765043140 ps
T695	/workspace/coverage/default/0.chip_tap_straps_dev.3843982332			Aug 17 07:06:18 PM PDT 24	Aug 17 07:09:39 PM PDT 24	2908159752 ps
T900	/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.878841829			Aug 17 07:21:43 PM PDT 24	Aug 17 07:26:29 PM PDT 24	3299591360 ps
T901	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.3018772025			Aug 17 07:18:52 PM PDT 24	Aug 17 08:12:56 PM PDT 24	15136321128 ps
T902	/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.2818123442			Aug 17 07:25:00 PM PDT 24	Aug 17 07:33:54 PM PDT 24	5251862984 ps
T116	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.1483284660			Aug 17 07:15:30 PM PDT 24	Aug 17 07:44:21 PM PDT 24	7916436975 ps
T903	/workspace/coverage/default/2.chip_sw_csrng_kat_test.1835826415			Aug 17 07:28:14 PM PDT 24	Aug 17 07:32:35 PM PDT 24	2517980288 ps
T716	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2600030989			Aug 17 07:31:28 PM PDT 24	Aug 17 07:38:49 PM PDT 24	4300184608 ps
T275	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.2864683048			Aug 17 07:13:36 PM PDT 24	Aug 17 08:49:25 PM PDT 24	23198637100 ps
T904	/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.295111453			Aug 17 07:33:55 PM PDT 24	Aug 17 07:43:16 PM PDT 24	4524294886 ps
T905	/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.341189522			Aug 17 07:06:21 PM PDT 24	Aug 17 07:23:52 PM PDT 24	5565399610 ps
T204	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.1359244189			Aug 17 07:09:46 PM PDT 24	Aug 17 07:14:25 PM PDT 24	2730605648 ps
T217	/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.2852045665			Aug 17 07:05:53 PM PDT 24	Aug 17 07:31:57 PM PDT 24	8675876220 ps
T49	/workspace/coverage/default/1.chip_sw_alert_test.309146927			Aug 17 07:12:07 PM PDT 24	Aug 17 07:16:54 PM PDT 24	2615064888 ps
T291	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.2598554545			Aug 17 07:24:53 PM PDT 24	Aug 17 07:33:05 PM PDT 24	4397351506 ps
T906	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2493552686			Aug 17 07:16:55 PM PDT 24	Aug 17 08:24:49 PM PDT 24	14193774276 ps
T752	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2111492638			Aug 17 07:29:12 PM PDT 24	Aug 17 07:35:01 PM PDT 24	4417312256 ps
T11	/workspace/coverage/default/0.chip_sw_spi_device_pass_through.3158919310			Aug 17 07:07:36 PM PDT 24	Aug 17 07:21:43 PM PDT 24	6750238535 ps
T59	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.2891175305			Aug 17 07:05:06 PM PDT 24	Aug 17 07:13:45 PM PDT 24	3518032478 ps
T155	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.2153120724			Aug 17 07:23:01 PM PDT 24	Aug 17 08:24:45 PM PDT 24	16590123668 ps
T9	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.744288096			Aug 17 07:05:08 PM PDT 24	Aug 17 07:10:17 PM PDT 24	3054490267 ps
T393	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1104792294			Aug 17 07:14:50 PM PDT 24	Aug 17 09:09:50 PM PDT 24	24743114408 ps
T125	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2551318626			Aug 17 07:14:39 PM PDT 24	Aug 17 07:25:12 PM PDT 24	3990095560 ps
T171	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.2578577784			Aug 17 07:11:12 PM PDT 24	Aug 17 07:31:06 PM PDT 24	11199767416 ps
T117	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.89858473			Aug 17 07:05:37 PM PDT 24	Aug 17 07:21:59 PM PDT 24	6843521672 ps
T907	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.3808245378			Aug 17 07:25:29 PM PDT 24	Aug 17 07:31:53 PM PDT 24	6109833870 ps
T908	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.2186787038			Aug 17 07:17:12 PM PDT 24	Aug 17 08:29:58 PM PDT 24	15561825240 ps
T368	/workspace/coverage/default/93.chip_sw_all_escalation_resets.4177898401			Aug 17 07:36:58 PM PDT 24	Aug 17 07:47:46 PM PDT 24	6057819050 ps
T909	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.2737953947			Aug 17 07:05:37 PM PDT 24	Aug 17 07:14:30 PM PDT 24	4810802000 ps
T910	/workspace/coverage/default/1.chip_sw_hmac_oneshot.1328446858			Aug 17 07:13:43 PM PDT 24	Aug 17 07:18:30 PM PDT 24	2758654560 ps
T911	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.382611205			Aug 17 07:14:57 PM PDT 24	Aug 17 07:23:19 PM PDT 24	6640789318 ps
T276	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.2684823508			Aug 17 07:07:06 PM PDT 24	Aug 17 07:08:57 PM PDT 24	2019698932 ps
T912	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.1508665210			Aug 17 07:29:40 PM PDT 24	Aug 17 07:40:45 PM PDT 24	4792049648 ps
T710	/workspace/coverage/default/0.chip_sw_ast_clk_outputs.2014857627			Aug 17 07:07:02 PM PDT 24	Aug 17 07:22:10 PM PDT 24	8433724880 ps
T913	/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.2584495407			Aug 17 07:16:08 PM PDT 24	Aug 17 07:21:11 PM PDT 24	3603708444 ps
T453	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1826366068			Aug 17 07:26:33 PM PDT 24	Aug 17 08:19:51 PM PDT 24	25019017546 ps
T737	/workspace/coverage/default/38.chip_sw_all_escalation_resets.1740840128			Aug 17 07:34:56 PM PDT 24	Aug 17 07:44:39 PM PDT 24	4496804238 ps
T657	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2083733125			Aug 17 07:20:22 PM PDT 24	Aug 17 08:35:55 PM PDT 24	24423841995 ps
T914	/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.4290863130			Aug 17 07:14:16 PM PDT 24	Aug 17 07:21:09 PM PDT 24	4136316150 ps
T165	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1611787943			Aug 17 07:22:57 PM PDT 24	Aug 17 07:27:57 PM PDT 24	2457101165 ps
T915	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.2284525572			Aug 17 07:07:07 PM PDT 24	Aug 17 07:11:57 PM PDT 24	3385721866 ps
T126	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.4012057819			Aug 17 07:10:20 PM PDT 24	Aug 17 07:22:10 PM PDT 24	4813081512 ps
T654	/workspace/coverage/default/1.chip_sw_edn_auto_mode.4117242806			Aug 17 07:18:03 PM PDT 24	Aug 17 07:36:18 PM PDT 24	4774955864 ps
T343	/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.3453677405			Aug 17 07:20:21 PM PDT 24	Aug 17 08:01:28 PM PDT 24	12840972712 ps
T175	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.2134352695			Aug 17 07:23:15 PM PDT 24	Aug 17 08:41:08 PM PDT 24	48987926114 ps
T205	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.1509210083			Aug 17 07:22:23 PM PDT 24	Aug 17 07:27:21 PM PDT 24	2913923856 ps
T263	/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2184645461			Aug 17 07:33:52 PM PDT 24	Aug 17 07:40:16 PM PDT 24	3230581152 ps
T757	/workspace/coverage/default/85.chip_sw_all_escalation_resets.1941458526			Aug 17 07:37:31 PM PDT 24	Aug 17 07:45:48 PM PDT 24	4790874500 ps
T87	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3772403760			Aug 17 07:31:29 PM PDT 24	Aug 17 07:38:08 PM PDT 24	3635939000 ps
T168	/workspace/coverage/default/40.chip_sw_all_escalation_resets.3648886651			Aug 17 07:32:36 PM PDT 24	Aug 17 07:41:26 PM PDT 24	4547290104 ps
T735	/workspace/coverage/default/2.chip_sw_ast_clk_outputs.390202423			Aug 17 07:24:37 PM PDT 24	Aug 17 07:46:47 PM PDT 24	8075524520 ps
T12	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3896782295			Aug 17 07:21:00 PM PDT 24	Aug 17 07:25:45 PM PDT 24	3287757940 ps
T792	/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1885118606			Aug 17 07:37:23 PM PDT 24	Aug 17 07:44:17 PM PDT 24	4166437240 ps
T206	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.391214298			Aug 17 07:10:23 PM PDT 24	Aug 17 07:15:32 PM PDT 24	3385003185 ps
T916	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.86004408			Aug 17 07:25:58 PM PDT 24	Aug 17 07:37:19 PM PDT 24	4598975752 ps
T917	/workspace/coverage/default/2.chip_tap_straps_prod.1662026997			Aug 17 07:26:12 PM PDT 24	Aug 17 07:28:28 PM PDT 24	2904969709 ps
T111	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2447803298			Aug 17 07:08:54 PM PDT 24	Aug 17 07:17:31 PM PDT 24	19945545508 ps
T277	/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1016584221			Aug 17 07:25:18 PM PDT 24	Aug 17 07:33:02 PM PDT 24	8868208045 ps
T112	/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.1990980194			Aug 17 07:07:19 PM PDT 24	Aug 17 07:51:17 PM PDT 24	19423376190 ps
T249	/workspace/coverage/default/43.chip_sw_all_escalation_resets.2066010830			Aug 17 07:33:41 PM PDT 24	Aug 17 07:46:45 PM PDT 24	6017141466 ps
T178	/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.312111810			Aug 17 07:09:28 PM PDT 24	Aug 17 07:11:54 PM PDT 24	3949633842 ps
T329	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3143019809			Aug 17 07:15:33 PM PDT 24	Aug 17 07:31:24 PM PDT 24	5211010404 ps
T918	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.874787784			Aug 17 07:08:21 PM PDT 24	Aug 17 07:23:53 PM PDT 24	8435812580 ps
T919	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.2898021091			Aug 17 07:16:46 PM PDT 24	Aug 17 08:10:12 PM PDT 24	11896083752 ps
T920	/workspace/coverage/default/2.chip_sw_example_manufacturer.2217317044			Aug 17 07:18:42 PM PDT 24	Aug 17 07:22:23 PM PDT 24	2679455224 ps
T921	/workspace/coverage/default/0.rom_e2e_asm_init_rma.4041037215			Aug 17 07:14:09 PM PDT 24	Aug 17 08:09:54 PM PDT 24	14992021864 ps
T922	/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.4022819676			Aug 17 07:09:02 PM PDT 24	Aug 17 07:14:31 PM PDT 24	3504836600 ps
T923	/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.1560533661			Aug 17 07:25:51 PM PDT 24	Aug 17 07:30:14 PM PDT 24	3002451580 ps