Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	482	1			T74	5		T455	1		T525	1
all_values[1]	490	1			T74	2		T455	1		T521	2
all_values[2]	477	1			T74	3		T455	3		T525	1
all_values[3]	492	1			T74	5		T455	2		T456	1
all_values[4]	476	1			T74	4		T456	1		T520	1
all_values[5]	479	1			T74	1		T455	3		T521	1
all_values[6]	473	1			T74	3		T521	3		T532	6
all_values[7]	488	1			T74	2		T455	5		T529	1
all_values[8]	473	1			T74	4		T455	2		T520	1
all_values[9]	466	1			T74	2		T455	4		T420	1
all_values[10]	489	1			T74	2		T455	1		T521	1
all_values[11]	475	1			T74	3		T455	5		T456	1
all_values[12]	492	1			T74	5		T455	3		T456	1
all_values[13]	502	1			T455	2		T456	1		T521	2
all_values[14]	511	1			T74	3		T455	3		T521	2
all_values[15]	503	1			T74	2		T521	9		T809	1
all_values[16]	447	1			T74	5		T455	2		T525	1
all_values[17]	503	1			T455	3		T521	2		T809	1
all_values[18]	487	1			T74	3		T455	2		T456	1
all_values[19]	502	1			T74	2		T455	2		T456	1
all_values[20]	533	1			T74	4		T455	2		T520	1
all_values[21]	456	1			T74	1		T455	3		T521	1
all_values[22]	508	1			T74	3		T455	3		T521	1
all_values[23]	483	1			T74	6		T455	2		T456	1
all_values[24]	485	1			T74	2		T455	1		T521	4
all_values[25]	463	1			T74	2		T456	1		T521	1
all_values[26]	490	1			T74	5		T455	1		T520	1
all_values[27]	496	1			T74	5		T455	3		T521	3
all_values[28]	498	1			T74	1		T455	2		T521	1
all_values[29]	498	1			T74	2		T455	1		T456	1
all_values[30]	490	1			T74	1		T455	5		T521	1
all_values[31]	510	1			T74	5		T455	5		T520	1
all_values[32]	504	1			T74	4		T455	3		T521	4
all_values[33]	501	1			T74	6		T455	2		T520	1
all_values[34]	507	1			T74	4		T455	2		T521	3
all_values[35]	553	1			T74	5		T455	2		T456	1
all_values[36]	473	1			T74	2		T455	5		T456	1
all_values[37]	501	1			T74	1		T455	4		T521	4
all_values[38]	498	1			T74	5		T455	2		T521	1
all_values[39]	467	1			T74	3		T455	4		T520	1
all_values[40]	519	1			T74	8		T455	2		T456	1
all_values[41]	480	1			T74	1		T455	2		T521	2
all_values[42]	466	1			T74	8		T455	1		T521	2
all_values[43]	503	1			T74	2		T455	2		T521	2
all_values[44]	493	1			T74	3		T455	3		T520	1
all_values[45]	490	1			T74	3		T455	1		T520	1
all_values[46]	536	1			T74	6		T455	3		T521	3
all_values[47]	490	1			T455	4		T521	1		T525	2
all_values[48]	490	1			T74	3		T455	2		T521	3
all_values[49]	452	1			T455	1		T521	4		T525	2