Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3584	1			T74	14		T455	28		T456	3
all_values[1]	3794	1			T74	14		T455	46		T466	1
all_values[2]	3700	1			T74	23		T455	30		T456	1
all_values[3]	3652	1			T74	13		T455	37		T456	1
all_values[4]	3585	1			T74	18		T455	40		T456	4
all_values[5]	3584	1			T74	20		T455	33		T466	2
all_values[6]	3598	1			T74	8		T455	32		T456	4
all_values[7]	3624	1			T74	13		T455	36		T456	1
all_values[8]	3737	1			T74	9		T455	28		T456	2
all_values[9]	3667	1			T74	11		T455	41		T456	2
all_values[10]	3530	1			T74	8		T455	38		T456	1
all_values[11]	3706	1			T74	11		T455	32		T456	2
all_values[12]	3623	1			T74	14		T455	37		T456	1
all_values[13]	3696	1			T74	18		T455	41		T456	2
all_values[14]	3716	1			T74	15		T455	43		T456	2
all_values[15]	3634	1			T74	21		T455	41		T456	1
all_values[16]	3610	1			T74	9		T455	40		T456	1
all_values[17]	3606	1			T74	15		T455	42		T456	3
all_values[18]	3617	1			T74	14		T455	41		T456	2
all_values[19]	3634	1			T74	20		T455	35		T466	2
all_values[20]	3649	1			T74	12		T455	22		T456	4
all_values[21]	3586	1			T74	9		T455	34		T456	2
all_values[22]	3672	1			T74	20		T455	39		T456	2
all_values[23]	3670	1			T74	12		T455	47		T456	1
all_values[24]	3634	1			T74	12		T455	30		T456	1
all_values[25]	3641	1			T74	18		T455	45		T456	4
all_values[26]	3731	1			T74	9		T455	29		T456	3
all_values[27]	3599	1			T74	10		T455	35		T456	2
all_values[28]	3693	1			T74	15		T455	35		T456	2
all_values[29]	3689	1			T74	16		T455	31		T456	1
all_values[30]	3653	1			T74	12		T455	34		T456	2
all_values[31]	3654	1			T74	17		T455	26		T456	4
all_values[32]	3623	1			T74	16		T455	29		T456	2
all_values[33]	3710	1			T74	12		T455	37		T456	1
all_values[34]	3695	1			T74	22		T455	40		T456	3
all_values[35]	3666	1			T74	17		T455	31		T456	1
all_values[36]	3594	1			T74	15		T455	39		T456	1
all_values[37]	3690	1			T74	19		T455	32		T466	4
all_values[38]	3571	1			T74	17		T455	33		T456	4
all_values[39]	3604	1			T74	15		T455	37		T456	2
all_values[40]	3609	1			T74	13		T455	45		T456	2
all_values[41]	3619	1			T74	13		T455	35		T456	4
all_values[42]	3515	1			T74	9		T455	52		T456	4
all_values[43]	3661	1			T74	15		T455	48		T466	1
all_values[44]	3629	1			T74	18		T455	26		T456	2
all_values[45]	3639	1			T74	14		T455	40		T456	2
all_values[46]	3664	1			T74	12		T455	31		T456	2
all_values[47]	3721	1			T74	22		T455	38		T456	2
all_values[48]	3686	1			T74	15		T455	35		T456	5
all_values[49]	3710	1			T74	17		T455	36		T456	3
all_values[50]	3612	1			T74	16		T455	41		T456	1
all_values[51]	3499	1			T74	10		T455	30		T466	3
all_values[52]	3650	1			T74	15		T455	26		T456	1
all_values[53]	3675	1			T74	17		T455	32		T466	1
all_values[54]	3717	1			T74	14		T455	45		T456	2
all_values[55]	3657	1			T74	12		T455	32		T456	2
all_values[56]	3753	1			T74	19		T455	32		T466	2
all_values[57]	3461	1			T74	7		T455	34		T456	1
all_values[58]	3662	1			T74	12		T455	32		T466	4
all_values[59]	3640	1			T74	15		T455	29		T456	2
all_values[60]	3669	1			T74	13		T455	34		T456	3
all_values[61]	3648	1			T74	13		T455	42		T456	1
all_values[62]	3647	1			T74	17		T455	41		T456	1
all_values[63]	3640	1			T74	15		T455	39		T456	2