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 LINE       17998
 EXPRESSION (addr_hit[198] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T256,T61
1	0	1	Covered	T148,T149,T534
1	1	0	Covered	T535,T541,T552
1	1	1	Covered	T2,T256,T61

 LINE       18001
 EXPRESSION (addr_hit[199] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T256,T61
1	0	1	Covered	T2,T256,T222
1	1	0	Not Covered
1	1	1	Covered	T2,T256,T222

 LINE       18002
 EXPRESSION (addr_hit[199] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T256,T61
1	0	1	Covered	T2,T256,T222
1	1	0	Covered	T534,T538,T568
1	1	1	Covered	T2,T256,T222

 LINE       18005
 EXPRESSION (addr_hit[200] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T256,T61
1	0	1	Covered	T690,T691,T148
1	1	0	Covered	T568,T684,T686
1	1	1	Covered	T252,T253,T254

 LINE       18008
 EXPRESSION (addr_hit[201] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T256,T61
1	0	1	Covered	T148,T149,T534
1	1	0	Covered	T534,T538,T552
1	1	1	Covered	T49,T50,T51