Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4023921	1			T80	2417		T81	2017		T82	109
values[2]	794695	1			T81	504		T82	47		T155	365
values[3]	111039	1			T82	3		T155	7		T529	16
values[4]	59663	1			T529	16		T254	2		T255	1
values[5]	39843	1			T529	16		T752	3		T427	42
values[6]	29746	1			T529	16		T752	3		T427	12
values[7]	24251	1			T529	16		T752	3		T427	12
values[8]	20796	1			T529	16		T752	3		T427	9
values[9]	17985	1			T529	16		T752	3		T427	5
values[10]	16648	1			T529	16		T752	3		T427	4
values[11]	15195	1			T529	17		T752	3		T427	7
values[12]	14444	1			T529	16		T752	4		T427	5
values[13]	13886	1			T529	17		T752	3		T427	8
values[14]	13583	1			T529	18		T752	3		T427	6
values[15]	12924	1			T529	16		T752	3		T427	7
values[16]	12242	1			T529	16		T752	3		T427	7
values[17]	11960	1			T529	16		T752	4		T427	7
values[18]	11635	1			T529	17		T752	3		T427	10
values[19]	11192	1			T529	17		T752	3		T427	5
values[20]	10756	1			T529	16		T752	3		T427	14
values[21]	10567	1			T529	17		T752	3		T427	11
values[22]	10215	1			T529	16		T752	3		T427	3
values[23]	9848	1			T529	17		T752	3		T427	3
values[24]	9569	1			T529	16		T752	3		T427	6
values[25]	9024	1			T529	16		T752	3		T427	5
values[26]	8868	1			T529	16		T752	3		T427	1
values[27]	8507	1			T529	16		T752	3		T427	2
values[28]	7941	1			T529	16		T752	3		T427	1
values[29]	7428	1			T529	16		T752	3		T427	2
values[30]	6946	1			T529	17		T752	3		T427	8
values[31]	6473	1			T529	16		T752	3		T427	4
values[32]	6112	1			T529	16		T752	3		T427	5
values[33]	5506	1			T529	16		T752	4		T427	3
values[34]	5113	1			T529	16		T752	3		T427	4
values[35]	4822	1			T529	17		T752	3		T427	4
values[36]	4483	1			T529	16		T752	3		T427	4
values[37]	4294	1			T529	17		T752	3		T427	3
values[38]	4266	1			T529	16		T752	3		T427	5
values[39]	4068	1			T529	16		T752	3		T427	2
values[40]	3786	1			T529	16		T752	3		T427	5
values[41]	3603	1			T529	16		T752	3		T427	1
values[42]	3551	1			T529	16		T752	3		T427	1
values[43]	3453	1			T529	16		T752	3		T427	4
values[44]	3367	1			T529	17		T752	3		T427	2
values[45]	3482	1			T529	18		T752	3		T427	10
values[46]	3231	1			T529	16		T752	3		T427	5
values[47]	3135	1			T529	16		T752	3		T456	9
values[48]	3066	1			T529	16		T752	3		T456	8
values[49]	3057	1			T529	16		T752	3		T456	6
values[50]	2902	1			T529	17		T752	3		T456	16
values[51]	2897	1			T529	16		T752	3		T456	7
values[52]	2852	1			T529	17		T752	3		T456	15
values[53]	2735	1			T529	16		T752	3		T456	4
values[54]	2752	1			T529	16		T752	3		T456	8
values[55]	2690	1			T529	16		T752	3		T456	6
values[56]	2669	1			T529	17		T752	3		T456	9
values[57]	2614	1			T529	16		T752	3		T456	10
values[58]	2558	1			T529	16		T752	3		T456	6
values[59]	2523	1			T529	17		T752	3		T456	8
values[60]	2538	1			T529	16		T752	5		T456	3
values[61]	2868	1			T529	16		T752	3		T456	2
values[62]	4223	1			T529	16		T752	3		T448	20
values[63]	10950	1			T529	17		T752	5		T448	41
values[64]	235984	1			T529	3075		T752	557		T448	66

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	5123366	1			T80	2351		T81	1994		T82	80
values[2]	855611	1			T81	528		T82	18		T155	321
values[3]	85615	1			T81	14		T82	4		T155	57
values[4]	15091	1			T81	2		T82	2		T155	3
values[5]	5881	1			T529	23		T254	12		T255	1
values[6]	3552	1			T529	5		T254	4		T255	1
values[7]	2771	1			T529	2		T254	2		T255	1
values[8]	2292	1			T529	2		T255	1		T456	2
values[9]	2049	1			T529	2		T456	2		T504	7
values[10]	1835	1			T529	2		T456	2		T504	4
values[11]	1740	1			T529	2		T456	4		T504	4
values[12]	1598	1			T529	2		T456	2		T504	4
values[13]	1481	1			T529	2		T456	2		T504	3
values[14]	1359	1			T529	2		T456	1		T504	7
values[15]	1327	1			T529	2		T456	1		T504	8
values[16]	1117	1			T529	2		T456	2		T504	7
values[17]	1031	1			T529	2		T456	2		T504	13
values[18]	1038	1			T529	2		T456	2		T504	12
values[19]	1007	1			T529	2		T456	2		T504	12
values[20]	990	1			T529	2		T456	2		T504	10
values[21]	996	1			T529	2		T456	2		T504	7
values[22]	938	1			T529	2		T456	2		T450	3
values[23]	925	1			T529	2		T456	2		T450	7
values[24]	844	1			T529	2		T456	2		T450	16
values[25]	758	1			T529	2		T456	2		T450	32
values[26]	761	1			T529	2		T456	2		T450	13
values[27]	805	1			T529	2		T456	2		T450	4
values[28]	778	1			T529	2		T456	2		T450	10
values[29]	731	1			T529	2		T456	2		T450	7
values[30]	726	1			T529	2		T456	2		T450	1
values[31]	639	1			T529	2		T456	2		T839	1
values[32]	628	1			T529	2		T456	2		T839	1
values[33]	617	1			T529	2		T456	2		T839	1
values[34]	614	1			T529	2		T456	2		T839	1
values[35]	566	1			T529	2		T456	2		T839	1
values[36]	576	1			T529	2		T456	2		T839	1
values[37]	518	1			T529	2		T456	2		T839	1
values[38]	524	1			T529	2		T456	2		T839	1
values[39]	514	1			T529	2		T456	2		T839	1
values[40]	491	1			T529	2		T456	2		T839	1
values[41]	516	1			T529	2		T456	2		T839	1
values[42]	521	1			T529	2		T456	2		T839	1
values[43]	523	1			T529	2		T456	2		T839	1
values[44]	523	1			T529	2		T456	1		T839	2
values[45]	461	1			T529	3		T456	1		T839	1
values[46]	440	1			T529	2		T456	2		T839	1
values[47]	442	1			T529	2		T456	3		T839	1
values[48]	430	1			T529	2		T456	2		T839	1
values[49]	431	1			T529	2		T456	2		T839	1
values[50]	396	1			T529	2		T456	2		T839	1
values[51]	399	1			T529	2		T456	2		T839	1
values[52]	419	1			T529	2		T456	2		T839	1
values[53]	385	1			T529	2		T456	2		T839	1
values[54]	377	1			T529	2		T456	2		T839	1
values[55]	367	1			T529	2		T456	1		T839	1
values[56]	378	1			T529	2		T456	1		T839	1
values[57]	366	1			T529	2		T456	2		T839	1
values[58]	395	1			T529	2		T456	3		T839	1
values[59]	395	1			T529	2		T456	2		T839	1
values[60]	392	1			T529	2		T456	2		T839	1
values[61]	425	1			T529	2		T456	2		T839	1
values[62]	679	1			T529	2		T456	2		T839	1
values[63]	2550	1			T529	2		T456	3		T839	1
values[64]	27657	1			T529	382		T456	129		T839	217

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	601492	1			T80	2363		T81	17		T82	1
values[2]	2858160	1			T81	2062		T82	1		T155	1240
values[3]	1280217	1			T81	523		T82	75		T155	324
values[4]	154323	1			T81	1		T82	30		T155	6
values[5]	79838	1			T82	4		T529	16		T254	2
values[6]	51968	1			T529	16		T752	3		T427	21
values[7]	37585	1			T529	16		T752	3		T427	5
values[8]	30531	1			T529	16		T752	3		T427	5
values[9]	25539	1			T529	16		T752	3		T427	3
values[10]	22633	1			T529	16		T752	3		T427	4
values[11]	20199	1			T529	16		T752	3		T427	3
values[12]	18267	1			T529	16		T752	3		T427	1
values[13]	17346	1			T529	16		T752	3		T427	2
values[14]	16759	1			T529	16		T752	3		T427	4
values[15]	16228	1			T529	16		T752	3		T427	1
values[16]	15327	1			T529	16		T752	3		T427	1
values[17]	14875	1			T529	16		T752	3		T456	62
values[18]	13937	1			T529	16		T752	3		T456	65
values[19]	13453	1			T529	16		T752	3		T456	73
values[20]	12628	1			T529	16		T752	3		T456	68
values[21]	12054	1			T529	16		T752	3		T456	74
values[22]	11484	1			T529	16		T752	3		T456	58
values[23]	10853	1			T529	16		T752	3		T456	64
values[24]	10621	1			T529	16		T752	3		T456	56
values[25]	10101	1			T529	16		T752	3		T456	27
values[26]	9651	1			T529	16		T752	3		T456	30
values[27]	9420	1			T529	16		T752	3		T456	24
values[28]	8906	1			T529	16		T752	3		T456	33
values[29]	8331	1			T529	17		T752	3		T456	28
values[30]	7641	1			T529	16		T752	3		T456	26
values[31]	7243	1			T529	16		T752	3		T456	25
values[32]	6663	1			T529	16		T752	3		T456	19
values[33]	6221	1			T529	16		T752	3		T456	11
values[34]	5852	1			T529	17		T752	3		T456	16
values[35]	5336	1			T529	16		T752	3		T456	8
values[36]	4990	1			T529	16		T752	3		T456	13
values[37]	4653	1			T529	16		T752	3		T456	6
values[38]	4457	1			T529	16		T752	3		T456	7
values[39]	4247	1			T529	17		T752	3		T456	13
values[40]	4100	1			T529	16		T752	3		T456	3
values[41]	4078	1			T529	17		T752	3		T456	4
values[42]	3953	1			T529	16		T752	3		T456	7
values[43]	3847	1			T529	16		T752	3		T456	6
values[44]	3625	1			T529	16		T752	3		T456	1
values[45]	3527	1			T529	16		T752	3		T448	2
values[46]	3415	1			T529	16		T752	3		T448	3
values[47]	3535	1			T529	16		T752	3		T448	1
values[48]	3443	1			T529	16		T752	3		T448	1
values[49]	3260	1			T529	16		T752	3		T448	6
values[50]	3190	1			T529	16		T752	3		T448	3
values[51]	3091	1			T529	16		T752	3		T448	3
values[52]	3016	1			T529	16		T752	3		T448	1
values[53]	3082	1			T529	16		T752	3		T448	2
values[54]	3109	1			T529	16		T752	3		T448	1
values[55]	3063	1			T529	16		T752	3		T448	6
values[56]	2991	1			T529	17		T752	3		T448	2
values[57]	2962	1			T529	17		T752	3		T448	2
values[58]	2789	1			T529	16		T752	3		T448	1
values[59]	2660	1			T529	16		T752	3		T448	2
values[60]	2687	1			T529	16		T752	3		T448	3
values[61]	2864	1			T529	16		T752	3		T448	2
values[62]	3798	1			T529	16		T752	3		T448	1
values[63]	9079	1			T529	17		T752	3		T448	25
values[64]	226913	1			T529	3089		T752	535		T448	51