Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2186328	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

37836424

1

T1

6422

T2

8760

T3

10645

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	28174228	1			T1	2544		T2	4303		T3	4242
values[0x0]	10363912	1			T1	3878		T2	4457		T3	6403
values[0x1]	1484612	1			T1	249		T2	547		T3	631

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	806413	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

39216339

1

T1

6671

T2

9307

T3

11276

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18623191	1			T1	3336		T2	4654		T3	5638
valid_sources[0x01]	18621856	1			T1	3335		T2	4653		T3	5638
valid_sources[0x02]	44863	1			T151	101		T392	222		T401	111
valid_sources[0x03]	44599	1			T151	61		T392	242		T401	135
valid_sources[0x04]	44253	1			T151	119		T392	241		T401	101
valid_sources[0x05]	43696	1			T151	90		T392	249		T401	110
valid_sources[0x06]	46121	1			T74	7		T151	102		T392	280
valid_sources[0x07]	44594	1			T151	111		T392	271		T401	118
valid_sources[0x08]	44734	1			T151	70		T392	266		T401	155
valid_sources[0x09]	43040	1			T211	34		T151	54		T392	246
valid_sources[0x0a]	44719	1			T151	98		T392	243		T401	115
valid_sources[0x0b]	44188	1			T211	5		T151	86		T392	226
valid_sources[0x0c]	45595	1			T151	94		T392	246		T401	123
valid_sources[0x0d]	44158	1			T74	3		T209	1		T151	87
valid_sources[0x0e]	45585	1			T151	84		T392	257		T401	125
valid_sources[0x0f]	47427	1			T151	92		T392	242		T401	135
valid_sources[0x10]	45138	1			T151	80		T392	261		T401	102
valid_sources[0x11]	44542	1			T151	75		T392	249		T401	125
valid_sources[0x12]	44401	1			T151	69		T392	268		T401	133
valid_sources[0x13]	44414	1			T151	88		T392	267		T401	129
valid_sources[0x14]	43729	1			T79	39		T151	59		T392	251
valid_sources[0x15]	45819	1			T151	97		T392	232		T401	119
valid_sources[0x16]	45999	1			T151	70		T392	239		T401	119
valid_sources[0x17]	46069	1			T74	2		T151	85		T392	246
valid_sources[0x18]	45796	1			T74	8		T209	2		T151	97
valid_sources[0x19]	44373	1			T74	8		T151	98		T392	240
valid_sources[0x1a]	45467	1			T209	3		T151	67		T392	225
valid_sources[0x1b]	44108	1			T151	110		T392	267		T401	114
valid_sources[0x1c]	45142	1			T209	2		T151	91		T392	255
valid_sources[0x1d]	44606	1			T209	3		T151	99		T392	251
valid_sources[0x1e]	45760	1			T151	103		T392	246		T401	124
valid_sources[0x1f]	45146	1			T151	107		T392	226		T401	118
valid_sources[0x20]	43987	1			T151	84		T392	228		T401	135

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27263921

1

T1

2544

T2

4303

T3

4242

values[0x0]

all_enables

biggest_size

10305033

1

T1

3878

T2

4457

T3

6403

values[0x1]

all_enables

biggest_size

267470

1

T74

15

T79

25

T57

23

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2937894	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

463142

1

T80

326

T81

319

T82

27

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1152351	1			T80	847		T81	874		T82	52
values[0x0]	1095739	1			T80	779		T81	843		T82	55
values[0x1]	1152946	1			T80	791		T81	804		T82	52

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2274018	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1127018

1

T80

777

T81

831

T82

59

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54005	1			T80	38		T81	45		T82	10
valid_sources[0x01]	53506	1			T80	64		T81	34		T155	54
valid_sources[0x02]	53683	1			T80	42		T81	28		T82	2
valid_sources[0x03]	52502	1			T80	18		T81	56		T155	50
valid_sources[0x04]	53106	1			T80	33		T81	41		T155	45
valid_sources[0x05]	53671	1			T80	7		T81	39		T155	83
valid_sources[0x06]	52637	1			T80	19		T81	22		T82	4
valid_sources[0x07]	52311	1			T80	35		T81	45		T82	1
valid_sources[0x08]	53259	1			T80	28		T81	23		T82	4
valid_sources[0x09]	52264	1			T80	29		T81	79		T82	16
valid_sources[0x0a]	52543	1			T80	36		T81	23		T155	51
valid_sources[0x0b]	52912	1			T80	40		T81	46		T82	5
valid_sources[0x0c]	53635	1			T80	19		T81	34		T82	1
valid_sources[0x0d]	53923	1			T80	21		T81	37		T155	62
valid_sources[0x0e]	54047	1			T80	34		T81	18		T155	49
valid_sources[0x0f]	53830	1			T81	40		T155	36		T256	78
valid_sources[0x10]	53853	1			T80	84		T81	53		T82	1
valid_sources[0x11]	53164	1			T80	99		T81	45		T155	33
valid_sources[0x12]	54096	1			T80	35		T81	22		T155	58
valid_sources[0x13]	52967	1			T80	23		T81	33		T155	22
valid_sources[0x14]	52630	1			T80	36		T81	35		T155	35
valid_sources[0x15]	53307	1			T81	80		T155	40		T256	39
valid_sources[0x16]	53005	1			T80	43		T81	34		T155	43
valid_sources[0x17]	54129	1			T80	19		T81	32		T155	84
valid_sources[0x18]	53385	1			T80	45		T81	25		T155	49
valid_sources[0x19]	53516	1			T80	32		T81	31		T155	71
valid_sources[0x1a]	52365	1			T80	12		T81	70		T155	52
valid_sources[0x1b]	52802	1			T80	23		T81	46		T155	38
valid_sources[0x1c]	53475	1			T80	20		T81	21		T82	14
valid_sources[0x1d]	53424	1			T80	42		T81	18		T82	8
valid_sources[0x1e]	52167	1			T80	29		T81	39		T155	46
valid_sources[0x1f]	52822	1			T80	29		T81	42		T155	37
valid_sources[0x20]	53210	1			T80	15		T81	38		T82	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48723

1

T80

38

T81

40

T82

2

values[0x0]

all_enables

biggest_size

365874

1

T80

257

T81

255

T82

24

values[0x1]

all_enables

biggest_size

48545

1

T80

31

T81

24

T82

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3136521	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

509443

1

T80

325

T81

346

T82

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1248997	1			T80	778		T81	867		T82	29
values[0x0]	1146599	1			T80	740		T81	875		T82	44
values[0x1]	1250368	1			T80	833		T81	796		T82	31

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2404917	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1241047

1

T80

835

T81

823

T82

35

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55961	1			T80	28		T81	42		T82	3
valid_sources[0x01]	56159	1			T80	64		T81	39		T82	1
valid_sources[0x02]	56834	1			T80	54		T81	44		T82	2
valid_sources[0x03]	57277	1			T80	11		T81	33		T155	52
valid_sources[0x04]	55974	1			T80	29		T81	32		T82	1
valid_sources[0x05]	57211	1			T80	18		T81	29		T82	3
valid_sources[0x06]	57214	1			T80	12		T81	43		T82	3
valid_sources[0x07]	57064	1			T80	13		T81	35		T155	47
valid_sources[0x08]	57696	1			T80	32		T81	45		T82	2
valid_sources[0x09]	55917	1			T80	33		T81	40		T155	76
valid_sources[0x0a]	56668	1			T80	43		T81	36		T82	4
valid_sources[0x0b]	57574	1			T80	27		T81	37		T82	2
valid_sources[0x0c]	56740	1			T80	17		T81	38		T82	7
valid_sources[0x0d]	57436	1			T80	26		T81	41		T82	3
valid_sources[0x0e]	57824	1			T80	24		T81	36		T82	4
valid_sources[0x0f]	57186	1			T81	48		T82	1		T155	35
valid_sources[0x10]	57470	1			T80	77		T81	38		T82	1
valid_sources[0x11]	57012	1			T80	109		T81	48		T82	1
valid_sources[0x12]	56605	1			T80	69		T81	59		T155	80
valid_sources[0x13]	56262	1			T80	23		T81	37		T155	34
valid_sources[0x14]	56856	1			T80	36		T81	32		T82	1
valid_sources[0x15]	56598	1			T81	40		T82	2		T155	43
valid_sources[0x16]	56767	1			T80	30		T81	43		T82	5
valid_sources[0x17]	57099	1			T80	34		T81	49		T155	86
valid_sources[0x18]	58256	1			T80	31		T81	39		T82	1
valid_sources[0x19]	57094	1			T80	35		T81	38		T155	62
valid_sources[0x1a]	57312	1			T80	30		T81	43		T82	1
valid_sources[0x1b]	55902	1			T80	42		T81	21		T155	57
valid_sources[0x1c]	57409	1			T80	15		T81	59		T82	2
valid_sources[0x1d]	57261	1			T80	37		T81	44		T155	42
valid_sources[0x1e]	57116	1			T80	24		T81	45		T82	2
valid_sources[0x1f]	57737	1			T80	47		T81	40		T82	2
valid_sources[0x20]	57311	1			T80	21		T81	41		T155	31

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

53816

1

T80

25

T81

29

T82

1

values[0x0]

all_enables

biggest_size

401892

1

T80

275

T81

285

T82

14

values[0x1]

all_enables

biggest_size

53735

1

T80

25

T81

32

T82

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2960117	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

468108

1

T80

314

T81

354

T82

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1160370	1			T80	778		T81	860		T82	39
values[0x0]	1104920	1			T80	782		T81	851		T82	36
values[0x1]	1162935	1			T80	803		T81	892		T82	36

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2292390	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1135835

1

T80

806

T81

858

T82

36

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53196	1			T80	32		T81	19		T82	5
valid_sources[0x01]	54439	1			T80	76		T81	14		T82	4
valid_sources[0x02]	52817	1			T80	52		T81	70		T82	1
valid_sources[0x03]	52954	1			T80	5		T81	34		T82	2
valid_sources[0x04]	53031	1			T80	22		T81	7		T82	1
valid_sources[0x05]	54917	1			T80	19		T81	25		T155	71
valid_sources[0x06]	53941	1			T80	11		T81	20		T82	2
valid_sources[0x07]	53170	1			T80	27		T81	17		T155	23
valid_sources[0x08]	53733	1			T80	31		T81	17		T82	1
valid_sources[0x09]	52860	1			T80	27		T81	78		T155	44
valid_sources[0x0a]	53285	1			T80	42		T81	23		T82	3
valid_sources[0x0b]	53658	1			T80	23		T81	49		T82	4
valid_sources[0x0c]	54245	1			T80	8		T81	49		T155	69
valid_sources[0x0d]	53843	1			T80	17		T81	30		T82	4
valid_sources[0x0e]	54315	1			T80	23		T81	42		T82	3
valid_sources[0x0f]	53704	1			T81	47		T82	1		T155	77
valid_sources[0x10]	53594	1			T80	67		T81	50		T82	2
valid_sources[0x11]	54143	1			T80	79		T81	25		T82	1
valid_sources[0x12]	53932	1			T80	70		T81	36		T155	53
valid_sources[0x13]	52446	1			T80	36		T81	27		T82	7
valid_sources[0x14]	54021	1			T80	29		T81	48		T82	1
valid_sources[0x15]	53685	1			T81	27		T82	1		T155	30
valid_sources[0x16]	52923	1			T80	49		T81	23		T82	1
valid_sources[0x17]	53022	1			T80	37		T81	52		T155	90
valid_sources[0x18]	54333	1			T80	44		T81	36		T82	3
valid_sources[0x19]	54108	1			T80	22		T81	65		T82	1
valid_sources[0x1a]	53872	1			T80	32		T81	47		T82	2
valid_sources[0x1b]	53344	1			T80	47		T81	26		T82	3
valid_sources[0x1c]	52587	1			T80	18		T81	25		T155	71
valid_sources[0x1d]	53651	1			T80	50		T81	51		T82	2
valid_sources[0x1e]	53181	1			T80	33		T81	45		T82	2
valid_sources[0x1f]	53415	1			T80	64		T81	20		T82	2
valid_sources[0x20]	53423	1			T80	25		T81	36		T155	23

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49192

1

T80

28

T81

36

T82

3

values[0x0]

all_enables

biggest_size

369273

1

T80

249

T81

275

T82

12

values[0x1]

all_enables

biggest_size

49643

1

T80

37

T81

43

T155

47