Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	525210559	61292520	0	0
DepthKnown_A	525210559	525105805	0	0
RvalidKnown_A	525210559	525105805	0	0
WreadyKnown_A	525210559	525105805	0	0
gen_passthru_fifo.paramCheckPass	1023	1023	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	61292520	0	0
T1	111353	71789	0	0
T2	158492	21444	0	0
T3	184459	25352	0	0
T30	300160	36486	0	0
T46	136165	146985	0	0
T47	133344	146915	0	0
T51	40982	0	0	0
T66	139717	19222	0	0
T88	66136	7696	0	0
T89	60675	5762	0	0
T163	0	18914	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	525105805	0	0
T1	111353	111302	0	0
T2	158492	158434	0	0
T3	184459	184358	0	0
T30	300160	299992	0	0
T46	136165	136159	0	0
T47	133344	133338	0	0
T51	40982	40927	0	0
T66	139717	139655	0	0
T88	66136	66081	0	0
T89	60675	60624	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	525105805	0	0
T1	111353	111302	0	0
T2	158492	158434	0	0
T3	184459	184358	0	0
T30	300160	299992	0	0
T46	136165	136159	0	0
T47	133344	133338	0	0
T51	40982	40927	0	0
T66	139717	139655	0	0
T88	66136	66081	0	0
T89	60675	60624	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	525105805	0	0
T1	111353	111302	0	0
T2	158492	158434	0	0
T3	184459	184358	0	0
T30	300160	299992	0	0
T46	136165	136159	0	0
T47	133344	133338	0	0
T51	40982	40927	0	0
T66	139717	139655	0	0
T88	66136	66081	0	0
T89	60675	60624	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1023	1023	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T30	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T51	1	1	0	0
T66	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	525210559	47138557	0	0
DepthKnown_A	525210559	525105805	0	0
RvalidKnown_A	525210559	525105805	0	0
WreadyKnown_A	525210559	525105805	0	0
gen_passthru_fifo.paramCheckPass	1023	1023	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	47138557	0	0
T1	111353	35495	0	0
T2	158492	16258	0	0
T3	184459	18095	0	0
T30	300160	28684	0	0
T46	136165	128049	0	0
T47	133344	127960	0	0
T51	40982	0	0	0
T66	139717	14041	0	0
T88	66136	5143	0	0
T89	60675	4030	0	0
T163	0	13634	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	525105805	0	0
T1	111353	111302	0	0
T2	158492	158434	0	0
T3	184459	184358	0	0
T30	300160	299992	0	0
T46	136165	136159	0	0
T47	133344	133338	0	0
T51	40982	40927	0	0
T66	139717	139655	0	0
T88	66136	66081	0	0
T89	60675	60624	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	525105805	0	0
T1	111353	111302	0	0
T2	158492	158434	0	0
T3	184459	184358	0	0
T30	300160	299992	0	0
T46	136165	136159	0	0
T47	133344	133338	0	0
T51	40982	40927	0	0
T66	139717	139655	0	0
T88	66136	66081	0	0
T89	60675	60624	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	525105805	0	0
T1	111353	111302	0	0
T2	158492	158434	0	0
T3	184459	184358	0	0
T30	300160	299992	0	0
T46	136165	136159	0	0
T47	133344	133338	0	0
T51	40982	40927	0	0
T66	139717	139655	0	0
T88	66136	66081	0	0
T89	60675	60624	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1023	1023	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T30	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T51	1	1	0	0
T66	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	525210559	44415250	0	0
DepthKnown_A	525210559	525105805	0	0
RvalidKnown_A	525210559	525105805	0	0
WreadyKnown_A	525210559	525105805	0	0
gen_passthru_fifo.paramCheckPass	1023	1023	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	44415250	0	0
T1	111353	7332	0	0
T2	158492	9584	0	0
T3	184459	11679	0	0
T30	300160	18882	0	0
T46	136165	201712	0	0
T47	133344	175605	0	0
T51	40982	0	0	0
T66	139717	7985	0	0
T88	66136	3444	0	0
T89	60675	3280	0	0
T163	0	7615	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	525105805	0	0
T1	111353	111302	0	0
T2	158492	158434	0	0
T3	184459	184358	0	0
T30	300160	299992	0	0
T46	136165	136159	0	0
T47	133344	133338	0	0
T51	40982	40927	0	0
T66	139717	139655	0	0
T88	66136	66081	0	0
T89	60675	60624	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	525105805	0	0
T1	111353	111302	0	0
T2	158492	158434	0	0
T3	184459	184358	0	0
T30	300160	299992	0	0
T46	136165	136159	0	0
T47	133344	133338	0	0
T51	40982	40927	0	0
T66	139717	139655	0	0
T88	66136	66081	0	0
T89	60675	60624	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	525105805	0	0
T1	111353	111302	0	0
T2	158492	158434	0	0
T3	184459	184358	0	0
T30	300160	299992	0	0
T46	136165	136159	0	0
T47	133344	133338	0	0
T51	40982	40927	0	0
T66	139717	139655	0	0
T88	66136	66081	0	0
T89	60675	60624	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1023	1023	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T30	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T51	1	1	0	0
T66	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	525210559	37238346	0	0
DepthKnown_A	525210559	525105805	0	0
RvalidKnown_A	525210559	525105805	0	0
WreadyKnown_A	525210559	525105805	0	0
gen_passthru_fifo.paramCheckPass	1023	1023	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	37238346	0	0
T1	111353	6671	0	0
T2	158492	9307	0	0
T3	184459	11276	0	0
T30	300160	18489	0	0
T46	136165	119900	0	0
T47	133344	119806	0	0
T51	40982	0	0	0
T66	139717	7707	0	0
T88	66136	3314	0	0
T89	60675	3161	0	0
T163	0	7340	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	525105805	0	0
T1	111353	111302	0	0
T2	158492	158434	0	0
T3	184459	184358	0	0
T30	300160	299992	0	0
T46	136165	136159	0	0
T47	133344	133338	0	0
T51	40982	40927	0	0
T66	139717	139655	0	0
T88	66136	66081	0	0
T89	60675	60624	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	525105805	0	0
T1	111353	111302	0	0
T2	158492	158434	0	0
T3	184459	184358	0	0
T30	300160	299992	0	0
T46	136165	136159	0	0
T47	133344	133338	0	0
T51	40982	40927	0	0
T66	139717	139655	0	0
T88	66136	66081	0	0
T89	60675	60624	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	525105805	0	0
T1	111353	111302	0	0
T2	158492	158434	0	0
T3	184459	184358	0	0
T30	300160	299992	0	0
T46	136165	136159	0	0
T47	133344	133338	0	0
T51	40982	40927	0	0
T66	139717	139655	0	0
T88	66136	66081	0	0
T89	60675	60624	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1023	1023	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T30	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T51	1	1	0	0
T66	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	613790124	96119	0	0
DepthKnown_A	613790124	613669666	0	0
RvalidKnown_A	613790124	613669666	0	0
WreadyKnown_A	613790124	613669666	0	0
gen_passthru_fifo.paramCheckPass	2934	2934	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613790124	96119	0	0
T1	111353	34	0	0
T2	158492	26	0	0
T3	184459	40	0	0
T30	300160	68	0	0
T46	136165	34	0	0
T47	133344	34	0	0
T51	40982	0	0	0
T66	139717	26	0	0
T88	66136	13	0	0
T89	60675	15	0	0
T163	0	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613790124	613669666	0	0
T1	111353	111302	0	0
T2	158492	158434	0	0
T3	184459	184358	0	0
T30	300160	299992	0	0
T46	136165	136159	0	0
T47	133344	133338	0	0
T51	40982	40927	0	0
T66	139717	139655	0	0
T88	66136	66081	0	0
T89	60675	60624	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613790124	613669666	0	0
T1	111353	111302	0	0
T2	158492	158434	0	0
T3	184459	184358	0	0
T30	300160	299992	0	0
T46	136165	136159	0	0
T47	133344	133338	0	0
T51	40982	40927	0	0
T66	139717	139655	0	0
T88	66136	66081	0	0
T89	60675	60624	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613790124	613669666	0	0
T1	111353	111302	0	0
T2	158492	158434	0	0
T3	184459	184358	0	0
T30	300160	299992	0	0
T46	136165	136159	0	0
T47	133344	133338	0	0
T51	40982	40927	0	0
T66	139717	139655	0	0
T88	66136	66081	0	0
T89	60675	60624	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2934	2934	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T30	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T51	1	1	0	0
T66	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	613790124	99469	0	0
DepthKnown_A	613790124	613669666	0	0
RvalidKnown_A	613790124	613669666	0	0
WreadyKnown_A	613790124	613669666	0	0
gen_passthru_fifo.paramCheckPass	2934	2934	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613790124	99469	0	0
T1	111353	34	0	0
T2	158492	26	0	0
T3	184459	40	0	0
T30	300160	68	0	0
T46	136165	34	0	0
T47	133344	34	0	0
T51	40982	0	0	0
T66	139717	26	0	0
T88	66136	13	0	0
T89	60675	15	0	0
T163	0	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613790124	613669666	0	0
T1	111353	111302	0	0
T2	158492	158434	0	0
T3	184459	184358	0	0
T30	300160	299992	0	0
T46	136165	136159	0	0
T47	133344	133338	0	0
T51	40982	40927	0	0
T66	139717	139655	0	0
T88	66136	66081	0	0
T89	60675	60624	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613790124	613669666	0	0
T1	111353	111302	0	0
T2	158492	158434	0	0
T3	184459	184358	0	0
T30	300160	299992	0	0
T46	136165	136159	0	0
T47	133344	133338	0	0
T51	40982	40927	0	0
T66	139717	139655	0	0
T88	66136	66081	0	0
T89	60675	60624	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613790124	613669666	0	0
T1	111353	111302	0	0
T2	158492	158434	0	0
T3	184459	184358	0	0
T30	300160	299992	0	0
T46	136165	136159	0	0
T47	133344	133338	0	0
T51	40982	40927	0	0
T66	139717	139655	0	0
T88	66136	66081	0	0
T89	60675	60624	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2934	2934	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T30	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T51	1	1	0	0
T66	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	613790124	52745	0	0
DepthKnown_A	613790124	613669666	0	0
RvalidKnown_A	613790124	613669666	0	0
WreadyKnown_A	613790124	613669666	0	0
gen_passthru_fifo.paramCheckPass	2934	2934	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613790124	52745	0	0
T1	111353	31	0	0
T2	158492	23	0	0
T3	184459	34	0	0
T30	300160	59	0	0
T46	136165	5	0	0
T47	133344	5	0	0
T51	40982	0	0	0
T66	139717	23	0	0
T88	66136	12	0	0
T89	60675	14	0	0
T163	0	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613790124	613669666	0	0
T1	111353	111302	0	0
T2	158492	158434	0	0
T3	184459	184358	0	0
T30	300160	299992	0	0
T46	136165	136159	0	0
T47	133344	133338	0	0
T51	40982	40927	0	0
T66	139717	139655	0	0
T88	66136	66081	0	0
T89	60675	60624	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613790124	613669666	0	0
T1	111353	111302	0	0
T2	158492	158434	0	0
T3	184459	184358	0	0
T30	300160	299992	0	0
T46	136165	136159	0	0
T47	133344	133338	0	0
T51	40982	40927	0	0
T66	139717	139655	0	0
T88	66136	66081	0	0
T89	60675	60624	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613790124	613669666	0	0
T1	111353	111302	0	0
T2	158492	158434	0	0
T3	184459	184358	0	0
T30	300160	299992	0	0
T46	136165	136159	0	0
T47	133344	133338	0	0
T51	40982	40927	0	0
T66	139717	139655	0	0
T88	66136	66081	0	0
T89	60675	60624	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2934	2934	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T30	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T51	1	1	0	0
T66	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	613790124	52745	0	0
DepthKnown_A	613790124	613669666	0	0
RvalidKnown_A	613790124	613669666	0	0
WreadyKnown_A	613790124	613669666	0	0
gen_passthru_fifo.paramCheckPass	2934	2934	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613790124	52745	0	0
T1	111353	31	0	0
T2	158492	23	0	0
T3	184459	34	0	0
T30	300160	59	0	0
T46	136165	5	0	0
T47	133344	5	0	0
T51	40982	0	0	0
T66	139717	23	0	0
T88	66136	12	0	0
T89	60675	14	0	0
T163	0	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613790124	613669666	0	0
T1	111353	111302	0	0
T2	158492	158434	0	0
T3	184459	184358	0	0
T30	300160	299992	0	0
T46	136165	136159	0	0
T47	133344	133338	0	0
T51	40982	40927	0	0
T66	139717	139655	0	0
T88	66136	66081	0	0
T89	60675	60624	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613790124	613669666	0	0
T1	111353	111302	0	0
T2	158492	158434	0	0
T3	184459	184358	0	0
T30	300160	299992	0	0
T46	136165	136159	0	0
T47	133344	133338	0	0
T51	40982	40927	0	0
T66	139717	139655	0	0
T88	66136	66081	0	0
T89	60675	60624	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613790124	613669666	0	0
T1	111353	111302	0	0
T2	158492	158434	0	0
T3	184459	184358	0	0
T30	300160	299992	0	0
T46	136165	136159	0	0
T47	133344	133338	0	0
T51	40982	40927	0	0
T66	139717	139655	0	0
T88	66136	66081	0	0
T89	60675	60624	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2934	2934	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T30	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T51	1	1	0	0
T66	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	613790124	43374	0	0
DepthKnown_A	613790124	613669666	0	0
RvalidKnown_A	613790124	613669666	0	0
WreadyKnown_A	613790124	613669666	0	0
gen_passthru_fifo.paramCheckPass	2934	2934	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613790124	43374	0	0
T1	111353	3	0	0
T2	158492	3	0	0
T3	184459	6	0	0
T30	300160	9	0	0
T46	136165	29	0	0
T47	133344	29	0	0
T51	40982	0	0	0
T66	139717	3	0	0
T88	66136	1	0	0
T89	60675	1	0	0
T163	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613790124	613669666	0	0
T1	111353	111302	0	0
T2	158492	158434	0	0
T3	184459	184358	0	0
T30	300160	299992	0	0
T46	136165	136159	0	0
T47	133344	133338	0	0
T51	40982	40927	0	0
T66	139717	139655	0	0
T88	66136	66081	0	0
T89	60675	60624	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613790124	613669666	0	0
T1	111353	111302	0	0
T2	158492	158434	0	0
T3	184459	184358	0	0
T30	300160	299992	0	0
T46	136165	136159	0	0
T47	133344	133338	0	0
T51	40982	40927	0	0
T66	139717	139655	0	0
T88	66136	66081	0	0
T89	60675	60624	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613790124	613669666	0	0
T1	111353	111302	0	0
T2	158492	158434	0	0
T3	184459	184358	0	0
T30	300160	299992	0	0
T46	136165	136159	0	0
T47	133344	133338	0	0
T51	40982	40927	0	0
T66	139717	139655	0	0
T88	66136	66081	0	0
T89	60675	60624	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2934	2934	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T30	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T51	1	1	0	0
T66	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	613790124	46724	0	0
DepthKnown_A	613790124	613669666	0	0
RvalidKnown_A	613790124	613669666	0	0
WreadyKnown_A	613790124	613669666	0	0
gen_passthru_fifo.paramCheckPass	2934	2934	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613790124	46724	0	0
T1	111353	3	0	0
T2	158492	3	0	0
T3	184459	6	0	0
T30	300160	9	0	0
T46	136165	29	0	0
T47	133344	29	0	0
T51	40982	0	0	0
T66	139717	3	0	0
T88	66136	1	0	0
T89	60675	1	0	0
T163	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613790124	613669666	0	0
T1	111353	111302	0	0
T2	158492	158434	0	0
T3	184459	184358	0	0
T30	300160	299992	0	0
T46	136165	136159	0	0
T47	133344	133338	0	0
T51	40982	40927	0	0
T66	139717	139655	0	0
T88	66136	66081	0	0
T89	60675	60624	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613790124	613669666	0	0
T1	111353	111302	0	0
T2	158492	158434	0	0
T3	184459	184358	0	0
T30	300160	299992	0	0
T46	136165	136159	0	0
T47	133344	133338	0	0
T51	40982	40927	0	0
T66	139717	139655	0	0
T88	66136	66081	0	0
T89	60675	60624	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613790124	613669666	0	0
T1	111353	111302	0	0
T2	158492	158434	0	0
T3	184459	184358	0	0
T30	300160	299992	0	0
T46	136165	136159	0	0
T47	133344	133338	0	0
T51	40982	40927	0	0
T66	139717	139655	0	0
T88	66136	66081	0	0
T89	60675	60624	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2934	2934	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T30	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T51	1	1	0	0
T66	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0