Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T30,T31	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T46,T47,T126	Yes	T46,T47,T126	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T46,T47,T126	Yes	T46,T47,T126	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T50,*T74,*T83	Yes	T50,T74,T83	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T74,T79,T57	Yes	T74,T79,T57	INPUT
tl_i.a_valid	Yes	Yes	T46,T47,T68	Yes	T46,T47,T68	INPUT
tl_o.a_ready	Yes	Yes	T46,T47,T68	Yes	T46,T47,T68	OUTPUT
tl_o.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T46,T47,T126	Yes	T46,T47,T126	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T46,T47,T68	Yes	T46,T47,T68	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T46,T47,T68	Yes	T46,T47,T68	OUTPUT
tl_o.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T83,*T79,*T266	Yes	T83,T79,T266	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T46,*T47,*T126	Yes	T46,T47,T126	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T46,T47,T68	Yes	T46,T47,T68	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T68,T368,T84	Yes	T68,T368,T84	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T68,T368,T84	Yes	T68,T368,T84	OUTPUT
cio_rx_i	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T46,T47,T126	Yes	T46,T47,T126	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T126,T127,T224	Yes	T126,T127,T224	OUTPUT
intr_tx_empty_o	Yes	Yes	T126,T127,T224	Yes	T126,T127,T224	OUTPUT
intr_rx_watermark_o	Yes	Yes	T126,T127,T224	Yes	T126,T127,T224	OUTPUT
intr_tx_done_o	Yes	Yes	T126,T127,T224	Yes	T126,T127,T224	OUTPUT
intr_rx_overflow_o	Yes	Yes	T126,T127,T224	Yes	T126,T127,T224	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T320,T336,T333	Yes	T320,T336,T333	OUTPUT
intr_rx_break_err_o	Yes	Yes	T320,T336,T333	Yes	T320,T336,T333	OUTPUT
intr_rx_timeout_o	Yes	Yes	T320,T336,T333	Yes	T320,T336,T333	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T320,T336,T333	Yes	T320,T336,T333	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T30,T31	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T46,T47,T48	Yes	T46,T47,T48	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T46,T47,T48	Yes	T46,T47,T48	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T50,*T74,*T83	Yes	T50,T74,T83	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T74,T79,T57	Yes	T74,T79,T57	INPUT
tl_i.a_valid	Yes	Yes	T46,T47,T68	Yes	T46,T47,T68	INPUT
tl_o.a_ready	Yes	Yes	T46,T47,T68	Yes	T46,T47,T68	OUTPUT
tl_o.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T46,T47,T48	Yes	T46,T47,T48	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T46,T47,T68	Yes	T46,T47,T68	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T46,T47,T68	Yes	T46,T47,T68	OUTPUT
tl_o.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T155	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T83,*T79,*T266	Yes	T83,T79,T266	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T80,T81,T155	Yes	T80,T81,T82	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T46,*T47,*T48	Yes	T46,T47,T48	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T46,T47,T68	Yes	T46,T47,T68	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T68,T84,T52	Yes	T68,T84,T52	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T68,T84,T52	Yes	T68,T84,T52	OUTPUT
cio_rx_i	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T46,T47,T48	Yes	T46,T47,T48	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T320,T228,T321	Yes	T320,T228,T321	OUTPUT
intr_tx_empty_o	Yes	Yes	T320,T228,T321	Yes	T320,T228,T321	OUTPUT
intr_rx_watermark_o	Yes	Yes	T320,T228,T321	Yes	T320,T228,T321	OUTPUT
intr_tx_done_o	Yes	Yes	T320,T346,T228	Yes	T320,T346,T228	OUTPUT
intr_rx_overflow_o	Yes	Yes	T320,T346,T228	Yes	T320,T346,T228	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T320,T336,T333	Yes	T320,T336,T333	OUTPUT
intr_rx_break_err_o	Yes	Yes	T320,T336,T333	Yes	T320,T336,T333	OUTPUT
intr_rx_timeout_o	Yes	Yes	T320,T336,T333	Yes	T320,T336,T333	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T320,T336,T333	Yes	T320,T336,T333	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T30,T31	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T224,T320,T225	Yes	T224,T320,T225	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T224,T320,T225	Yes	T224,T320,T225	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T50,*T74,*T83	Yes	T50,T74,T83	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T74,T79,T57	Yes	T74,T79,T57	INPUT
tl_i.a_valid	Yes	Yes	T68,T224,T320	Yes	T68,T224,T320	INPUT
tl_o.a_ready	Yes	Yes	T68,T224,T320	Yes	T68,T224,T320	OUTPUT
tl_o.d_error	Yes	Yes	T80,T81,T155	Yes	T80,T81,T155	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T224,T320,T225	Yes	T224,T320,T225	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T68,T224,T320	Yes	T68,T224,T320	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T68,T224,T320	Yes	T68,T224,T320	OUTPUT
tl_o.d_sink	Yes	Yes	T80,T81,T155	Yes	T80,T81,T155	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T80,T81,T155	Yes	T80,T81,T82	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T224,*T320,*T225	Yes	T224,T320,T225	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T68,T224,T320	Yes	T68,T224,T320	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T68,T368,T84	Yes	T68,T368,T84	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T84,T85,T86	Yes	T84,T85,T269	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T84,T85,T269	Yes	T84,T85,T86	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T68,T368,T84	Yes	T68,T368,T84	OUTPUT
cio_rx_i	Yes	Yes	T224,T225,T364	Yes	T224,T7,T225	INPUT
cio_tx_o	Yes	Yes	T224,T225,T364	Yes	T224,T225,T364	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T224,T320,T225	Yes	T224,T320,T225	OUTPUT
intr_tx_empty_o	Yes	Yes	T224,T320,T225	Yes	T224,T320,T225	OUTPUT
intr_rx_watermark_o	Yes	Yes	T224,T320,T225	Yes	T224,T320,T225	OUTPUT
intr_tx_done_o	Yes	Yes	T224,T320,T225	Yes	T224,T320,T225	OUTPUT
intr_rx_overflow_o	Yes	Yes	T224,T320,T225	Yes	T224,T320,T225	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T320,T336,T333	Yes	T320,T336,T333	OUTPUT
intr_rx_break_err_o	Yes	Yes	T320,T336,T333	Yes	T320,T336,T333	OUTPUT
intr_rx_timeout_o	Yes	Yes	T320,T336,T333	Yes	T320,T336,T333	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T320,T336,T333	Yes	T320,T336,T333	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T30,T31	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T126,T127,T320	Yes	T126,T127,T320	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T126,T127,T320	Yes	T126,T127,T320	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T50,*T74,*T83	Yes	T50,T74,T83	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T74,T79,T57	Yes	T74,T79,T57	INPUT
tl_i.a_valid	Yes	Yes	T68,T126,T127	Yes	T68,T126,T127	INPUT
tl_o.a_ready	Yes	Yes	T68,T126,T127	Yes	T68,T126,T127	OUTPUT
tl_o.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T126,T127,T320	Yes	T126,T127,T320	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T68,T126,T127	Yes	T68,T126,T127	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T68,T126,T127	Yes	T68,T126,T127	OUTPUT
tl_o.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T126,*T127,*T320	Yes	T126,T127,T320	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T68,T126,T127	Yes	T68,T126,T127	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T68,T84,T221	Yes	T68,T84,T221	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T68,T84,T221	Yes	T68,T84,T221	OUTPUT
cio_rx_i	Yes	Yes	T126,T127,T279	Yes	T126,T127,T279	INPUT
cio_tx_o	Yes	Yes	T126,T127,T279	Yes	T126,T127,T279	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T126,T127,T320	Yes	T126,T127,T320	OUTPUT
intr_tx_empty_o	Yes	Yes	T126,T127,T320	Yes	T126,T127,T320	OUTPUT
intr_rx_watermark_o	Yes	Yes	T126,T127,T320	Yes	T126,T127,T320	OUTPUT
intr_tx_done_o	Yes	Yes	T126,T127,T320	Yes	T126,T127,T320	OUTPUT
intr_rx_overflow_o	Yes	Yes	T126,T127,T320	Yes	T126,T127,T320	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T320,T336,T333	Yes	T320,T336,T333	OUTPUT
intr_rx_break_err_o	Yes	Yes	T320,T336,T333	Yes	T320,T336,T333	OUTPUT
intr_rx_timeout_o	Yes	Yes	T320,T336,T333	Yes	T320,T336,T333	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T320,T336,T333	Yes	T320,T336,T333	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T30,T31	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T13,T14,T320	Yes	T13,T14,T320	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T13,T14,T320	Yes	T13,T14,T320	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T50,*T74,*T83	Yes	T50,T74,T83	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T74,T79,T57	Yes	T74,T79,T57	INPUT
tl_i.a_valid	Yes	Yes	T13,T68,T14	Yes	T13,T68,T14	INPUT
tl_o.a_ready	Yes	Yes	T13,T68,T14	Yes	T13,T68,T14	OUTPUT
tl_o.d_error	Yes	Yes	T80,T81,T155	Yes	T80,T81,T155	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T13,T14,T320	Yes	T13,T14,T320	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T13,T68,T14	Yes	T13,T68,T14	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T13,T68,T14	Yes	T13,T68,T14	OUTPUT
tl_o.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T13,*T14,*T320	Yes	T13,T14,T320	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T13,T68,T14	Yes	T13,T68,T14	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T68,T84,T52	Yes	T68,T84,T52	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T68,T84,T52	Yes	T68,T84,T52	OUTPUT
cio_rx_i	Yes	Yes	T13,T14,T365	Yes	T13,T14,T365	INPUT
cio_tx_o	Yes	Yes	T13,T14,T365	Yes	T13,T14,T365	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T13,T14,T320	Yes	T13,T14,T320	OUTPUT
intr_tx_empty_o	Yes	Yes	T13,T14,T320	Yes	T13,T14,T320	OUTPUT
intr_rx_watermark_o	Yes	Yes	T13,T14,T320	Yes	T13,T14,T320	OUTPUT
intr_tx_done_o	Yes	Yes	T13,T14,T320	Yes	T13,T14,T320	OUTPUT
intr_rx_overflow_o	Yes	Yes	T13,T14,T320	Yes	T13,T14,T320	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T320,T336,T333	Yes	T320,T336,T333	OUTPUT
intr_rx_break_err_o	Yes	Yes	T320,T336,T333	Yes	T320,T336,T333	OUTPUT
intr_rx_timeout_o	Yes	Yes	T320,T336,T333	Yes	T320,T336,T333	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T320,T336,T333	Yes	T320,T336,T333	OUTPUT

*Tests covering at least one bit in the range