Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T7,T10,T11 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T10,T11 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T7,T10,T11 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
30947 |
30422 |
0 |
0 |
T5 |
4 |
3 |
0 |
0 |
T10 |
187 |
186 |
0 |
0 |
T11 |
287 |
286 |
0 |
0 |
T15 |
33 |
32 |
0 |
0 |
T27 |
3 |
4 |
0 |
0 |
T28 |
4 |
3 |
0 |
0 |
T29 |
2 |
1 |
0 |
0 |
T33 |
7 |
6 |
0 |
0 |
T49 |
1 |
0 |
0 |
0 |
T50 |
3 |
2 |
0 |
0 |
T67 |
6 |
5 |
0 |
0 |
T105 |
3 |
2 |
0 |
0 |
T111 |
1 |
0 |
0 |
0 |
T125 |
2 |
1 |
0 |
0 |
T167 |
1 |
0 |
0 |
0 |
T175 |
0 |
3 |
0 |
0 |
T176 |
6 |
5 |
0 |
0 |
T192 |
0 |
2 |
0 |
0 |
T193 |
0 |
5 |
0 |
0 |
T194 |
6 |
5 |
0 |
0 |
T195 |
2 |
1 |
0 |
0 |
T196 |
7 |
6 |
0 |
0 |
T197 |
8 |
7 |
0 |
0 |
T198 |
6 |
5 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
149331 |
147917 |
0 |
0 |
T4 |
0 |
2 |
0 |
0 |
T5 |
0 |
5 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T27 |
35 |
33 |
0 |
0 |
T28 |
25 |
23 |
0 |
0 |
T29 |
10 |
8 |
0 |
0 |
T30 |
3 |
2 |
0 |
0 |
T31 |
2 |
1 |
0 |
0 |
T32 |
0 |
1 |
0 |
0 |
T33 |
35 |
33 |
0 |
0 |
T35 |
545 |
544 |
0 |
0 |
T68 |
0 |
4 |
0 |
0 |
T89 |
1 |
0 |
0 |
0 |
T118 |
1 |
0 |
0 |
0 |
T130 |
1 |
0 |
0 |
0 |
T131 |
0 |
1 |
0 |
0 |
T132 |
1 |
0 |
0 |
0 |
T135 |
1 |
0 |
0 |
0 |
T163 |
1 |
0 |
0 |
0 |
T189 |
0 |
1 |
0 |
0 |
T194 |
14 |
30 |
0 |
0 |
T195 |
15 |
29 |
0 |
0 |
T196 |
14 |
13 |
0 |
0 |
T197 |
11 |
10 |
0 |
0 |
T198 |
17 |
16 |
0 |
0 |
T199 |
0 |
1 |
0 |
0 |
T200 |
0 |
1 |
0 |
0 |
T201 |
18 |
17 |
0 |
0 |
T202 |
1 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T51,T5,T15 |
0 | 1 | Covered | T51,T5,T15 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T51,T5,T15 |
1 | 1 | Covered | T51,T5,T15 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
968 |
836 |
0 |
0 |
T5 |
4 |
3 |
0 |
0 |
T15 |
33 |
32 |
0 |
0 |
T49 |
1 |
0 |
0 |
0 |
T50 |
3 |
2 |
0 |
0 |
T67 |
6 |
5 |
0 |
0 |
T105 |
3 |
2 |
0 |
0 |
T111 |
1 |
0 |
0 |
0 |
T125 |
2 |
1 |
0 |
0 |
T167 |
1 |
0 |
0 |
0 |
T175 |
0 |
3 |
0 |
0 |
T176 |
6 |
5 |
0 |
0 |
T192 |
0 |
2 |
0 |
0 |
T193 |
0 |
5 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1725 |
712 |
0 |
0 |
T4 |
0 |
2 |
0 |
0 |
T5 |
0 |
5 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T30 |
3 |
2 |
0 |
0 |
T31 |
2 |
1 |
0 |
0 |
T32 |
0 |
1 |
0 |
0 |
T68 |
0 |
4 |
0 |
0 |
T89 |
1 |
0 |
0 |
0 |
T118 |
1 |
0 |
0 |
0 |
T130 |
1 |
0 |
0 |
0 |
T131 |
0 |
1 |
0 |
0 |
T132 |
1 |
0 |
0 |
0 |
T135 |
1 |
0 |
0 |
0 |
T163 |
1 |
0 |
0 |
0 |
T189 |
0 |
1 |
0 |
0 |
T199 |
0 |
1 |
0 |
0 |
T200 |
0 |
1 |
0 |
0 |
T202 |
1 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T7,T10,T11 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T10,T11,T12 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T7,T10,T11 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5410 |
5389 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
187 |
186 |
0 |
0 |
T11 |
287 |
286 |
0 |
0 |
T12 |
931 |
930 |
0 |
0 |
T27 |
0 |
2 |
0 |
0 |
T203 |
211 |
210 |
0 |
0 |
T204 |
19 |
18 |
0 |
0 |
T205 |
1026 |
1025 |
0 |
0 |
T206 |
559 |
558 |
0 |
0 |
T207 |
1026 |
1025 |
0 |
0 |
T208 |
1026 |
1025 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2440 |
2419 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T27 |
18 |
17 |
0 |
0 |
T28 |
14 |
13 |
0 |
0 |
T29 |
6 |
5 |
0 |
0 |
T33 |
17 |
16 |
0 |
0 |
T35 |
545 |
544 |
0 |
0 |
T194 |
0 |
17 |
0 |
0 |
T195 |
0 |
15 |
0 |
0 |
T205 |
576 |
575 |
0 |
0 |
T206 |
1 |
0 |
0 |
0 |
T207 |
576 |
575 |
0 |
0 |
T208 |
576 |
575 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T7,T9,T27 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T35,T205,T8 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T7,T9,T27 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
48 |
36 |
0 |
0 |
T27 |
3 |
2 |
0 |
0 |
T28 |
4 |
3 |
0 |
0 |
T29 |
2 |
1 |
0 |
0 |
T33 |
7 |
6 |
0 |
0 |
T194 |
6 |
5 |
0 |
0 |
T195 |
2 |
1 |
0 |
0 |
T196 |
7 |
6 |
0 |
0 |
T197 |
8 |
7 |
0 |
0 |
T198 |
6 |
5 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145 |
129 |
0 |
0 |
T27 |
17 |
16 |
0 |
0 |
T28 |
11 |
10 |
0 |
0 |
T29 |
4 |
3 |
0 |
0 |
T33 |
18 |
17 |
0 |
0 |
T194 |
14 |
13 |
0 |
0 |
T195 |
15 |
14 |
0 |
0 |
T196 |
14 |
13 |
0 |
0 |
T197 |
11 |
10 |
0 |
0 |
T198 |
17 |
16 |
0 |
0 |
T201 |
18 |
17 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T7,T10,T11 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T34,T35,T36 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T7,T10,T11 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5364 |
5343 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
172 |
171 |
0 |
0 |
T11 |
282 |
281 |
0 |
0 |
T12 |
918 |
917 |
0 |
0 |
T27 |
0 |
3 |
0 |
0 |
T203 |
201 |
200 |
0 |
0 |
T204 |
19 |
18 |
0 |
0 |
T205 |
1026 |
1025 |
0 |
0 |
T206 |
566 |
565 |
0 |
0 |
T207 |
1025 |
1024 |
0 |
0 |
T208 |
1025 |
1024 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
185 |
168 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T27 |
17 |
16 |
0 |
0 |
T28 |
9 |
8 |
0 |
0 |
T29 |
9 |
8 |
0 |
0 |
T33 |
18 |
17 |
0 |
0 |
T35 |
2 |
1 |
0 |
0 |
T36 |
1 |
0 |
0 |
0 |
T194 |
0 |
16 |
0 |
0 |
T195 |
0 |
28 |
0 |
0 |
T205 |
2 |
1 |
0 |
0 |
T207 |
2 |
1 |
0 |
0 |
T208 |
2 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T7,T9,T27 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T35,T205 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T7,T9,T27 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
52 |
40 |
0 |
0 |
T28 |
8 |
7 |
0 |
0 |
T29 |
9 |
8 |
0 |
0 |
T33 |
7 |
6 |
0 |
0 |
T194 |
3 |
2 |
0 |
0 |
T195 |
3 |
2 |
0 |
0 |
T196 |
5 |
4 |
0 |
0 |
T197 |
7 |
6 |
0 |
0 |
T198 |
6 |
5 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
157 |
140 |
0 |
0 |
T27 |
23 |
22 |
0 |
0 |
T28 |
8 |
7 |
0 |
0 |
T29 |
10 |
9 |
0 |
0 |
T33 |
11 |
10 |
0 |
0 |
T194 |
13 |
12 |
0 |
0 |
T195 |
22 |
21 |
0 |
0 |
T196 |
22 |
21 |
0 |
0 |
T197 |
6 |
5 |
0 |
0 |
T198 |
19 |
18 |
0 |
0 |
T201 |
16 |
15 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T7,T10,T11 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T205,T8,T207 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T7,T10,T11 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5758 |
5734 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T10 |
337 |
336 |
0 |
0 |
T11 |
415 |
414 |
0 |
0 |
T12 |
914 |
913 |
0 |
0 |
T27 |
0 |
2 |
0 |
0 |
T28 |
0 |
13 |
0 |
0 |
T59 |
1 |
0 |
0 |
0 |
T60 |
1 |
0 |
0 |
0 |
T203 |
340 |
339 |
0 |
0 |
T204 |
1 |
0 |
0 |
0 |
T205 |
1025 |
1024 |
0 |
0 |
T206 |
542 |
541 |
0 |
0 |
T207 |
0 |
1024 |
0 |
0 |
T208 |
0 |
1024 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
531 |
517 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T27 |
15 |
14 |
0 |
0 |
T28 |
9 |
8 |
0 |
0 |
T29 |
9 |
8 |
0 |
0 |
T33 |
23 |
22 |
0 |
0 |
T194 |
13 |
12 |
0 |
0 |
T195 |
24 |
23 |
0 |
0 |
T196 |
0 |
28 |
0 |
0 |
T205 |
117 |
116 |
0 |
0 |
T207 |
117 |
116 |
0 |
0 |
T208 |
117 |
116 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T7,T10,T11 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T205,T8 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T7,T10,T11 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
59 |
36 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T10 |
3 |
2 |
0 |
0 |
T11 |
3 |
2 |
0 |
0 |
T12 |
3 |
2 |
0 |
0 |
T27 |
0 |
2 |
0 |
0 |
T28 |
0 |
4 |
0 |
0 |
T29 |
0 |
3 |
0 |
0 |
T33 |
0 |
4 |
0 |
0 |
T59 |
1 |
0 |
0 |
0 |
T60 |
1 |
0 |
0 |
0 |
T194 |
0 |
1 |
0 |
0 |
T203 |
3 |
2 |
0 |
0 |
T205 |
1 |
0 |
0 |
0 |
T206 |
3 |
2 |
0 |
0 |
T207 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
148 |
132 |
0 |
0 |
T27 |
18 |
17 |
0 |
0 |
T28 |
7 |
6 |
0 |
0 |
T29 |
6 |
5 |
0 |
0 |
T33 |
18 |
17 |
0 |
0 |
T194 |
13 |
12 |
0 |
0 |
T195 |
19 |
18 |
0 |
0 |
T196 |
18 |
17 |
0 |
0 |
T197 |
9 |
8 |
0 |
0 |
T198 |
18 |
17 |
0 |
0 |
T201 |
16 |
15 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T10,T11,T12 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T35,T8,T27 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T10,T11,T12 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5716 |
5693 |
0 |
0 |
T10 |
322 |
321 |
0 |
0 |
T11 |
410 |
409 |
0 |
0 |
T12 |
900 |
899 |
0 |
0 |
T27 |
0 |
2 |
0 |
0 |
T28 |
0 |
16 |
0 |
0 |
T59 |
1 |
0 |
0 |
0 |
T60 |
1 |
0 |
0 |
0 |
T203 |
331 |
330 |
0 |
0 |
T204 |
1 |
0 |
0 |
0 |
T205 |
1026 |
1025 |
0 |
0 |
T206 |
549 |
548 |
0 |
0 |
T207 |
1025 |
1024 |
0 |
0 |
T208 |
0 |
1024 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
289 |
277 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T27 |
18 |
17 |
0 |
0 |
T28 |
5 |
4 |
0 |
0 |
T29 |
7 |
6 |
0 |
0 |
T33 |
29 |
28 |
0 |
0 |
T35 |
114 |
113 |
0 |
0 |
T194 |
12 |
11 |
0 |
0 |
T195 |
22 |
21 |
0 |
0 |
T196 |
27 |
26 |
0 |
0 |
T197 |
12 |
11 |
0 |
0 |
T198 |
0 |
28 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T10,T11,T12 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T35,T205 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T10,T11,T12 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
79 |
58 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
3 |
2 |
0 |
0 |
T11 |
3 |
2 |
0 |
0 |
T12 |
3 |
2 |
0 |
0 |
T28 |
0 |
7 |
0 |
0 |
T29 |
0 |
2 |
0 |
0 |
T33 |
0 |
5 |
0 |
0 |
T59 |
1 |
0 |
0 |
0 |
T60 |
1 |
0 |
0 |
0 |
T194 |
0 |
10 |
0 |
0 |
T195 |
0 |
1 |
0 |
0 |
T203 |
3 |
2 |
0 |
0 |
T205 |
1 |
0 |
0 |
0 |
T206 |
3 |
2 |
0 |
0 |
T207 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176 |
160 |
0 |
0 |
T27 |
19 |
18 |
0 |
0 |
T28 |
9 |
8 |
0 |
0 |
T29 |
7 |
6 |
0 |
0 |
T33 |
26 |
25 |
0 |
0 |
T194 |
14 |
13 |
0 |
0 |
T195 |
20 |
19 |
0 |
0 |
T196 |
26 |
25 |
0 |
0 |
T197 |
13 |
12 |
0 |
0 |
T198 |
23 |
22 |
0 |
0 |
T201 |
13 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T7,T74,T79 |
0 | 1 | Covered | T7,T34,T35 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T10,T11 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T7,T74,T79 |
1 | 1 | Covered | T7,T34,T35 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2518 |
2494 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T27 |
19 |
18 |
0 |
0 |
T28 |
25 |
24 |
0 |
0 |
T29 |
0 |
14 |
0 |
0 |
T33 |
0 |
21 |
0 |
0 |
T35 |
546 |
545 |
0 |
0 |
T36 |
1 |
0 |
0 |
0 |
T194 |
0 |
29 |
0 |
0 |
T195 |
0 |
22 |
0 |
0 |
T205 |
576 |
575 |
0 |
0 |
T207 |
576 |
575 |
0 |
0 |
T208 |
576 |
575 |
0 |
0 |
T209 |
1 |
0 |
0 |
0 |
T210 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5203 |
5172 |
0 |
0 |
T10 |
151 |
150 |
0 |
0 |
T11 |
252 |
251 |
0 |
0 |
T12 |
914 |
913 |
0 |
0 |
T27 |
0 |
4 |
0 |
0 |
T28 |
0 |
9 |
0 |
0 |
T34 |
1 |
0 |
0 |
0 |
T35 |
1 |
0 |
0 |
0 |
T57 |
1 |
0 |
0 |
0 |
T79 |
1 |
0 |
0 |
0 |
T203 |
173 |
172 |
0 |
0 |
T204 |
1 |
0 |
0 |
0 |
T205 |
0 |
1024 |
0 |
0 |
T206 |
0 |
541 |
0 |
0 |
T207 |
0 |
1024 |
0 |
0 |
T208 |
0 |
1024 |
0 |
0 |
T211 |
1 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T7,T74,T79 |
0 | 1 | Covered | T7,T34,T35 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T10,T11 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T7,T74,T79 |
1 | 1 | Covered | T7,T34,T35 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2515 |
2491 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T27 |
19 |
18 |
0 |
0 |
T28 |
23 |
22 |
0 |
0 |
T29 |
0 |
14 |
0 |
0 |
T33 |
0 |
23 |
0 |
0 |
T35 |
546 |
545 |
0 |
0 |
T36 |
1 |
0 |
0 |
0 |
T194 |
0 |
28 |
0 |
0 |
T195 |
0 |
21 |
0 |
0 |
T205 |
576 |
575 |
0 |
0 |
T207 |
576 |
575 |
0 |
0 |
T208 |
576 |
575 |
0 |
0 |
T209 |
1 |
0 |
0 |
0 |
T210 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5204 |
5173 |
0 |
0 |
T10 |
151 |
150 |
0 |
0 |
T11 |
252 |
251 |
0 |
0 |
T12 |
914 |
913 |
0 |
0 |
T27 |
0 |
5 |
0 |
0 |
T28 |
0 |
10 |
0 |
0 |
T34 |
1 |
0 |
0 |
0 |
T35 |
1 |
0 |
0 |
0 |
T57 |
1 |
0 |
0 |
0 |
T79 |
1 |
0 |
0 |
0 |
T203 |
173 |
172 |
0 |
0 |
T204 |
1 |
0 |
0 |
0 |
T205 |
0 |
1024 |
0 |
0 |
T206 |
0 |
541 |
0 |
0 |
T207 |
0 |
1024 |
0 |
0 |
T208 |
0 |
1024 |
0 |
0 |
T211 |
1 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T7,T74,T79 |
0 | 1 | Covered | T10,T11,T12 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T10,T11 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T7,T74,T79 |
1 | 1 | Covered | T10,T11,T12 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
231 |
202 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T27 |
12 |
11 |
0 |
0 |
T28 |
0 |
18 |
0 |
0 |
T29 |
0 |
20 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
T35 |
2 |
1 |
0 |
0 |
T36 |
1 |
0 |
0 |
0 |
T194 |
0 |
25 |
0 |
0 |
T195 |
0 |
24 |
0 |
0 |
T205 |
2 |
1 |
0 |
0 |
T206 |
1 |
0 |
0 |
0 |
T207 |
2 |
1 |
0 |
0 |
T208 |
2 |
1 |
0 |
0 |
T209 |
1 |
0 |
0 |
0 |
T210 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5188 |
5157 |
0 |
0 |
T10 |
136 |
135 |
0 |
0 |
T11 |
247 |
246 |
0 |
0 |
T12 |
900 |
899 |
0 |
0 |
T27 |
0 |
4 |
0 |
0 |
T28 |
0 |
16 |
0 |
0 |
T34 |
1 |
0 |
0 |
0 |
T35 |
1 |
0 |
0 |
0 |
T57 |
1 |
0 |
0 |
0 |
T79 |
1 |
0 |
0 |
0 |
T203 |
164 |
163 |
0 |
0 |
T204 |
1 |
0 |
0 |
0 |
T205 |
0 |
1025 |
0 |
0 |
T206 |
0 |
548 |
0 |
0 |
T207 |
0 |
1024 |
0 |
0 |
T208 |
0 |
1024 |
0 |
0 |
T211 |
1 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T7,T74,T79 |
0 | 1 | Covered | T10,T11,T12 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T10,T11 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T7,T74,T79 |
1 | 1 | Covered | T10,T11,T12 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
231 |
202 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T27 |
11 |
10 |
0 |
0 |
T28 |
0 |
19 |
0 |
0 |
T29 |
0 |
20 |
0 |
0 |
T33 |
0 |
13 |
0 |
0 |
T35 |
2 |
1 |
0 |
0 |
T36 |
1 |
0 |
0 |
0 |
T194 |
0 |
26 |
0 |
0 |
T195 |
0 |
27 |
0 |
0 |
T205 |
2 |
1 |
0 |
0 |
T206 |
1 |
0 |
0 |
0 |
T207 |
2 |
1 |
0 |
0 |
T208 |
2 |
1 |
0 |
0 |
T209 |
1 |
0 |
0 |
0 |
T210 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5187 |
5156 |
0 |
0 |
T10 |
136 |
135 |
0 |
0 |
T11 |
247 |
246 |
0 |
0 |
T12 |
900 |
899 |
0 |
0 |
T27 |
0 |
4 |
0 |
0 |
T28 |
0 |
15 |
0 |
0 |
T34 |
1 |
0 |
0 |
0 |
T35 |
1 |
0 |
0 |
0 |
T57 |
1 |
0 |
0 |
0 |
T79 |
1 |
0 |
0 |
0 |
T203 |
164 |
163 |
0 |
0 |
T204 |
1 |
0 |
0 |
0 |
T205 |
0 |
1025 |
0 |
0 |
T206 |
0 |
548 |
0 |
0 |
T207 |
0 |
1024 |
0 |
0 |
T208 |
0 |
1024 |
0 |
0 |
T211 |
1 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T7,T74,T79 |
0 | 1 | Covered | T205,T8,T207 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T10,T11 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T7,T74,T79 |
1 | 1 | Covered | T205,T8,T207 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
540 |
520 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T27 |
24 |
23 |
0 |
0 |
T28 |
26 |
25 |
0 |
0 |
T29 |
11 |
10 |
0 |
0 |
T33 |
14 |
13 |
0 |
0 |
T194 |
0 |
9 |
0 |
0 |
T195 |
0 |
16 |
0 |
0 |
T196 |
0 |
26 |
0 |
0 |
T205 |
117 |
116 |
0 |
0 |
T207 |
117 |
116 |
0 |
0 |
T208 |
117 |
116 |
0 |
0 |
T209 |
1 |
0 |
0 |
0 |
T210 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
30698 |
30661 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T10 |
370 |
369 |
0 |
0 |
T11 |
448 |
447 |
0 |
0 |
T12 |
930 |
929 |
0 |
0 |
T40 |
20 |
19 |
0 |
0 |
T41 |
20 |
19 |
0 |
0 |
T50 |
1418 |
1417 |
0 |
0 |
T203 |
374 |
373 |
0 |
0 |
T212 |
2349 |
2348 |
0 |
0 |
T213 |
2349 |
2348 |
0 |
0 |
T214 |
0 |
4722 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T7,T74,T79 |
0 | 1 | Covered | T205,T8,T207 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T10,T11 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T7,T74,T79 |
1 | 1 | Covered | T205,T8,T207 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
542 |
522 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T27 |
25 |
24 |
0 |
0 |
T28 |
25 |
24 |
0 |
0 |
T29 |
11 |
10 |
0 |
0 |
T33 |
15 |
14 |
0 |
0 |
T194 |
0 |
10 |
0 |
0 |
T195 |
0 |
14 |
0 |
0 |
T196 |
0 |
27 |
0 |
0 |
T205 |
117 |
116 |
0 |
0 |
T207 |
117 |
116 |
0 |
0 |
T208 |
117 |
116 |
0 |
0 |
T209 |
1 |
0 |
0 |
0 |
T210 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
30695 |
30658 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T10 |
370 |
369 |
0 |
0 |
T11 |
448 |
447 |
0 |
0 |
T12 |
930 |
929 |
0 |
0 |
T40 |
20 |
19 |
0 |
0 |
T41 |
20 |
19 |
0 |
0 |
T50 |
1418 |
1417 |
0 |
0 |
T203 |
374 |
373 |
0 |
0 |
T212 |
2349 |
2348 |
0 |
0 |
T213 |
2349 |
2348 |
0 |
0 |
T214 |
0 |
4722 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T19,T109,T7 |
0 | 1 | Covered | T19,T109,T10 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T10,T11 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T19,T109,T7 |
1 | 1 | Covered | T19,T109,T10 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
458 |
413 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
1 |
0 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T19 |
8 |
7 |
0 |
0 |
T20 |
2 |
1 |
0 |
0 |
T21 |
1 |
0 |
0 |
0 |
T35 |
0 |
109 |
0 |
0 |
T74 |
1 |
0 |
0 |
0 |
T79 |
1 |
0 |
0 |
0 |
T109 |
2 |
1 |
0 |
0 |
T205 |
0 |
1 |
0 |
0 |
T215 |
2 |
1 |
0 |
0 |
T216 |
0 |
7 |
0 |
0 |
T217 |
0 |
30 |
0 |
0 |
T218 |
0 |
1 |
0 |
0 |
T219 |
0 |
1 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
30681 |
30644 |
0 |
0 |
T7 |
2 |
1 |
0 |
0 |
T10 |
355 |
354 |
0 |
0 |
T11 |
443 |
442 |
0 |
0 |
T12 |
917 |
916 |
0 |
0 |
T40 |
20 |
19 |
0 |
0 |
T41 |
20 |
19 |
0 |
0 |
T50 |
1418 |
1417 |
0 |
0 |
T203 |
364 |
363 |
0 |
0 |
T212 |
2349 |
2348 |
0 |
0 |
T213 |
2349 |
2348 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T19,T109,T7 |
0 | 1 | Covered | T19,T109,T10 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T10,T11 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T19,T109,T7 |
1 | 1 | Covered | T19,T109,T10 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
458 |
413 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
1 |
0 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T19 |
8 |
7 |
0 |
0 |
T20 |
2 |
1 |
0 |
0 |
T21 |
1 |
0 |
0 |
0 |
T35 |
0 |
109 |
0 |
0 |
T74 |
1 |
0 |
0 |
0 |
T79 |
1 |
0 |
0 |
0 |
T109 |
2 |
1 |
0 |
0 |
T205 |
0 |
1 |
0 |
0 |
T215 |
2 |
1 |
0 |
0 |
T216 |
0 |
7 |
0 |
0 |
T217 |
0 |
30 |
0 |
0 |
T218 |
0 |
1 |
0 |
0 |
T219 |
0 |
1 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
30679 |
30642 |
0 |
0 |
T7 |
2 |
1 |
0 |
0 |
T10 |
355 |
354 |
0 |
0 |
T11 |
443 |
442 |
0 |
0 |
T12 |
917 |
916 |
0 |
0 |
T40 |
20 |
19 |
0 |
0 |
T41 |
20 |
19 |
0 |
0 |
T50 |
1418 |
1417 |
0 |
0 |
T203 |
364 |
363 |
0 |
0 |
T212 |
2349 |
2348 |
0 |
0 |
T213 |
2349 |
2348 |
0 |
0 |