Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T27,T28,T29 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T19,T109,T63 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T19,T20,T21 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T63,T104,T62 |
| 1 | 0 | Covered | T37,T38,T39 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T37,T38,T39 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T37,T38,T39 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T37,T38,T39 |
| 1 | 1 | Covered | T37,T38,T39 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T28,T29,T33 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T28,T29,T33 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T63,T37,T38 |
| 1 | Covered | T1,T2,T3 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T63,T37,T38 |
| 1 | 0 | Covered | T28,T29,T33 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T27,T28,T29 |
Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T27,T28,T29 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T28,T29,T33 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T63,T37,T38 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T27,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1023 |
1023 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1023 |
1023 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T47 |
1 |
1 |
0 |
0 |
| T51 |
1 |
1 |
0 |
0 |
| T66 |
1 |
1 |
0 |
0 |
| T88 |
1 |
1 |
0 |
0 |
| T89 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T27,T28,T29 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T13,T14,T15 |
| 0 | 1 | Covered | T13,T14,T15 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T15,T24,T25 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T33 |
| 1 | 1 | Covered | T15,T24,T7 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T27,T28,T29 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T27,T28,T29 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T15,T24,T7 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T15,T24,T7 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T15,T24,T7 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T27,T28,T29 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T27,T28,T29 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T27,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T15,T24,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T27,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1023 |
1023 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1023 |
1023 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T47 |
1 |
1 |
0 |
0 |
| T51 |
1 |
1 |
0 |
0 |
| T66 |
1 |
1 |
0 |
0 |
| T88 |
1 |
1 |
0 |
0 |
| T89 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T27,T28,T29 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T13,T14,T15 |
| 0 | 1 | Covered | T13,T14,T15 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T13,T14,T15 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T13,T14,T15 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T27,T28,T29 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T27,T28,T29 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T13,T14,T15 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T13,T14,T15 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T13,T14,T15 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T27,T28,T29 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T27,T28,T29 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T27,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T13,T14,T15 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T27,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1023 |
1023 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1023 |
1023 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T47 |
1 |
1 |
0 |
0 |
| T51 |
1 |
1 |
0 |
0 |
| T66 |
1 |
1 |
0 |
0 |
| T88 |
1 |
1 |
0 |
0 |
| T89 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T27,T28,T29 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T15,T153,T24 |
| 0 | 1 | Covered | T15,T153,T24 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T15,T153,T24 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T15,T153,T24 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T27,T28,T29 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T27,T28,T29 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T15,T153,T24 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T15,T153,T24 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T15,T153,T24 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T34,T35,T36 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T27,T28,T29 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T27,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T15,T153,T24 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T34,T35,T36 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1023 |
1023 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1023 |
1023 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T47 |
1 |
1 |
0 |
0 |
| T51 |
1 |
1 |
0 |
0 |
| T66 |
1 |
1 |
0 |
0 |
| T88 |
1 |
1 |
0 |
0 |
| T89 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T27,T28,T29 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T15,T24,T74 |
| 0 | 1 | Covered | T15,T24,T7 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T15,T24,T7 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T15,T24,T7 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T27,T28,T29 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T27,T28,T29 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T15,T24,T7 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T15,T24,T7 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T15,T24,T7 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T27,T28,T29 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T27,T28,T29 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T27,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T15,T24,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T27,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1023 |
1023 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1023 |
1023 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T47 |
1 |
1 |
0 |
0 |
| T51 |
1 |
1 |
0 |
0 |
| T66 |
1 |
1 |
0 |
0 |
| T88 |
1 |
1 |
0 |
0 |
| T89 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T27,T28,T29 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T126,T127,T15 |
| 0 | 1 | Covered | T126,T127,T15 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T15,T24,T25 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T15,T24,T25 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T27,T28,T29 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T27,T28,T29 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T15,T24,T25 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T15,T24,T25 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T15,T24,T25 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T27,T28,T29 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T27,T28,T29 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T27,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T15,T24,T25 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T27,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1023 |
1023 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1023 |
1023 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T47 |
1 |
1 |
0 |
0 |
| T51 |
1 |
1 |
0 |
0 |
| T66 |
1 |
1 |
0 |
0 |
| T88 |
1 |
1 |
0 |
0 |
| T89 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T27,T28,T29 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T126,T127,T15 |
| 0 | 1 | Covered | T126,T127,T15 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T126,T127,T15 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T33 |
| 1 | 1 | Covered | T126,T127,T15 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T27,T28,T29 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T27,T28,T29 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T126,T127,T15 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T126,T127,T15 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T126,T127,T15 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T27,T28,T29 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T27,T28,T29 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T27,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T126,T127,T15 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T27,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1023 |
1023 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1023 |
1023 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T47 |
1 |
1 |
0 |
0 |
| T51 |
1 |
1 |
0 |
0 |
| T66 |
1 |
1 |
0 |
0 |
| T88 |
1 |
1 |
0 |
0 |
| T89 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T27,T28,T29 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T15,T24,T7 |
| 0 | 1 | Covered | T15,T24,T7 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T15,T24,T25 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T15,T24,T25 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T27,T28,T29 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T27,T28,T29 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T15,T24,T25 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T15,T24,T25 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T15,T24,T25 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T27,T28,T29 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T27,T28,T29 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T27,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T15,T24,T25 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T27,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1023 |
1023 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1023 |
1023 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T47 |
1 |
1 |
0 |
0 |
| T51 |
1 |
1 |
0 |
0 |
| T66 |
1 |
1 |
0 |
0 |
| T88 |
1 |
1 |
0 |
0 |
| T89 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T27,T28,T29 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T15,T24,T7 |
| 0 | 1 | Covered | T15,T24,T223 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T15,T24,T25 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T15,T24,T7 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T27,T28,T29 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T27,T28,T29 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T15,T24,T7 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T15,T24,T7 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T15,T24,T7 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T40,T41,T42 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T27,T28,T29 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T27,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T15,T24,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T40,T41,T42 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1023 |
1023 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1023 |
1023 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T47 |
1 |
1 |
0 |
0 |
| T51 |
1 |
1 |
0 |
0 |
| T66 |
1 |
1 |
0 |
0 |
| T88 |
1 |
1 |
0 |
0 |
| T89 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T27,T28,T29 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T15,T24,T7 |
| 0 | 1 | Covered | T15,T24,T223 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T15,T24,T25 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T15,T24,T7 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T27,T28,T29 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T27,T28,T29 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T15,T24,T7 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T15,T24,T7 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T15,T24,T7 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T27,T28,T29 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T27,T28,T29 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T27,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T15,T24,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T27,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1023 |
1023 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1023 |
1023 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T47 |
1 |
1 |
0 |
0 |
| T51 |
1 |
1 |
0 |
0 |
| T66 |
1 |
1 |
0 |
0 |
| T88 |
1 |
1 |
0 |
0 |
| T89 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T27,T28,T29 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T7,T74,T79 |
| 0 | 1 | Covered | T7,T34,T35 |
| 1 | 0 | Covered | T27,T28,T33 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T10,T11,T12 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T35,T205,T8 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T27,T28,T29 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T27,T28,T29 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T35,T205,T8 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T35,T205,T8 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T35,T205,T8 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T34,T35,T36 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T27,T28,T29 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T27,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T35,T205,T8 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T34,T35,T36 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1023 |
1023 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1023 |
1023 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T47 |
1 |
1 |
0 |
0 |
| T51 |
1 |
1 |
0 |
0 |
| T66 |
1 |
1 |
0 |
0 |
| T88 |
1 |
1 |
0 |
0 |
| T89 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T27,T28,T29 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T7,T74,T79 |
| 0 | 1 | Covered | T10,T11,T12 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T34,T35,T36 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T7,T35,T205 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T27,T28,T29 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T27,T28,T29 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T7,T35,T205 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T35,T205 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T7,T35,T205 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T10,T11,T12 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T27,T28,T29 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T27,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T35,T205 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T10,T11,T12 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1023 |
1023 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1023 |
1023 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T47 |
1 |
1 |
0 |
0 |
| T51 |
1 |
1 |
0 |
0 |
| T66 |
1 |
1 |
0 |
0 |
| T88 |
1 |
1 |
0 |
0 |
| T89 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T27,T28,T29 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T7,T74,T79 |
| 0 | 1 | Covered | T205,T8,T207 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T205,T8,T207 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T7,T205,T8 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T27,T28,T29 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T27,T28,T29 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T7,T205,T8 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T205,T8 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T7,T205,T8 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T27,T28,T29 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T27,T28,T29 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T27,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T205,T8 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T27,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1023 |
1023 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1023 |
1023 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T47 |
1 |
1 |
0 |
0 |
| T51 |
1 |
1 |
0 |
0 |
| T66 |
1 |
1 |
0 |
0 |
| T88 |
1 |
1 |
0 |
0 |
| T89 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T27,T28,T29 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T19,T109,T7 |
| 0 | 1 | Covered | T19,T109,T10 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T35,T8,T27 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T7,T35,T205 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T27,T28,T29 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T27,T28,T29 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T7,T35,T205 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T35,T205 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T7,T35,T205 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T10,T11,T12 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T27,T28,T29 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T27,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T35,T205 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T10,T11,T12 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1023 |
1023 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1023 |
1023 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T47 |
1 |
1 |
0 |
0 |
| T51 |
1 |
1 |
0 |
0 |
| T66 |
1 |
1 |
0 |
0 |
| T88 |
1 |
1 |
0 |
0 |
| T89 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T27,T28,T29 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T224,T7,T74 |
| 0 | 1 | Covered | T224,T7,T225 |
| 1 | 0 | Covered | T28,T29,T33 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T205,T207,T208 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T205,T207,T208 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T27,T28,T29 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T27,T28,T29 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T205,T207,T208 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T205,T207,T208 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T205,T207,T208 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T34,T35,T36 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T27,T28,T29 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T27,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T205,T207,T208 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T34,T35,T36 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1023 |
1023 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1023 |
1023 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T47 |
1 |
1 |
0 |
0 |
| T51 |
1 |
1 |
0 |
0 |
| T66 |
1 |
1 |
0 |
0 |
| T88 |
1 |
1 |
0 |
0 |
| T89 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T27,T28,T29 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T224,T7,T74 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T27,T28,T29 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T27,T28,T29 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T34,T35,T36 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T27,T28,T29 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T27,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T34,T35,T36 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1023 |
1023 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1023 |
1023 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T47 |
1 |
1 |
0 |
0 |
| T51 |
1 |
1 |
0 |
0 |
| T66 |
1 |
1 |
0 |
0 |
| T88 |
1 |
1 |
0 |
0 |
| T89 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T27,T28,T29 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T15,T19,T109 |
| 0 | 1 | Covered | T15,T19,T109 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T15,T24,T25 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T15,T24,T25 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T27,T28,T29 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T27,T28,T29 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T15,T24,T25 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T15,T24,T25 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T15,T24,T25 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T34,T35,T36 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T27,T28,T29 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T27,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T15,T24,T25 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T34,T35,T36 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1023 |
1023 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1023 |
1023 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T47 |
1 |
1 |
0 |
0 |
| T51 |
1 |
1 |
0 |
0 |
| T66 |
1 |
1 |
0 |
0 |
| T88 |
1 |
1 |
0 |
0 |
| T89 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T27,T28,T29 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T15,T19,T16 |
| 0 | 1 | Covered | T15,T19,T16 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T29,T33 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T15,T19,T24 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T15,T19,T24 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T27,T28,T29 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T27,T28,T29 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T15,T19,T24 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T15,T19,T24 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T15,T19,T24 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T27,T28,T29 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T27,T28,T29 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T27,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T15,T19,T24 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T27,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1023 |
1023 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1023 |
1023 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T47 |
1 |
1 |
0 |
0 |
| T51 |
1 |
1 |
0 |
0 |
| T66 |
1 |
1 |
0 |
0 |
| T88 |
1 |
1 |
0 |
0 |
| T89 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T27,T28,T29 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T15,T19,T109 |
| 0 | 1 | Covered | T15,T19,T109 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T15,T24,T25 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T15,T24,T7 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T27,T28,T29 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T27,T28,T29 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T15,T24,T7 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T15,T24,T7 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T15,T24,T7 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T27,T28,T29 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T27,T28,T29 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T27,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T15,T24,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T27,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1023 |
1023 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1023 |
1023 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T47 |
1 |
1 |
0 |
0 |
| T51 |
1 |
1 |
0 |
0 |
| T66 |
1 |
1 |
0 |
0 |
| T88 |
1 |
1 |
0 |
0 |
| T89 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T27,T28,T29 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T202,T15,T226 |
| 0 | 1 | Covered | T202,T15,T226 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T202,T15,T19 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T202,T15,T19 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T27,T28,T29 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T27,T28,T29 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T202,T15,T19 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T202,T15,T19 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T202,T15,T19 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T27,T28,T29 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T27,T28,T29 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T27,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T202,T15,T19 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T27,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1023 |
1023 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1023 |
1023 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T47 |
1 |
1 |
0 |
0 |
| T51 |
1 |
1 |
0 |
0 |
| T66 |
1 |
1 |
0 |
0 |
| T88 |
1 |
1 |
0 |
0 |
| T89 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T27,T28,T29 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T202,T15,T226 |
| 0 | 1 | Covered | T202,T15,T226 |
| 1 | 0 | Covered | T27,T28,T33 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T202,T15,T153 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T202,T15,T226 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T27,T28,T29 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T27,T28,T29 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T202,T15,T226 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T202,T15,T226 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T202,T15,T226 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T27,T28,T29 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T27,T28,T29 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T27,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T202,T15,T226 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T27,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1023 |
1023 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1023 |
1023 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T47 |
1 |
1 |
0 |
0 |
| T51 |
1 |
1 |
0 |
0 |
| T66 |
1 |
1 |
0 |
0 |
| T88 |
1 |
1 |
0 |
0 |
| T89 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T27,T28,T29 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T202,T15,T227 |
| 0 | 1 | Covered | T15,T227,T153 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T15,T153,T24 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T202,T15,T227 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T27,T28,T29 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T27,T28,T29 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T202,T15,T227 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T202,T15,T227 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T202,T15,T227 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T27,T28,T29 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T27,T28,T29 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T27,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T202,T15,T227 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T27,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1023 |
1023 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1023 |
1023 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T47 |
1 |
1 |
0 |
0 |
| T51 |
1 |
1 |
0 |
0 |
| T66 |
1 |
1 |
0 |
0 |
| T88 |
1 |
1 |
0 |
0 |
| T89 |
1 |
1 |
0 |
0 |