Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T106,T183,T57
0	1	Covered	T106,T183,T308
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T106,T183,T308
1	Covered	T106,T183,T57

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T106,T183,T308
1	Covered	T106,T183,T57

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T106,T183,T308
1	1	Covered	T106,T183,T308

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T106,T183,T57
1	0	Covered	T106,T183,T308
1	1	Covered	T106,T183,T308

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T106,T183,T308

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T106,T183,T57
0	Covered	T106,T183,T308

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T106,T183,T57
0	Covered	T106,T183,T308

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1050421118	1034147286	0	0
CheckNGreaterZero_A	2046	2046	0	0
GntImpliesReady_A	1050421118	8372	0	0
GntImpliesValid_A	1050421118	8372	0	0
GrantKnown_A	1050421118	1034147286	0	0
IdxKnown_A	1050421118	1034147286	0	0
IndexIsCorrect_A	1050421118	8372	0	0
NoReadyValidNoGrant_A	1050421118	0	0	0
Priority_A	1050421118	8372	0	0
ReadyAndValidImplyGrant_A	1050421118	8372	0	0
ReqAndReadyImplyGrant_A	1050421118	8372	0	0
ReqImpliesValid_A	1050421118	8372	0	0
ValidKnown_A	1050421118	1034147286	0	0
gen_data_port_assertion.DataFlow_A	1050421118	8372	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050421118	1034147286	0	0
T1	222706	222604	0	0
T2	316984	316868	0	0
T3	368918	368716	0	0
T30	600320	599984	0	0
T46	272330	272318	0	0
T47	266688	266676	0	0
T51	81964	81854	0	0
T66	279434	279310	0	0
T88	132272	132162	0	0
T89	121350	121248	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2046	2046	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T30	2	2	0	0
T46	2	2	0	0
T47	2	2	0	0
T51	2	2	0	0
T66	2	2	0	0
T88	2	2	0	0
T89	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050421118	8372	0	0
T106	201186	2797	0	0
T107	251018	0	0	0
T108	477366	0	0	0
T109	202102	0	0	0
T110	259844	0	0	0
T111	386434	0	0	0
T112	172920	0	0	0
T113	456702	0	0	0
T183	0	2792	0	0
T308	0	2783	0	0
T391	436372	0	0	0
T407	215322	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050421118	8372	0	0
T106	201186	2797	0	0
T107	251018	0	0	0
T108	477366	0	0	0
T109	202102	0	0	0
T110	259844	0	0	0
T111	386434	0	0	0
T112	172920	0	0	0
T113	456702	0	0	0
T183	0	2792	0	0
T308	0	2783	0	0
T391	436372	0	0	0
T407	215322	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050421118	1034147286	0	0
T1	222706	222604	0	0
T2	316984	316868	0	0
T3	368918	368716	0	0
T30	600320	599984	0	0
T46	272330	272318	0	0
T47	266688	266676	0	0
T51	81964	81854	0	0
T66	279434	279310	0	0
T88	132272	132162	0	0
T89	121350	121248	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050421118	1034147286	0	0
T1	222706	222604	0	0
T2	316984	316868	0	0
T3	368918	368716	0	0
T30	600320	599984	0	0
T46	272330	272318	0	0
T47	266688	266676	0	0
T51	81964	81854	0	0
T66	279434	279310	0	0
T88	132272	132162	0	0
T89	121350	121248	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050421118	8372	0	0
T106	201186	2797	0	0
T107	251018	0	0	0
T108	477366	0	0	0
T109	202102	0	0	0
T110	259844	0	0	0
T111	386434	0	0	0
T112	172920	0	0	0
T113	456702	0	0	0
T183	0	2792	0	0
T308	0	2783	0	0
T391	436372	0	0	0
T407	215322	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050421118	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050421118	8372	0	0
T106	201186	2797	0	0
T107	251018	0	0	0
T108	477366	0	0	0
T109	202102	0	0	0
T110	259844	0	0	0
T111	386434	0	0	0
T112	172920	0	0	0
T113	456702	0	0	0
T183	0	2792	0	0
T308	0	2783	0	0
T391	436372	0	0	0
T407	215322	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050421118	8372	0	0
T106	201186	2797	0	0
T107	251018	0	0	0
T108	477366	0	0	0
T109	202102	0	0	0
T110	259844	0	0	0
T111	386434	0	0	0
T112	172920	0	0	0
T113	456702	0	0	0
T183	0	2792	0	0
T308	0	2783	0	0
T391	436372	0	0	0
T407	215322	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050421118	8372	0	0
T106	201186	2797	0	0
T107	251018	0	0	0
T108	477366	0	0	0
T109	202102	0	0	0
T110	259844	0	0	0
T111	386434	0	0	0
T112	172920	0	0	0
T113	456702	0	0	0
T183	0	2792	0	0
T308	0	2783	0	0
T391	436372	0	0	0
T407	215322	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050421118	8372	0	0
T106	201186	2797	0	0
T107	251018	0	0	0
T108	477366	0	0	0
T109	202102	0	0	0
T110	259844	0	0	0
T111	386434	0	0	0
T112	172920	0	0	0
T113	456702	0	0	0
T183	0	2792	0	0
T308	0	2783	0	0
T391	436372	0	0	0
T407	215322	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050421118	1034147286	0	0
T1	222706	222604	0	0
T2	316984	316868	0	0
T3	368918	368716	0	0
T30	600320	599984	0	0
T46	272330	272318	0	0
T47	266688	266676	0	0
T51	81964	81854	0	0
T66	279434	279310	0	0
T88	132272	132162	0	0
T89	121350	121248	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050421118	8372	0	0
T106	201186	2797	0	0
T107	251018	0	0	0
T108	477366	0	0	0
T109	202102	0	0	0
T110	259844	0	0	0
T111	386434	0	0	0
T112	172920	0	0	0
T113	456702	0	0	0
T183	0	2792	0	0
T308	0	2783	0	0
T391	436372	0	0	0
T407	215322	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T106,T183,T57
0	1	Covered	T106,T183,T308
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T106,T183,T308
1	Covered	T106,T183,T57

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T106,T183,T308
1	Covered	T106,T183,T57

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T106,T183,T308
1	1	Covered	T106,T183,T308

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T106,T183,T57
1	0	Covered	T106,T183,T308
1	1	Covered	T106,T183,T308

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T106,T183,T308

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T106,T183,T57
0	Covered	T106,T183,T308

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T106,T183,T57
0	Covered	T106,T183,T308

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	525210559	517073643	0	0
CheckNGreaterZero_A	1023	1023	0	0
GntImpliesReady_A	525210559	5184	0	0
GntImpliesValid_A	525210559	5184	0	0
GrantKnown_A	525210559	517073643	0	0
IdxKnown_A	525210559	517073643	0	0
IndexIsCorrect_A	525210559	5184	0	0
NoReadyValidNoGrant_A	525210559	0	0	0
Priority_A	525210559	5184	0	0
ReadyAndValidImplyGrant_A	525210559	5184	0	0
ReqAndReadyImplyGrant_A	525210559	5184	0	0
ReqImpliesValid_A	525210559	5184	0	0
ValidKnown_A	525210559	517073643	0	0
gen_data_port_assertion.DataFlow_A	525210559	5184	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	517073643	0	0
T1	111353	111302	0	0
T2	158492	158434	0	0
T3	184459	184358	0	0
T30	300160	299992	0	0
T46	136165	136159	0	0
T47	133344	133338	0	0
T51	40982	40927	0	0
T66	139717	139655	0	0
T88	66136	66081	0	0
T89	60675	60624	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1023	1023	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T30	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T51	1	1	0	0
T66	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	5184	0	0
T106	100593	1734	0	0
T107	125509	0	0	0
T108	238683	0	0	0
T109	101051	0	0	0
T110	129922	0	0	0
T111	193217	0	0	0
T112	86460	0	0	0
T113	228351	0	0	0
T183	0	1730	0	0
T308	0	1720	0	0
T391	218186	0	0	0
T407	107661	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	5184	0	0
T106	100593	1734	0	0
T107	125509	0	0	0
T108	238683	0	0	0
T109	101051	0	0	0
T110	129922	0	0	0
T111	193217	0	0	0
T112	86460	0	0	0
T113	228351	0	0	0
T183	0	1730	0	0
T308	0	1720	0	0
T391	218186	0	0	0
T407	107661	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	517073643	0	0
T1	111353	111302	0	0
T2	158492	158434	0	0
T3	184459	184358	0	0
T30	300160	299992	0	0
T46	136165	136159	0	0
T47	133344	133338	0	0
T51	40982	40927	0	0
T66	139717	139655	0	0
T88	66136	66081	0	0
T89	60675	60624	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	517073643	0	0
T1	111353	111302	0	0
T2	158492	158434	0	0
T3	184459	184358	0	0
T30	300160	299992	0	0
T46	136165	136159	0	0
T47	133344	133338	0	0
T51	40982	40927	0	0
T66	139717	139655	0	0
T88	66136	66081	0	0
T89	60675	60624	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	5184	0	0
T106	100593	1734	0	0
T107	125509	0	0	0
T108	238683	0	0	0
T109	101051	0	0	0
T110	129922	0	0	0
T111	193217	0	0	0
T112	86460	0	0	0
T113	228351	0	0	0
T183	0	1730	0	0
T308	0	1720	0	0
T391	218186	0	0	0
T407	107661	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	5184	0	0
T106	100593	1734	0	0
T107	125509	0	0	0
T108	238683	0	0	0
T109	101051	0	0	0
T110	129922	0	0	0
T111	193217	0	0	0
T112	86460	0	0	0
T113	228351	0	0	0
T183	0	1730	0	0
T308	0	1720	0	0
T391	218186	0	0	0
T407	107661	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	5184	0	0
T106	100593	1734	0	0
T107	125509	0	0	0
T108	238683	0	0	0
T109	101051	0	0	0
T110	129922	0	0	0
T111	193217	0	0	0
T112	86460	0	0	0
T113	228351	0	0	0
T183	0	1730	0	0
T308	0	1720	0	0
T391	218186	0	0	0
T407	107661	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	5184	0	0
T106	100593	1734	0	0
T107	125509	0	0	0
T108	238683	0	0	0
T109	101051	0	0	0
T110	129922	0	0	0
T111	193217	0	0	0
T112	86460	0	0	0
T113	228351	0	0	0
T183	0	1730	0	0
T308	0	1720	0	0
T391	218186	0	0	0
T407	107661	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	5184	0	0
T106	100593	1734	0	0
T107	125509	0	0	0
T108	238683	0	0	0
T109	101051	0	0	0
T110	129922	0	0	0
T111	193217	0	0	0
T112	86460	0	0	0
T113	228351	0	0	0
T183	0	1730	0	0
T308	0	1720	0	0
T391	218186	0	0	0
T407	107661	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	517073643	0	0
T1	111353	111302	0	0
T2	158492	158434	0	0
T3	184459	184358	0	0
T30	300160	299992	0	0
T46	136165	136159	0	0
T47	133344	133338	0	0
T51	40982	40927	0	0
T66	139717	139655	0	0
T88	66136	66081	0	0
T89	60675	60624	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	5184	0	0
T106	100593	1734	0	0
T107	125509	0	0	0
T108	238683	0	0	0
T109	101051	0	0	0
T110	129922	0	0	0
T111	193217	0	0	0
T112	86460	0	0	0
T113	228351	0	0	0
T183	0	1730	0	0
T308	0	1720	0	0
T391	218186	0	0	0
T407	107661	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T106,T183,T57
0	1	Covered	T106,T183,T308
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T106,T183,T308
1	Covered	T106,T183,T57

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T106,T183,T308
1	Covered	T106,T183,T57

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T106,T183,T308
1	1	Covered	T106,T183,T308

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T106,T183,T57
1	0	Covered	T106,T183,T308
1	1	Covered	T106,T183,T308

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T106,T183,T308

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T106,T183,T57
0	Covered	T106,T183,T308

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T106,T183,T57
0	Covered	T106,T183,T308

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	525210559	517073643	0	0
CheckNGreaterZero_A	1023	1023	0	0
GntImpliesReady_A	525210559	3188	0	0
GntImpliesValid_A	525210559	3188	0	0
GrantKnown_A	525210559	517073643	0	0
IdxKnown_A	525210559	517073643	0	0
IndexIsCorrect_A	525210559	3188	0	0
NoReadyValidNoGrant_A	525210559	0	0	0
Priority_A	525210559	3188	0	0
ReadyAndValidImplyGrant_A	525210559	3188	0	0
ReqAndReadyImplyGrant_A	525210559	3188	0	0
ReqImpliesValid_A	525210559	3188	0	0
ValidKnown_A	525210559	517073643	0	0
gen_data_port_assertion.DataFlow_A	525210559	3188	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	517073643	0	0
T1	111353	111302	0	0
T2	158492	158434	0	0
T3	184459	184358	0	0
T30	300160	299992	0	0
T46	136165	136159	0	0
T47	133344	133338	0	0
T51	40982	40927	0	0
T66	139717	139655	0	0
T88	66136	66081	0	0
T89	60675	60624	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1023	1023	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T30	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T51	1	1	0	0
T66	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	3188	0	0
T106	100593	1063	0	0
T107	125509	0	0	0
T108	238683	0	0	0
T109	101051	0	0	0
T110	129922	0	0	0
T111	193217	0	0	0
T112	86460	0	0	0
T113	228351	0	0	0
T183	0	1062	0	0
T308	0	1063	0	0
T391	218186	0	0	0
T407	107661	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	3188	0	0
T106	100593	1063	0	0
T107	125509	0	0	0
T108	238683	0	0	0
T109	101051	0	0	0
T110	129922	0	0	0
T111	193217	0	0	0
T112	86460	0	0	0
T113	228351	0	0	0
T183	0	1062	0	0
T308	0	1063	0	0
T391	218186	0	0	0
T407	107661	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	517073643	0	0
T1	111353	111302	0	0
T2	158492	158434	0	0
T3	184459	184358	0	0
T30	300160	299992	0	0
T46	136165	136159	0	0
T47	133344	133338	0	0
T51	40982	40927	0	0
T66	139717	139655	0	0
T88	66136	66081	0	0
T89	60675	60624	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	517073643	0	0
T1	111353	111302	0	0
T2	158492	158434	0	0
T3	184459	184358	0	0
T30	300160	299992	0	0
T46	136165	136159	0	0
T47	133344	133338	0	0
T51	40982	40927	0	0
T66	139717	139655	0	0
T88	66136	66081	0	0
T89	60675	60624	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	3188	0	0
T106	100593	1063	0	0
T107	125509	0	0	0
T108	238683	0	0	0
T109	101051	0	0	0
T110	129922	0	0	0
T111	193217	0	0	0
T112	86460	0	0	0
T113	228351	0	0	0
T183	0	1062	0	0
T308	0	1063	0	0
T391	218186	0	0	0
T407	107661	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	3188	0	0
T106	100593	1063	0	0
T107	125509	0	0	0
T108	238683	0	0	0
T109	101051	0	0	0
T110	129922	0	0	0
T111	193217	0	0	0
T112	86460	0	0	0
T113	228351	0	0	0
T183	0	1062	0	0
T308	0	1063	0	0
T391	218186	0	0	0
T407	107661	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	3188	0	0
T106	100593	1063	0	0
T107	125509	0	0	0
T108	238683	0	0	0
T109	101051	0	0	0
T110	129922	0	0	0
T111	193217	0	0	0
T112	86460	0	0	0
T113	228351	0	0	0
T183	0	1062	0	0
T308	0	1063	0	0
T391	218186	0	0	0
T407	107661	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	3188	0	0
T106	100593	1063	0	0
T107	125509	0	0	0
T108	238683	0	0	0
T109	101051	0	0	0
T110	129922	0	0	0
T111	193217	0	0	0
T112	86460	0	0	0
T113	228351	0	0	0
T183	0	1062	0	0
T308	0	1063	0	0
T391	218186	0	0	0
T407	107661	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	3188	0	0
T106	100593	1063	0	0
T107	125509	0	0	0
T108	238683	0	0	0
T109	101051	0	0	0
T110	129922	0	0	0
T111	193217	0	0	0
T112	86460	0	0	0
T113	228351	0	0	0
T183	0	1062	0	0
T308	0	1063	0	0
T391	218186	0	0	0
T407	107661	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	517073643	0	0
T1	111353	111302	0	0
T2	158492	158434	0	0
T3	184459	184358	0	0
T30	300160	299992	0	0
T46	136165	136159	0	0
T47	133344	133338	0	0
T51	40982	40927	0	0
T66	139717	139655	0	0
T88	66136	66081	0	0
T89	60675	60624	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525210559	3188	0	0
T106	100593	1063	0	0
T107	125509	0	0	0
T108	238683	0	0	0
T109	101051	0	0	0
T110	129922	0	0	0
T111	193217	0	0	0
T112	86460	0	0	0
T113	228351	0	0	0
T183	0	1062	0	0
T308	0	1063	0	0
T391	218186	0	0	0
T407	107661	0	0	0