Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1257477	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

36238060

1

T1

7230

T2

8235

T3

98221

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	26300363	1			T1	3210		T2	4055		T3	94014
values[0x0]	9936811	1			T1	4020		T2	4180		T3	4207
values[0x1]	1258363	1			T1	328		T2	549		T3	26339

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9102	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

37486435

1

T1

7558

T2

8784

T3

124560

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18733616	1			T1	3779		T2	4392		T3	62280
valid_sources[0x01]	18732482	1			T1	3779		T2	4392		T3	62280
valid_sources[0x02]	232	1			T89	4		T339	1		T44	46
valid_sources[0x03]	299	1			T90	2		T44	54		T46	61
valid_sources[0x04]	4863	1			T339	2		T44	28		T45	2291
valid_sources[0x05]	283	1			T14	1		T90	1		T44	35
valid_sources[0x06]	266	1			T44	30		T46	52		T235	33
valid_sources[0x07]	302	1			T44	50		T45	20		T46	54
valid_sources[0x08]	262	1			T90	1		T44	61		T46	61
valid_sources[0x09]	269	1			T89	7		T339	2		T44	48
valid_sources[0x0a]	377	1			T44	59		T46	42		T235	45
valid_sources[0x0b]	446	1			T44	35		T45	16		T46	70
valid_sources[0x0c]	313	1			T339	1		T44	49		T46	47
valid_sources[0x0d]	228	1			T14	8		T90	1		T44	42
valid_sources[0x0e]	237	1			T14	6		T90	1		T44	53
valid_sources[0x0f]	247	1			T90	1		T44	49		T46	38
valid_sources[0x10]	309	1			T44	45		T45	16		T46	43
valid_sources[0x11]	259	1			T90	1		T44	78		T46	47
valid_sources[0x12]	271	1			T44	64		T45	16		T46	53
valid_sources[0x13]	306	1			T90	2		T44	51		T46	52
valid_sources[0x14]	279	1			T339	1		T44	37		T46	47
valid_sources[0x15]	235	1			T339	2		T44	52		T46	48
valid_sources[0x16]	274	1			T90	4		T44	60		T46	46
valid_sources[0x17]	237	1			T339	1		T44	58		T46	61
valid_sources[0x18]	330	1			T63	39		T44	75		T46	43
valid_sources[0x19]	264	1			T90	1		T44	51		T46	49
valid_sources[0x1a]	274	1			T339	1		T44	64		T46	62
valid_sources[0x1b]	307	1			T14	1		T90	3		T44	71
valid_sources[0x1c]	274	1			T44	76		T46	43		T235	40
valid_sources[0x1d]	253	1			T44	45		T46	63		T235	52
valid_sources[0x1e]	265	1			T339	1		T44	60		T46	67
valid_sources[0x1f]	309	1			T44	71		T45	40		T46	38
valid_sources[0x20]	256	1			T14	1		T44	64		T46	39

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26300363

1

T1

3210

T2

4055

T3

94014

values[0x0]

all_enables

biggest_size

9932164

1

T1

4020

T2

4180

T3

4207

values[0x1]

all_enables

biggest_size

5533

1

T14

17

T89

19

T90

25