Unified Coverage Report :: Module :: tlul_rsp_intg_gen

Module : tlul_rsp_intg_gen

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	83.33					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_rsp_intg_gen	83.33	66.67					100.00
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.u_rsp_intg_gen	83.33	66.67					100.00
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.u_rsp_intg_gen	83.33	66.67					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.u_rsp_intg_gen	83.33	66.67					100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_rsp_intg_gen	100.00	100.00					100.00
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_rsp_intg_gen	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_rsp_intg_gen	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_rsp_intg_gen	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_sim_win_rsp.u_intg_gen	100.00	100.00					100.00

Line Coverage for Module : tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_rsp_intg_gen

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_rsp_intg_gen

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_rv_plic.u_reg.u_rsp_intg_gen

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_rsp_intg_gen

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_rv_core_ibex.u_sim_win_rsp.u_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	25	1	1	100.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
47	1	1
48	1	1
49	1	1
53	1	1

---

Line Coverage for Module : tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 )
Line Coverage for Module self-instances :

SCORE	LINE
83.33	66.67

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_rsp_intg_gen

SCORE	LINE
83.33	66.67

tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.u_rsp_intg_gen

SCORE	LINE
83.33	66.67

tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.u_rsp_intg_gen

SCORE	LINE
83.33	66.67

tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.u_rsp_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		6	4	66.67
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	43	1	0	0.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	0	1
43	0	1
47	1	1
48	1	1
49	1	1
53	1	1

---

Assert Coverage for Module : tlul_rsp_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	9207	9207	0	0
PayLoadWidthCheck	9207	9207	0	0

DataWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9207	9207	0	0
T1	9	9	0	0
T2	9	9	0	0
T3	9	9	0	0
T4	9	9	0	0
T5	9	9	0	0
T6	9	9	0	0
T22	9	9	0	0
T59	9	9	0	0
T62	9	9	0	0
T93	9	9	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	9207	9207	0	0
T1	9	9	0	0
T2	9	9	0	0
T3	9	9	0	0
T4	9	9	0	0
T5	9	9	0	0
T6	9	9	0	0
T22	9	9	0	0
T59	9	9	0	0
T62	9	9	0	0
T93	9	9	0	0