Line Coverage for Module :
prim_lc_or_hardened
| Line No. | Total | Covered | Percent |
TOTAL | | 5 | 5 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_or_hardened_0.1/rtl/prim_lc_or_hardened.sv' or '../src/lowrisc_prim_lc_or_hardened_0.1/rtl/prim_lc_or_hardened.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
4 |
4 |
60 |
1 |
1 |
Cond Coverage for Module :
prim_lc_or_hardened
| Total | Covered | Percent |
Conditions | 28 | 28 | 100.00 |
Logical | 28 | 28 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 56
EXPRESSION ((lc_en_a_copies[0] == ActVal) || (lc_en_b_copies[0] == ActVal))
--------------1-------------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 56
SUB-EXPRESSION (lc_en_a_copies[0] == ActVal)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 56
SUB-EXPRESSION (lc_en_b_copies[0] == ActVal)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 56
EXPRESSION ((lc_en_a_copies[1] == ActVal) || (lc_en_b_copies[1] == ActVal))
--------------1-------------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 56
SUB-EXPRESSION (lc_en_a_copies[1] == ActVal)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 56
SUB-EXPRESSION (lc_en_b_copies[1] == ActVal)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 56
EXPRESSION ((lc_en_a_copies[2] == ActVal) || (lc_en_b_copies[2] == ActVal))
--------------1-------------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 56
SUB-EXPRESSION (lc_en_a_copies[2] == ActVal)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 56
SUB-EXPRESSION (lc_en_b_copies[2] == ActVal)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 56
EXPRESSION ((lc_en_a_copies[3] == ActVal) || (lc_en_b_copies[3] == ActVal))
--------------1-------------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 56
SUB-EXPRESSION (lc_en_a_copies[3] == ActVal)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 56
SUB-EXPRESSION (lc_en_b_copies[3] == ActVal)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_lc_or_hardened
Assertion Details
FunctionCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
136283482 |
135597607 |
0 |
0 |
T1 |
38611 |
37918 |
0 |
0 |
T2 |
33361 |
32554 |
0 |
0 |
T3 |
271998 |
271550 |
0 |
0 |
T4 |
57689 |
57351 |
0 |
0 |
T5 |
304509 |
303621 |
0 |
0 |
T6 |
104149 |
104005 |
0 |
0 |
T22 |
94836 |
94224 |
0 |
0 |
T59 |
226278 |
225934 |
0 |
0 |
T62 |
50502 |
49830 |
0 |
0 |
T93 |
272920 |
272031 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
136283482 |
135597607 |
0 |
0 |
T1 |
38611 |
37918 |
0 |
0 |
T2 |
33361 |
32554 |
0 |
0 |
T3 |
271998 |
271550 |
0 |
0 |
T4 |
57689 |
57351 |
0 |
0 |
T5 |
304509 |
303621 |
0 |
0 |
T6 |
104149 |
104005 |
0 |
0 |
T22 |
94836 |
94224 |
0 |
0 |
T59 |
226278 |
225934 |
0 |
0 |
T62 |
50502 |
49830 |
0 |
0 |
T93 |
272920 |
272031 |
0 |
0 |