Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	541565630	62019597	0	0
DepthKnown_A	541565630	541458798	0	0
RvalidKnown_A	541565630	541458798	0	0
WreadyKnown_A	541565630	541458798	0	0
gen_passthru_fifo.paramCheckPass	1023	1023	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	62019597	0	0
T1	140293	19233	0	0
T2	97883	10916	0	0
T3	112985	97175	0	0
T4	235876	30973	0	0
T5	126352	136443	0	0
T6	431859	314382	0	0
T22	391042	83388	0	0
T59	939792	114106	0	0
T62	201313	26254	0	0
T93	108984	94174	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	541458798	0	0
T1	140293	140238	0	0
T2	97883	97832	0	0
T3	112985	112980	0	0
T4	235876	235763	0	0
T5	126352	126340	0	0
T6	431859	431825	0	0
T22	391042	390991	0	0
T59	939792	939734	0	0
T62	201313	201258	0	0
T93	108984	108978	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	541458798	0	0
T1	140293	140238	0	0
T2	97883	97832	0	0
T3	112985	112980	0	0
T4	235876	235763	0	0
T5	126352	126340	0	0
T6	431859	431825	0	0
T22	391042	390991	0	0
T59	939792	939734	0	0
T62	201313	201258	0	0
T93	108984	108978	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	541458798	0	0
T1	140293	140238	0	0
T2	97883	97832	0	0
T3	112985	112980	0	0
T4	235876	235763	0	0
T5	126352	126340	0	0
T6	431859	431825	0	0
T22	391042	390991	0	0
T59	939792	939734	0	0
T62	201313	201258	0	0
T93	108984	108978	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1023	1023	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T22	1	1	0	0
T59	1	1	0	0
T62	1	1	0	0
T93	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	541565630	48225390	0	0
DepthKnown_A	541565630	541458798	0	0
RvalidKnown_A	541565630	541458798	0	0
WreadyKnown_A	541565630	541458798	0	0
gen_passthru_fifo.paramCheckPass	1023	1023	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	48225390	0	0
T1	140293	13937	0	0
T2	97883	8638	0	0
T3	112985	93275	0	0
T4	235876	21366	0	0
T5	126352	118645	0	0
T6	431859	157677	0	0
T22	391042	56122	0	0
T59	939792	95322	0	0
T62	201313	23562	0	0
T93	108984	90032	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	541458798	0	0
T1	140293	140238	0	0
T2	97883	97832	0	0
T3	112985	112980	0	0
T4	235876	235763	0	0
T5	126352	126340	0	0
T6	431859	431825	0	0
T22	391042	390991	0	0
T59	939792	939734	0	0
T62	201313	201258	0	0
T93	108984	108978	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	541458798	0	0
T1	140293	140238	0	0
T2	97883	97832	0	0
T3	112985	112980	0	0
T4	235876	235763	0	0
T5	126352	126340	0	0
T6	431859	431825	0	0
T22	391042	390991	0	0
T59	939792	939734	0	0
T62	201313	201258	0	0
T93	108984	108978	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	541458798	0	0
T1	140293	140238	0	0
T2	97883	97832	0	0
T3	112985	112980	0	0
T4	235876	235763	0	0
T5	126352	126340	0	0
T6	431859	431825	0	0
T22	391042	390991	0	0
T59	939792	939734	0	0
T62	201313	201258	0	0
T93	108984	108978	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1023	1023	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T22	1	1	0	0
T59	1	1	0	0
T62	1	1	0	0
T93	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	541565630	44510725	0	0
DepthKnown_A	541565630	541458798	0	0
RvalidKnown_A	541565630	541458798	0	0
WreadyKnown_A	541565630	541458798	0	0
gen_passthru_fifo.paramCheckPass	1023	1023	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	44510725	0	0
T1	140293	7842	0	0
T2	97883	9143	0	0
T3	112985	124765	0	0
T4	235876	15157	0	0
T5	126352	191905	0	0
T6	431859	21985	0	0
T22	391042	99558	0	0
T59	939792	153640	0	0
T62	201313	5991	0	0
T93	108984	120031	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	541458798	0	0
T1	140293	140238	0	0
T2	97883	97832	0	0
T3	112985	112980	0	0
T4	235876	235763	0	0
T5	126352	126340	0	0
T6	431859	431825	0	0
T22	391042	390991	0	0
T59	939792	939734	0	0
T62	201313	201258	0	0
T93	108984	108978	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	541458798	0	0
T1	140293	140238	0	0
T2	97883	97832	0	0
T3	112985	112980	0	0
T4	235876	235763	0	0
T5	126352	126340	0	0
T6	431859	431825	0	0
T22	391042	390991	0	0
T59	939792	939734	0	0
T62	201313	201258	0	0
T93	108984	108978	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	541458798	0	0
T1	140293	140238	0	0
T2	97883	97832	0	0
T3	112985	112980	0	0
T4	235876	235763	0	0
T5	126352	126340	0	0
T6	431859	431825	0	0
T22	391042	390991	0	0
T59	939792	939734	0	0
T62	201313	201258	0	0
T93	108984	108978	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1023	1023	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T22	1	1	0	0
T59	1	1	0	0
T62	1	1	0	0
T93	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	541565630	37562968	0	0
DepthKnown_A	541565630	541458798	0	0
RvalidKnown_A	541565630	541458798	0	0
WreadyKnown_A	541565630	541458798	0	0
gen_passthru_fifo.paramCheckPass	1023	1023	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	37562968	0	0
T1	140293	7558	0	0
T2	97883	8784	0	0
T3	112985	124560	0	0
T4	235876	14767	0	0
T5	126352	110840	0	0
T6	431859	20796	0	0
T22	391042	99311	0	0
T59	939792	86461	0	0
T62	201313	5782	0	0
T93	108984	119814	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	541458798	0	0
T1	140293	140238	0	0
T2	97883	97832	0	0
T3	112985	112980	0	0
T4	235876	235763	0	0
T5	126352	126340	0	0
T6	431859	431825	0	0
T22	391042	390991	0	0
T59	939792	939734	0	0
T62	201313	201258	0	0
T93	108984	108978	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	541458798	0	0
T1	140293	140238	0	0
T2	97883	97832	0	0
T3	112985	112980	0	0
T4	235876	235763	0	0
T5	126352	126340	0	0
T6	431859	431825	0	0
T22	391042	390991	0	0
T59	939792	939734	0	0
T62	201313	201258	0	0
T93	108984	108978	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	541458798	0	0
T1	140293	140238	0	0
T2	97883	97832	0	0
T3	112985	112980	0	0
T4	235876	235763	0	0
T5	126352	126340	0	0
T6	431859	431825	0	0
T22	391042	390991	0	0
T59	939792	939734	0	0
T62	201313	201258	0	0
T93	108984	108978	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1023	1023	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T22	1	1	0	0
T59	1	1	0	0
T62	1	1	0	0
T93	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	541565630	64514	0	0
DepthKnown_A	541565630	541458798	0	0
RvalidKnown_A	541565630	541458798	0	0
WreadyKnown_A	541565630	541458798	0	0
gen_passthru_fifo.paramCheckPass	1023	1023	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	64514	0	0
T1	140293	26	0	0
T2	97883	14	0	0
T3	112985	53	0	0
T4	235876	151	0	0
T5	126352	27	0	0
T6	431859	91	0	0
T22	391042	18	0	0
T59	939792	34	0	0
T62	201313	78	0	0
T93	108984	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	541458798	0	0
T1	140293	140238	0	0
T2	97883	97832	0	0
T3	112985	112980	0	0
T4	235876	235763	0	0
T5	126352	126340	0	0
T6	431859	431825	0	0
T22	391042	390991	0	0
T59	939792	939734	0	0
T62	201313	201258	0	0
T93	108984	108978	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	541458798	0	0
T1	140293	140238	0	0
T2	97883	97832	0	0
T3	112985	112980	0	0
T4	235876	235763	0	0
T5	126352	126340	0	0
T6	431859	431825	0	0
T22	391042	390991	0	0
T59	939792	939734	0	0
T62	201313	201258	0	0
T93	108984	108978	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	541458798	0	0
T1	140293	140238	0	0
T2	97883	97832	0	0
T3	112985	112980	0	0
T4	235876	235763	0	0
T5	126352	126340	0	0
T6	431859	431825	0	0
T22	391042	390991	0	0
T59	939792	939734	0	0
T62	201313	201258	0	0
T93	108984	108978	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1023	1023	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T22	1	1	0	0
T59	1	1	0	0
T62	1	1	0	0
T93	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	541565630	64514	0	0
DepthKnown_A	541565630	541458798	0	0
RvalidKnown_A	541565630	541458798	0	0
WreadyKnown_A	541565630	541458798	0	0
gen_passthru_fifo.paramCheckPass	1023	1023	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	64514	0	0
T1	140293	26	0	0
T2	97883	14	0	0
T3	112985	53	0	0
T4	235876	151	0	0
T5	126352	27	0	0
T6	431859	91	0	0
T22	391042	18	0	0
T59	939792	34	0	0
T62	201313	78	0	0
T93	108984	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	541458798	0	0
T1	140293	140238	0	0
T2	97883	97832	0	0
T3	112985	112980	0	0
T4	235876	235763	0	0
T5	126352	126340	0	0
T6	431859	431825	0	0
T22	391042	390991	0	0
T59	939792	939734	0	0
T62	201313	201258	0	0
T93	108984	108978	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	541458798	0	0
T1	140293	140238	0	0
T2	97883	97832	0	0
T3	112985	112980	0	0
T4	235876	235763	0	0
T5	126352	126340	0	0
T6	431859	431825	0	0
T22	391042	390991	0	0
T59	939792	939734	0	0
T62	201313	201258	0	0
T93	108984	108978	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	541458798	0	0
T1	140293	140238	0	0
T2	97883	97832	0	0
T3	112985	112980	0	0
T4	235876	235763	0	0
T5	126352	126340	0	0
T6	431859	431825	0	0
T22	391042	390991	0	0
T59	939792	939734	0	0
T62	201313	201258	0	0
T93	108984	108978	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1023	1023	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T22	1	1	0	0
T59	1	1	0	0
T62	1	1	0	0
T93	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	541565630	51179	0	0
DepthKnown_A	541565630	541458798	0	0
RvalidKnown_A	541565630	541458798	0	0
WreadyKnown_A	541565630	541458798	0	0
gen_passthru_fifo.paramCheckPass	1023	1023	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	51179	0	0
T1	140293	23	0	0
T2	97883	13	0	0
T3	112985	52	0	0
T4	235876	95	0	0
T5	126352	0	0	0
T6	431859	86	0	0
T8	0	72	0	0
T22	391042	15	0	0
T59	939792	5	0	0
T62	201313	77	0	0
T93	108984	55	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	541458798	0	0
T1	140293	140238	0	0
T2	97883	97832	0	0
T3	112985	112980	0	0
T4	235876	235763	0	0
T5	126352	126340	0	0
T6	431859	431825	0	0
T22	391042	390991	0	0
T59	939792	939734	0	0
T62	201313	201258	0	0
T93	108984	108978	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	541458798	0	0
T1	140293	140238	0	0
T2	97883	97832	0	0
T3	112985	112980	0	0
T4	235876	235763	0	0
T5	126352	126340	0	0
T6	431859	431825	0	0
T22	391042	390991	0	0
T59	939792	939734	0	0
T62	201313	201258	0	0
T93	108984	108978	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	541458798	0	0
T1	140293	140238	0	0
T2	97883	97832	0	0
T3	112985	112980	0	0
T4	235876	235763	0	0
T5	126352	126340	0	0
T6	431859	431825	0	0
T22	391042	390991	0	0
T59	939792	939734	0	0
T62	201313	201258	0	0
T93	108984	108978	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1023	1023	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T22	1	1	0	0
T59	1	1	0	0
T62	1	1	0	0
T93	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	541565630	51179	0	0
DepthKnown_A	541565630	541458798	0	0
RvalidKnown_A	541565630	541458798	0	0
WreadyKnown_A	541565630	541458798	0	0
gen_passthru_fifo.paramCheckPass	1023	1023	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	51179	0	0
T1	140293	23	0	0
T2	97883	13	0	0
T3	112985	52	0	0
T4	235876	95	0	0
T5	126352	0	0	0
T6	431859	86	0	0
T8	0	72	0	0
T22	391042	15	0	0
T59	939792	5	0	0
T62	201313	77	0	0
T93	108984	55	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	541458798	0	0
T1	140293	140238	0	0
T2	97883	97832	0	0
T3	112985	112980	0	0
T4	235876	235763	0	0
T5	126352	126340	0	0
T6	431859	431825	0	0
T22	391042	390991	0	0
T59	939792	939734	0	0
T62	201313	201258	0	0
T93	108984	108978	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	541458798	0	0
T1	140293	140238	0	0
T2	97883	97832	0	0
T3	112985	112980	0	0
T4	235876	235763	0	0
T5	126352	126340	0	0
T6	431859	431825	0	0
T22	391042	390991	0	0
T59	939792	939734	0	0
T62	201313	201258	0	0
T93	108984	108978	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	541458798	0	0
T1	140293	140238	0	0
T2	97883	97832	0	0
T3	112985	112980	0	0
T4	235876	235763	0	0
T5	126352	126340	0	0
T6	431859	431825	0	0
T22	391042	390991	0	0
T59	939792	939734	0	0
T62	201313	201258	0	0
T93	108984	108978	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1023	1023	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T22	1	1	0	0
T59	1	1	0	0
T62	1	1	0	0
T93	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	541565630	13335	0	0
DepthKnown_A	541565630	541458798	0	0
RvalidKnown_A	541565630	541458798	0	0
WreadyKnown_A	541565630	541458798	0	0
gen_passthru_fifo.paramCheckPass	1023	1023	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	13335	0	0
T1	140293	3	0	0
T2	97883	1	0	0
T3	112985	1	0	0
T4	235876	56	0	0
T5	126352	27	0	0
T6	431859	5	0	0
T22	391042	3	0	0
T59	939792	29	0	0
T62	201313	1	0	0
T93	108984	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	541458798	0	0
T1	140293	140238	0	0
T2	97883	97832	0	0
T3	112985	112980	0	0
T4	235876	235763	0	0
T5	126352	126340	0	0
T6	431859	431825	0	0
T22	391042	390991	0	0
T59	939792	939734	0	0
T62	201313	201258	0	0
T93	108984	108978	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	541458798	0	0
T1	140293	140238	0	0
T2	97883	97832	0	0
T3	112985	112980	0	0
T4	235876	235763	0	0
T5	126352	126340	0	0
T6	431859	431825	0	0
T22	391042	390991	0	0
T59	939792	939734	0	0
T62	201313	201258	0	0
T93	108984	108978	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	541458798	0	0
T1	140293	140238	0	0
T2	97883	97832	0	0
T3	112985	112980	0	0
T4	235876	235763	0	0
T5	126352	126340	0	0
T6	431859	431825	0	0
T22	391042	390991	0	0
T59	939792	939734	0	0
T62	201313	201258	0	0
T93	108984	108978	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1023	1023	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T22	1	1	0	0
T59	1	1	0	0
T62	1	1	0	0
T93	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	541565630	13335	0	0
DepthKnown_A	541565630	541458798	0	0
RvalidKnown_A	541565630	541458798	0	0
WreadyKnown_A	541565630	541458798	0	0
gen_passthru_fifo.paramCheckPass	1023	1023	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	13335	0	0
T1	140293	3	0	0
T2	97883	1	0	0
T3	112985	1	0	0
T4	235876	56	0	0
T5	126352	27	0	0
T6	431859	5	0	0
T22	391042	3	0	0
T59	939792	29	0	0
T62	201313	1	0	0
T93	108984	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	541458798	0	0
T1	140293	140238	0	0
T2	97883	97832	0	0
T3	112985	112980	0	0
T4	235876	235763	0	0
T5	126352	126340	0	0
T6	431859	431825	0	0
T22	391042	390991	0	0
T59	939792	939734	0	0
T62	201313	201258	0	0
T93	108984	108978	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	541458798	0	0
T1	140293	140238	0	0
T2	97883	97832	0	0
T3	112985	112980	0	0
T4	235876	235763	0	0
T5	126352	126340	0	0
T6	431859	431825	0	0
T22	391042	390991	0	0
T59	939792	939734	0	0
T62	201313	201258	0	0
T93	108984	108978	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541565630	541458798	0	0
T1	140293	140238	0	0
T2	97883	97832	0	0
T3	112985	112980	0	0
T4	235876	235763	0	0
T5	126352	126340	0	0
T6	431859	431825	0	0
T22	391042	390991	0	0
T59	939792	939734	0	0
T62	201313	201258	0	0
T93	108984	108978	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1023	1023	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T22	1	1	0	0
T59	1	1	0	0
T62	1	1	0	0
T93	1	1	0	0