Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_plic_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.38 100.00 70.00 99.52 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_plic.u_reg 92.38 100.00 70.00 99.52 100.00

Line Coverage for Module : rv_plic_reg_top
Line No.TotalCoveredPercent
TOTAL15601560100.00
ALWAYS6844100.00
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CONT_ASSIGN1659311100.00
CONT_ASSIGN1662711100.00
CONT_ASSIGN1664111100.00
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WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
69 1 1
70 1 1
71 1 1
MISSING_ELSE
77 1 1
89 1 1
90 1 1
118 1 1
119 1 1
16579 1 1
16593 1 1
16627 1 1
16641 1 1
16647 1 1
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16650 1 1
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19314 1 1
19315 1 1
19316 1 1
19317 1 1
19318 1 1
19319 1 1
19320 1 1
19321 1 1
19322 1 1
19323 1 1
19324 1 1
19325 1 1
19326 1 1
19327 1 1
19328 1 1
19329 1 1
19330 1 1
19331 1 1
19332 1 1
19333 1 1
19334 1 1
19335 1 1
19336 1 1
19337 1 1
19338 1 1
19339 1 1
19340 1 1
19341 1 1
19342 1 1
19343 1 1
19347 1 1
19348 1 1
19349 1 1
19350 1 1
19351 1 1
19352 1 1
19353 1 1
19354 1 1
19355 1 1
19356 1 1
19357 1 1
19358 1 1
19359 1 1
19360 1 1
19361 1 1
19362 1 1
19363 1 1
19364 1 1
19365 1 1
19366 1 1
19367 1 1
19368 1 1
19369 1 1
19370 1 1
19371 1 1
19372 1 1
19376 1 1
19380 1 1
19384 1 1
19388 1 1
19402 unreachable
19410 1 1
19411 1 1


Cond Coverage for Module : rv_plic_reg_top
TotalCoveredPercent
Conditions2023141670.00
Logical2023141670.00
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
58-1683398.45
16834-1685644.75
16856-1723670.36
17239-1800875.00

Branch Coverage for Module : rv_plic_reg_top
Line No.TotalCoveredPercent
Branches 208 207 99.52
TERNARY 16852 2 2 100.00
IF 68 3 3 100.00
CASE 18222 203 202 99.51

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 16852 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T22
0 Covered T1,T2,T3


LineNo. Expression -1-: 68 if ((!rst_ni)) -2-: 70 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T385,T386,T387
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 18222 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T1,T3,T22
addr_hit[1] Covered T295,T139,T117
addr_hit[2] Covered T295,T139,T117
addr_hit[3] Covered T295,T139,T117
addr_hit[4] Covered T295,T139,T117
addr_hit[5] Covered T295,T139,T117
addr_hit[6] Covered T295,T139,T117
addr_hit[7] Covered T295,T139,T117
addr_hit[8] Covered T295,T139,T117
addr_hit[9] Covered T295,T139,T117
addr_hit[10] Covered T3,T93,T311
addr_hit[11] Covered T3,T93,T311
addr_hit[12] Covered T3,T93,T311
addr_hit[13] Covered T3,T93,T311
addr_hit[14] Covered T3,T93,T311
addr_hit[15] Covered T3,T93,T311
addr_hit[16] Covered T3,T93,T311
addr_hit[17] Covered T3,T93,T311
addr_hit[18] Covered T3,T93,T311
addr_hit[19] Covered T135,T139,T261
addr_hit[20] Covered T135,T139,T261
addr_hit[21] Covered T135,T139,T261
addr_hit[22] Covered T135,T139,T261
addr_hit[23] Covered T135,T139,T261
addr_hit[24] Covered T135,T139,T261
addr_hit[25] Covered T135,T139,T261
addr_hit[26] Covered T135,T139,T261
addr_hit[27] Covered T135,T139,T261
addr_hit[28] Covered T139,T30,T261
addr_hit[29] Covered T139,T30,T261
addr_hit[30] Covered T139,T30,T261
addr_hit[31] Covered T139,T30,T261
addr_hit[32] Covered T139,T30,T261
addr_hit[33] Covered T139,T30,T261
addr_hit[34] Covered T139,T30,T261
addr_hit[35] Covered T139,T30,T261
addr_hit[36] Covered T139,T30,T261
addr_hit[37] Covered T139,T261,T262
addr_hit[38] Covered T139,T261,T262
addr_hit[39] Covered T139,T261,T262
addr_hit[40] Covered T139,T261,T262
addr_hit[41] Covered T139,T261,T262
addr_hit[42] Covered T139,T261,T262
addr_hit[43] Covered T139,T261,T262
addr_hit[44] Covered T139,T261,T262
addr_hit[45] Covered T139,T261,T262
addr_hit[46] Covered T139,T261,T262
addr_hit[47] Covered T139,T261,T262
addr_hit[48] Covered T139,T261,T262
addr_hit[49] Covered T139,T261,T262
addr_hit[50] Covered T139,T261,T262
addr_hit[51] Covered T139,T261,T262
addr_hit[52] Covered T139,T261,T262
addr_hit[53] Covered T139,T261,T262
addr_hit[54] Covered T139,T261,T262
addr_hit[55] Covered T139,T261,T262
addr_hit[56] Covered T139,T261,T262
addr_hit[57] Covered T139,T261,T262
addr_hit[58] Covered T139,T261,T262
addr_hit[59] Covered T139,T261,T262
addr_hit[60] Covered T139,T261,T262
addr_hit[61] Covered T139,T261,T262
addr_hit[62] Covered T139,T261,T262
addr_hit[63] Covered T139,T261,T262
addr_hit[64] Covered T139,T261,T262
addr_hit[65] Covered T139,T261,T262
addr_hit[66] Covered T139,T261,T262
addr_hit[67] Covered T139,T261,T262
addr_hit[68] Covered T139,T261,T262
addr_hit[69] Covered T139,T26,T261
addr_hit[70] Covered T139,T261,T262
addr_hit[71] Covered T139,T261,T262
addr_hit[72] Covered T139,T26,T261
addr_hit[73] Covered T139,T26,T261
addr_hit[74] Covered T139,T261,T262
addr_hit[75] Covered T139,T261,T262
addr_hit[76] Covered T139,T261,T262
addr_hit[77] Covered T139,T261,T262
addr_hit[78] Covered T139,T261,T262
addr_hit[79] Covered T139,T261,T262
addr_hit[80] Covered T139,T261,T262
addr_hit[81] Covered T139,T261,T262
addr_hit[82] Covered T139,T261,T262
addr_hit[83] Covered T139,T261,T262
addr_hit[84] Covered T139,T261,T262
addr_hit[85] Covered T139,T261,T262
addr_hit[86] Covered T218,T139,T261
addr_hit[87] Covered T218,T139,T261
addr_hit[88] Covered T139,T261,T262
addr_hit[89] Covered T218,T139,T261
addr_hit[90] Covered T218,T139,T261
addr_hit[91] Covered T218,T139,T261
addr_hit[92] Covered T139,T261,T262
addr_hit[93] Covered T139,T261,T262
addr_hit[94] Covered T139,T261,T262
addr_hit[95] Covered T139,T261,T262
addr_hit[96] Covered T139,T261,T262
addr_hit[97] Covered T139,T261,T262
addr_hit[98] Covered T139,T261,T262
addr_hit[99] Covered T139,T261,T262
addr_hit[100] Covered T139,T261,T262
addr_hit[101] Covered T139,T261,T262
addr_hit[102] Covered T139,T261,T262
addr_hit[103] Covered T139,T261,T262
addr_hit[104] Covered T139,T261,T262
addr_hit[105] Covered T139,T261,T262
addr_hit[106] Covered T139,T261,T262
addr_hit[107] Covered T139,T219,T261
addr_hit[108] Covered T139,T219,T261
addr_hit[109] Covered T139,T261,T262
addr_hit[110] Covered T139,T219,T261
addr_hit[111] Covered T139,T219,T261
addr_hit[112] Covered T139,T219,T261
addr_hit[113] Covered T139,T219,T261
addr_hit[114] Covered T139,T219,T261
addr_hit[115] Covered T139,T261,T262
addr_hit[116] Covered T139,T219,T261
addr_hit[117] Covered T139,T261,T262
addr_hit[118] Covered T139,T261,T262
addr_hit[119] Covered T139,T261,T262
addr_hit[120] Covered T139,T261,T262
addr_hit[121] Covered T139,T261,T262
addr_hit[122] Covered T139,T261,T262
addr_hit[123] Covered T139,T261,T262
addr_hit[124] Covered T139,T261,T262
addr_hit[125] Covered T139,T261,T262
addr_hit[126] Covered T139,T261,T262
addr_hit[127] Covered T4,T77,T78
addr_hit[128] Covered T4,T77,T78
addr_hit[129] Covered T4,T77,T78
addr_hit[130] Covered T4,T77,T78
addr_hit[131] Covered T139,T26,T261
addr_hit[132] Covered T139,T26,T261
addr_hit[133] Covered T139,T261,T262
addr_hit[134] Covered T139,T261,T262
addr_hit[135] Covered T139,T261,T262
addr_hit[136] Covered T139,T261,T262
addr_hit[137] Covered T139,T261,T262
addr_hit[138] Covered T139,T261,T262
addr_hit[139] Covered T139,T261,T262
addr_hit[140] Covered T139,T261,T262
addr_hit[141] Covered T139,T261,T262
addr_hit[142] Covered T139,T261,T262
addr_hit[143] Covered T139,T261,T262
addr_hit[144] Covered T139,T261,T262
addr_hit[145] Covered T139,T261,T262
addr_hit[146] Covered T139,T261,T262
addr_hit[147] Covered T139,T261,T262
addr_hit[148] Covered T139,T261,T262
addr_hit[149] Covered T139,T261,T262
addr_hit[150] Covered T139,T261,T262
addr_hit[151] Covered T139,T261,T262
addr_hit[152] Covered T139,T261,T262
addr_hit[153] Covered T1,T266,T29
addr_hit[154] Covered T139,T261,T262
addr_hit[155] Covered T139,T261,T118
addr_hit[156] Covered T4,T77,T78
addr_hit[157] Covered T4,T77,T78
addr_hit[158] Covered T139,T261,T262
addr_hit[159] Covered T139,T261,T262
addr_hit[160] Covered T139,T367,T284
addr_hit[161] Covered T139,T367,T284
addr_hit[162] Covered T139,T367,T284
addr_hit[163] Covered T139,T367,T284
addr_hit[164] Covered T139,T367,T284
addr_hit[165] Covered T139,T261,T262
addr_hit[166] Covered T154,T139,T261
addr_hit[167] Covered T154,T139,T261
addr_hit[168] Covered T139,T261,T262
addr_hit[169] Covered T139,T261,T262
addr_hit[170] Covered T139,T261,T262
addr_hit[171] Covered T139,T261,T262
addr_hit[172] Covered T139,T261,T183
addr_hit[173] Covered T139,T261,T262
addr_hit[174] Covered T139,T261,T262
addr_hit[175] Covered T22,T139,T261
addr_hit[176] Covered T139,T261,T262
addr_hit[177] Covered T139,T261,T262
addr_hit[178] Covered T139,T261,T262
addr_hit[179] Covered T139,T261,T27
addr_hit[180] Covered T139,T261,T262
addr_hit[181] Covered T139,T261,T262
addr_hit[182] Covered T22,T139,T261
addr_hit[183] Covered T139,T261,T262
addr_hit[184] Covered T22,T139,T261
addr_hit[185] Covered T139,T261,T262
addr_hit[186] Covered T14
addr_hit[187] Covered T14
addr_hit[188] Covered T14
addr_hit[189] Covered T14
addr_hit[190] Covered T14,T388,T389
addr_hit[191] Covered T14
addr_hit[192] Covered T3,T93,T311
addr_hit[193] Covered T139,T30,T261
addr_hit[194] Covered T218,T139,T26
addr_hit[195] Covered T4,T77,T78
addr_hit[196] Covered T1,T4,T266
addr_hit[197] Covered T22,T154,T139
addr_hit[198] Covered T1,T3,T22
addr_hit[199] Covered T1,T3,T22
addr_hit[200] Covered T261,T262,T14
addr_hit[201] Covered T14,T64,T65
default Not Covered


Assert Coverage for Module : rv_plic_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 541565630 33063 0 0
reAfterRv 541565630 33063 0 0
rePulse 541565630 13349 0 0
wePulse 541565630 19714 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 541565630 33063 0 0
T1 140293 8 0 0
T2 97883 0 0 0
T3 112985 48 0 0
T4 235876 44 0 0
T5 126352 0 0 0
T6 431859 0 0 0
T22 391042 2308 0 0
T59 939792 0 0 0
T62 201313 0 0 0
T77 0 104 0 0
T78 0 44 0 0
T93 108984 48 0 0
T135 0 48 0 0
T266 0 8 0 0
T311 0 46 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 541565630 33063 0 0
T1 140293 8 0 0
T2 97883 0 0 0
T3 112985 48 0 0
T4 235876 44 0 0
T5 126352 0 0 0
T6 431859 0 0 0
T22 391042 2308 0 0
T59 939792 0 0 0
T62 201313 0 0 0
T77 0 104 0 0
T78 0 44 0 0
T93 108984 48 0 0
T135 0 48 0 0
T266 0 8 0 0
T311 0 46 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 541565630 13349 0 0
T1 140293 3 0 0
T2 97883 0 0 0
T3 112985 19 0 0
T4 235876 14 0 0
T5 126352 0 0 0
T6 431859 0 0 0
T22 391042 1136 0 0
T59 939792 0 0 0
T62 201313 0 0 0
T77 0 32 0 0
T78 0 14 0 0
T93 108984 19 0 0
T135 0 19 0 0
T266 0 3 0 0
T311 0 18 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 541565630 19714 0 0
T1 140293 5 0 0
T2 97883 0 0 0
T3 112985 29 0 0
T4 235876 30 0 0
T5 126352 0 0 0
T6 431859 0 0 0
T22 391042 1172 0 0
T59 939792 0 0 0
T62 201313 0 0 0
T77 0 72 0 0
T78 0 30 0 0
T93 108984 29 0 0
T135 0 29 0 0
T266 0 5 0 0
T311 0 28 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%