Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3644039	1			T85	65		T86	93		T87	222
values[2]	729102	1			T85	47		T86	49		T87	67
values[3]	108392	1			T85	1		T91	2		T250	2
values[4]	57089	1			T776	1		T414	104		T619	14
values[5]	37481	1			T776	1		T414	82		T619	25
values[6]	27480	1			T776	1		T414	81		T619	29
values[7]	21120	1			T776	1		T414	75		T619	21
values[8]	17417	1			T776	1		T414	75		T619	12
values[9]	15460	1			T776	1		T414	93		T619	34
values[10]	13987	1			T776	1		T414	76		T619	31
values[11]	12631	1			T776	1		T414	76		T619	21
values[12]	12031	1			T776	1		T414	109		T619	16
values[13]	11508	1			T776	1		T414	86		T619	7
values[14]	10917	1			T776	1		T414	73		T619	7
values[15]	10390	1			T776	1		T414	71		T619	26
values[16]	10042	1			T776	1		T414	45		T619	27
values[17]	9656	1			T776	1		T414	66		T619	16
values[18]	9344	1			T776	1		T414	77		T619	21
values[19]	8783	1			T776	1		T414	82		T619	16
values[20]	8202	1			T776	1		T414	96		T619	21
values[21]	7893	1			T776	1		T414	72		T619	26
values[22]	7760	1			T776	1		T414	50		T619	28
values[23]	7540	1			T776	1		T414	57		T619	26
values[24]	7311	1			T776	1		T414	57		T619	38
values[25]	6956	1			T776	1		T414	60		T619	33
values[26]	6592	1			T776	1		T414	51		T619	34
values[27]	6504	1			T776	1		T414	80		T619	49
values[28]	6290	1			T776	1		T414	60		T619	33
values[29]	6064	1			T776	1		T414	59		T619	20
values[30]	5741	1			T776	1		T414	76		T619	6
values[31]	5326	1			T776	1		T414	53		T619	8
values[32]	5011	1			T776	1		T414	31		T619	2
values[33]	4619	1			T776	1		T414	29		T619	5
values[34]	4213	1			T776	1		T414	21		T619	4
values[35]	4148	1			T776	1		T414	26		T619	5
values[36]	3928	1			T776	1		T414	23		T619	4
values[37]	3678	1			T776	1		T414	16		T619	6
values[38]	3568	1			T776	1		T414	19		T619	4
values[39]	3380	1			T776	1		T414	25		T619	1
values[40]	3267	1			T776	1		T414	18		T619	7
values[41]	3177	1			T776	1		T414	12		T619	3
values[42]	3113	1			T776	1		T414	26		T619	2
values[43]	3042	1			T776	1		T414	22		T619	1
values[44]	2958	1			T776	1		T414	16		T619	1
values[45]	2859	1			T776	1		T414	9		T619	1
values[46]	2834	1			T776	1		T414	11		T619	2
values[47]	2809	1			T776	1		T414	11		T619	2
values[48]	2812	1			T776	1		T414	11		T619	8
values[49]	2753	1			T776	1		T414	11		T619	4
values[50]	2661	1			T776	1		T414	13		T619	4
values[51]	2597	1			T776	1		T414	17		T619	6
values[52]	2593	1			T776	1		T414	16		T619	6
values[53]	2544	1			T776	1		T414	4		T619	1
values[54]	2467	1			T776	1		T414	11		T619	1
values[55]	2439	1			T776	1		T414	13		T619	1
values[56]	2422	1			T776	1		T414	3		T619	1
values[57]	2372	1			T776	1		T414	6		T619	1
values[58]	2269	1			T776	1		T619	2		T716	2
values[59]	2303	1			T776	1		T716	3		T455	4
values[60]	2350	1			T776	1		T716	1		T455	1
values[61]	2494	1			T776	1		T716	6		T601	1
values[62]	3794	1			T776	1		T716	9		T601	1
values[63]	10655	1			T776	2		T716	34		T601	10
values[64]	211135	1			T776	144		T716	71		T601	24

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4631133	1			T85	91		T86	85		T87	283
values[2]	773542	1			T85	18		T86	32		T87	70
values[3]	83089	1			T86	1		T87	1		T89	7
values[4]	14455	1			T417	2		T776	1		T509	1
values[5]	5317	1			T417	1		T776	1		T495	6
values[6]	3144	1			T417	1		T776	1		T495	5
values[7]	2409	1			T776	1		T495	13		T527	1
values[8]	2019	1			T776	1		T495	4		T601	25
values[9]	1919	1			T776	1		T495	9		T601	29
values[10]	1746	1			T776	1		T495	3		T601	33
values[11]	1624	1			T776	1		T601	22		T437	1
values[12]	1529	1			T776	1		T601	30		T437	1
values[13]	1482	1			T776	1		T601	27		T437	1
values[14]	1365	1			T776	1		T601	29		T437	1
values[15]	1203	1			T776	1		T601	19		T437	1
values[16]	1057	1			T776	1		T601	15		T437	1
values[17]	946	1			T776	1		T601	17		T437	1
values[18]	864	1			T776	1		T601	14		T437	1
values[19]	840	1			T776	1		T601	21		T437	1
values[20]	821	1			T776	1		T601	14		T437	1
values[21]	787	1			T776	1		T601	26		T437	1
values[22]	777	1			T776	1		T601	15		T437	1
values[23]	738	1			T776	1		T601	14		T437	1
values[24]	687	1			T776	1		T601	5		T437	1
values[25]	677	1			T776	1		T601	4		T437	1
values[26]	612	1			T776	1		T437	2		T570	7
values[27]	564	1			T776	1		T437	1		T570	11
values[28]	602	1			T776	1		T437	1		T570	9
values[29]	529	1			T776	1		T437	1		T570	12
values[30]	560	1			T776	1		T437	1		T570	8
values[31]	517	1			T776	1		T437	1		T570	6
values[32]	539	1			T776	1		T437	1		T570	6
values[33]	525	1			T776	1		T437	1		T570	9
values[34]	498	1			T776	1		T437	1		T570	12
values[35]	468	1			T776	1		T437	1		T570	15
values[36]	395	1			T776	1		T437	1		T570	5
values[37]	448	1			T776	1		T437	1		T570	9
values[38]	443	1			T776	1		T437	1		T570	20
values[39]	463	1			T776	1		T437	1		T570	17
values[40]	450	1			T776	1		T437	1		T570	10
values[41]	422	1			T776	1		T437	1		T570	6
values[42]	460	1			T776	1		T437	1		T570	8
values[43]	431	1			T776	1		T437	1		T570	8
values[44]	439	1			T776	1		T437	1		T570	11
values[45]	408	1			T776	1		T437	1		T570	5
values[46]	381	1			T776	1		T437	1		T570	3
values[47]	368	1			T776	1		T437	1		T570	6
values[48]	366	1			T776	1		T437	1		T570	5
values[49]	398	1			T776	1		T437	1		T570	3
values[50]	377	1			T776	1		T437	1		T570	2
values[51]	363	1			T776	1		T437	1		T570	1
values[52]	342	1			T776	1		T437	1		T570	1
values[53]	329	1			T776	1		T437	1		T570	2
values[54]	351	1			T776	1		T437	1		T570	2
values[55]	337	1			T776	1		T437	1		T570	3
values[56]	328	1			T776	1		T437	1		T570	1
values[57]	344	1			T776	1		T437	1		T570	3
values[58]	347	1			T776	1		T437	1		T570	1
values[59]	334	1			T776	1		T437	1		T570	1
values[60]	330	1			T776	1		T437	1		T570	1
values[61]	314	1			T776	1		T437	1		T570	3
values[62]	569	1			T776	1		T437	1		T570	5
values[63]	2181	1			T776	1		T437	1		T570	24
values[64]	24387	1			T776	230		T437	225		T570	49

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	581751	1			T85	1		T86	1		T87	2
values[2]	2571211	1			T85	63		T86	57		T87	206
values[3]	1152547	1			T85	42		T86	43		T87	67
values[4]	153134	1			T85	2		T89	1		T91	1
values[5]	78566	1			T776	1		T414	80		T619	19
values[6]	49997	1			T776	1		T414	80		T619	21
values[7]	35877	1			T776	1		T414	80		T619	22
values[8]	27277	1			T776	1		T414	119		T619	34
values[9]	22457	1			T776	1		T414	98		T619	12
values[10]	19580	1			T776	1		T414	76		T619	16
values[11]	17302	1			T776	1		T414	87		T619	18
values[12]	15663	1			T776	1		T414	82		T619	25
values[13]	14611	1			T776	2		T414	72		T619	40
values[14]	13625	1			T776	1		T414	105		T619	34
values[15]	12547	1			T776	1		T414	69		T619	24
values[16]	11772	1			T776	1		T414	70		T619	21
values[17]	11331	1			T776	1		T414	50		T619	36
values[18]	10977	1			T776	1		T414	63		T619	25
values[19]	10849	1			T776	1		T414	50		T619	14
values[20]	10288	1			T776	1		T414	51		T619	9
values[21]	9985	1			T776	1		T414	78		T619	20
values[22]	9554	1			T776	1		T414	80		T619	36
values[23]	9151	1			T776	1		T414	81		T619	30
values[24]	8708	1			T776	1		T414	77		T619	32
values[25]	8326	1			T776	1		T414	69		T619	32
values[26]	7957	1			T776	1		T414	58		T619	21
values[27]	7264	1			T776	1		T414	26		T619	15
values[28]	6953	1			T776	1		T414	28		T619	9
values[29]	6666	1			T776	1		T414	30		T619	10
values[30]	6277	1			T776	1		T414	38		T619	11
values[31]	5895	1			T776	1		T414	40		T619	14
values[32]	5361	1			T776	1		T414	13		T619	11
values[33]	4926	1			T776	1		T414	11		T619	4
values[34]	4549	1			T776	1		T414	16		T619	4
values[35]	4358	1			T776	1		T414	10		T619	3
values[36]	4177	1			T776	1		T414	17		T619	3
values[37]	3832	1			T776	1		T414	18		T619	5
values[38]	3804	1			T776	1		T414	4		T619	10
values[39]	3621	1			T776	1		T414	6		T619	10
values[40]	3504	1			T776	1		T414	3		T619	11
values[41]	3453	1			T776	1		T414	3		T619	6
values[42]	3416	1			T776	1		T414	2		T619	1
values[43]	3381	1			T776	1		T414	2		T619	3
values[44]	3315	1			T776	1		T414	2		T619	5
values[45]	3193	1			T776	1		T414	6		T619	6
values[46]	3162	1			T776	1		T414	4		T619	3
values[47]	3125	1			T776	1		T414	4		T619	1
values[48]	3003	1			T776	1		T414	5		T619	3
values[49]	3031	1			T776	1		T414	3		T619	1
values[50]	3006	1			T776	1		T414	4		T619	3
values[51]	3013	1			T776	1		T619	5		T716	1
values[52]	2861	1			T776	1		T619	5		T716	1
values[53]	2780	1			T776	1		T619	4		T716	2
values[54]	2750	1			T776	1		T619	7		T716	4
values[55]	2624	1			T776	1		T619	1		T716	5
values[56]	2605	1			T776	1		T716	3		T601	7
values[57]	2620	1			T776	1		T716	3		T601	10
values[58]	2628	1			T776	1		T716	2		T601	7
values[59]	2589	1			T776	1		T716	4		T601	10
values[60]	2605	1			T776	1		T716	2		T601	9
values[61]	2663	1			T776	1		T716	1		T601	8
values[62]	3571	1			T776	1		T716	2		T601	7
values[63]	9148	1			T776	1		T716	31		T601	20
values[64]	202668	1			T776	215		T716	84		T601	90