Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2220860	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

28829844

1

T1

5784

T2

4823

T3

11684

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	21332487	1			T1	2368		T2	1583		T3	5980
values[0x0]	8407413	1			T1	3416		T2	3240		T3	5704
values[0x1]	1310804	1			T1	289		T2	139		T3	685

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	914240	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

30136464

1

T1

6073

T2

4962

T3

12369

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14044992	1			T1	3037		T2	2481		T3	6185
valid_sources[0x01]	14043506	1			T1	3036		T2	2481		T3	6184
valid_sources[0x02]	47945	1			T80	2		T96	69		T379	14
valid_sources[0x03]	46994	1			T210	1		T96	67		T379	18
valid_sources[0x04]	47096	1			T32	2		T209	8		T96	90
valid_sources[0x05]	47567	1			T210	1		T96	80		T379	26
valid_sources[0x06]	46633	1			T80	1		T96	68		T379	20
valid_sources[0x07]	47302	1			T210	1		T96	95		T379	12
valid_sources[0x08]	48105	1			T62	3		T96	80		T379	13
valid_sources[0x09]	48986	1			T32	1		T80	1		T62	5
valid_sources[0x0a]	48507	1			T210	1		T62	1		T96	66
valid_sources[0x0b]	46618	1			T32	1		T62	6		T96	84
valid_sources[0x0c]	47180	1			T209	1		T96	79		T379	22
valid_sources[0x0d]	47250	1			T80	2		T96	68		T379	22
valid_sources[0x0e]	47397	1			T52	2		T210	2		T62	1
valid_sources[0x0f]	47815	1			T80	1		T96	84		T379	26
valid_sources[0x10]	47456	1			T80	1		T52	2		T96	82
valid_sources[0x11]	46974	1			T32	1		T210	3		T96	56
valid_sources[0x12]	47155	1			T80	4		T52	2		T62	6
valid_sources[0x13]	47872	1			T52	2		T62	1		T96	88
valid_sources[0x14]	47569	1			T32	2		T210	1		T96	82
valid_sources[0x15]	47032	1			T32	2		T96	63		T379	21
valid_sources[0x16]	47873	1			T80	1		T52	3		T209	3
valid_sources[0x17]	48672	1			T80	1		T52	2		T210	2
valid_sources[0x18]	47595	1			T80	1		T52	1		T96	94
valid_sources[0x19]	54523	1			T210	2		T96	82		T379	15
valid_sources[0x1a]	47197	1			T32	1		T80	1		T210	1
valid_sources[0x1b]	48216	1			T32	1		T80	1		T52	1
valid_sources[0x1c]	47668	1			T80	1		T210	3		T96	80
valid_sources[0x1d]	46657	1			T32	3		T96	101		T379	20
valid_sources[0x1e]	47491	1			T32	1		T209	4		T210	3
valid_sources[0x1f]	46884	1			T96	61		T379	21		T519	27
valid_sources[0x20]	47553	1			T32	1		T80	3		T52	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

20243463

1

T1

2368

T2

1583

T3

5980

values[0x0]

all_enables

biggest_size

8355467

1

T1

3416

T2

3240

T3

5704

values[0x1]

all_enables

biggest_size

230914

1

T32

20

T80

21

T52

18

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2735294	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

431761

1

T85

22

T86

22

T87

36

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1073168	1			T85	40		T86	47		T87	85
values[0x0]	1021178	1			T85	38		T86	52		T87	89
values[0x1]	1072709	1			T85	35		T86	43		T87	115

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2117159	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1049896

1

T85

42

T86

49

T87

92

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	48475	1			T86	2		T89	18		T250	14
valid_sources[0x01]	49352	1			T85	2		T86	4		T87	5
valid_sources[0x02]	50236	1			T85	5		T86	5		T87	6
valid_sources[0x03]	49726	1			T85	1		T86	4		T87	9
valid_sources[0x04]	48186	1			T85	2		T86	4		T89	24
valid_sources[0x05]	50025	1			T85	3		T86	1		T87	7
valid_sources[0x06]	50220	1			T85	1		T86	1		T87	19
valid_sources[0x07]	49195	1			T85	3		T87	2		T89	23
valid_sources[0x08]	49762	1			T85	2		T87	11		T89	27
valid_sources[0x09]	50150	1			T85	2		T86	5		T87	17
valid_sources[0x0a]	48899	1			T85	1		T86	1		T89	13
valid_sources[0x0b]	49061	1			T85	2		T86	3		T87	3
valid_sources[0x0c]	49404	1			T85	2		T86	1		T89	28
valid_sources[0x0d]	50008	1			T85	2		T86	3		T87	8
valid_sources[0x0e]	49022	1			T85	3		T86	3		T87	2
valid_sources[0x0f]	49707	1			T85	1		T86	2		T89	17
valid_sources[0x10]	49262	1			T85	1		T86	2		T87	3
valid_sources[0x11]	49990	1			T85	4		T86	3		T87	4
valid_sources[0x12]	49794	1			T85	1		T86	4		T87	1
valid_sources[0x13]	48884	1			T85	1		T86	1		T87	9
valid_sources[0x14]	49327	1			T86	1		T87	3		T89	21
valid_sources[0x15]	50008	1			T85	1		T86	1		T87	11
valid_sources[0x16]	49030	1			T85	1		T86	1		T89	13
valid_sources[0x17]	49221	1			T85	4		T86	1		T87	1
valid_sources[0x18]	49000	1			T85	2		T86	3		T87	1
valid_sources[0x19]	48488	1			T86	4		T89	30		T91	3
valid_sources[0x1a]	49747	1			T85	1		T86	2		T87	4
valid_sources[0x1b]	50183	1			T85	5		T86	1		T87	1
valid_sources[0x1c]	48850	1			T85	2		T87	2		T89	15
valid_sources[0x1d]	50239	1			T85	2		T86	1		T87	11
valid_sources[0x1e]	49427	1			T85	1		T86	1		T87	20
valid_sources[0x1f]	49744	1			T85	1		T87	10		T89	26
valid_sources[0x20]	49461	1			T85	3		T86	1		T89	27

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

45471

1

T85

3

T86

3

T87

2

values[0x0]

all_enables

biggest_size

340976

1

T85

17

T86

18

T87

29

values[0x1]

all_enables

biggest_size

45314

1

T85

2

T86

1

T87

5

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2913424	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

474181

1

T85

14

T86

16

T87

51

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1161161	1			T85	35		T86	40		T87	126
values[0x0]	1067059	1			T85	35		T86	30		T87	112
values[0x1]	1159385	1			T85	39		T86	48		T87	116

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2235837	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1151768

1

T85

41

T86

38

T87

141

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52415	1			T86	5		T87	4		T89	27
valid_sources[0x01]	53437	1			T87	6		T89	26		T91	1
valid_sources[0x02]	53835	1			T86	8		T87	4		T90	1
valid_sources[0x03]	53182	1			T86	4		T87	3		T89	16
valid_sources[0x04]	52157	1			T85	6		T86	9		T87	4
valid_sources[0x05]	53192	1			T86	6		T87	4		T90	2
valid_sources[0x06]	53309	1			T86	4		T87	5		T89	21
valid_sources[0x07]	52561	1			T86	5		T87	9		T89	15
valid_sources[0x08]	53753	1			T85	3		T86	1		T87	6
valid_sources[0x09]	53406	1			T86	7		T87	8		T89	34
valid_sources[0x0a]	52093	1			T85	1		T87	6		T89	19
valid_sources[0x0b]	52874	1			T87	4		T89	21		T91	1
valid_sources[0x0c]	52368	1			T86	1		T87	3		T89	32
valid_sources[0x0d]	53713	1			T87	6		T89	25		T91	2
valid_sources[0x0e]	52911	1			T86	5		T87	4		T89	14
valid_sources[0x0f]	53099	1			T87	7		T89	24		T91	1
valid_sources[0x10]	53613	1			T85	8		T87	9		T89	19
valid_sources[0x11]	53098	1			T87	6		T89	17		T91	2
valid_sources[0x12]	53974	1			T86	1		T87	5		T90	1
valid_sources[0x13]	53234	1			T85	1		T87	5		T89	23
valid_sources[0x14]	54068	1			T85	9		T87	6		T89	10
valid_sources[0x15]	52989	1			T86	4		T87	4		T89	18
valid_sources[0x16]	53716	1			T85	7		T86	2		T87	4
valid_sources[0x17]	52538	1			T87	4		T89	11		T91	3
valid_sources[0x18]	53441	1			T86	3		T87	5		T89	39
valid_sources[0x19]	53378	1			T87	4		T89	28		T250	43
valid_sources[0x1a]	52806	1			T86	4		T87	3		T89	9
valid_sources[0x1b]	52174	1			T85	1		T87	3		T89	14
valid_sources[0x1c]	53239	1			T87	10		T89	14		T250	45
valid_sources[0x1d]	53019	1			T85	1		T86	4		T87	9
valid_sources[0x1e]	53025	1			T85	15		T87	4		T89	22
valid_sources[0x1f]	52974	1			T87	8		T89	22		T250	11
valid_sources[0x20]	52357	1			T87	5		T89	16		T91	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49844

1

T85

3

T86

3

T87

3

values[0x0]

all_enables

biggest_size

374468

1

T85

11

T86

11

T87

38

values[0x1]

all_enables

biggest_size

49869

1

T86

2

T87

10

T89

17

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2759953	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

436237

1

T85

14

T86

12

T87

33

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1082523	1			T85	38		T86	35		T87	89
values[0x0]	1031402	1			T85	36		T86	34		T87	91
values[0x1]	1082265	1			T85	34		T86	32		T87	95

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2136415	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1059775

1

T85

36

T86

28

T87

87

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	50350	1			T85	1		T86	7		T87	4
valid_sources[0x01]	49861	1			T85	1		T87	3		T89	21
valid_sources[0x02]	50097	1			T87	2		T90	1		T89	17
valid_sources[0x03]	50209	1			T85	3		T86	2		T87	6
valid_sources[0x04]	49814	1			T85	3		T87	4		T89	19
valid_sources[0x05]	50132	1			T85	3		T87	6		T89	28
valid_sources[0x06]	49746	1			T85	1		T87	5		T89	15
valid_sources[0x07]	50136	1			T85	1		T86	1		T87	6
valid_sources[0x08]	50542	1			T85	1		T87	6		T89	26
valid_sources[0x09]	50017	1			T86	1		T87	4		T89	23
valid_sources[0x0a]	50057	1			T85	3		T87	2		T89	20
valid_sources[0x0b]	49479	1			T85	3		T86	3		T87	4
valid_sources[0x0c]	49509	1			T85	3		T86	1		T87	5
valid_sources[0x0d]	49782	1			T85	2		T87	8		T89	22
valid_sources[0x0e]	50006	1			T85	6		T86	2		T87	2
valid_sources[0x0f]	49934	1			T86	5		T87	7		T89	12
valid_sources[0x10]	50553	1			T85	2		T86	3		T87	1
valid_sources[0x11]	50476	1			T85	3		T87	4		T89	15
valid_sources[0x12]	49830	1			T85	3		T86	1		T87	8
valid_sources[0x13]	49868	1			T85	1		T87	7		T89	12
valid_sources[0x14]	50235	1			T85	1		T86	3		T87	2
valid_sources[0x15]	51455	1			T85	2		T86	2		T87	2
valid_sources[0x16]	49917	1			T86	8		T87	3		T89	19
valid_sources[0x17]	49649	1			T85	7		T86	3		T87	10
valid_sources[0x18]	50195	1			T86	5		T87	6		T90	1
valid_sources[0x19]	50447	1			T85	5		T86	3		T87	3
valid_sources[0x1a]	49558	1			T85	5		T86	1		T87	6
valid_sources[0x1b]	50963	1			T86	1		T87	2		T89	11
valid_sources[0x1c]	50042	1			T87	6		T89	24		T250	25
valid_sources[0x1d]	49886	1			T85	4		T87	7		T90	1
valid_sources[0x1e]	49353	1			T85	3		T87	2		T89	23
valid_sources[0x1f]	51132	1			T85	1		T87	5		T89	16
valid_sources[0x20]	48562	1			T85	2		T86	2		T87	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46064

1

T85

1

T86

1

T87

2

values[0x0]

all_enables

biggest_size

344526

1

T85

13

T86

11

T87

29

values[0x1]

all_enables

biggest_size

45647

1

T87

2

T90

1

T89

23