Module Definition
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Module : ibex_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.46 93.46

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_ibex_ibex_top_0.1/rtl/ibex_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_core 95.78 95.78


Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.78 95.78


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.78 95.78


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.74 96.47 89.29 99.75 100.00 68.18 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : ibex_top
TotalCoveredPercent
Totals 42 33 78.57
Total Bits 826 772 93.46
Total Bits 0->1 413 386 93.46
Total Bits 1->0 413 386 93.46

Ports 42 33 78.57
Port Bits 826 772 93.46
Port Bits 0->1 413 386 93.46
Port Bits 1->0 413 386 93.46

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T39,T31,T33 Yes T1,T2,T3 INPUT
test_en_i No No No INPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.rf_cfg.test No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.test No No No INPUT
hart_id_i[31:0] Unreachable Unreachable Unreachable INPUT
boot_addr_i[31:0] Unreachable Unreachable Unreachable INPUT
instr_req_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
instr_gnt_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
instr_rvalid_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
instr_addr_o[1:0] Unreachable Unreachable Unreachable OUTPUT
instr_addr_o[16:2] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
instr_addr_o[27:17] No No No OUTPUT
instr_addr_o[29:28] Yes Yes *T189,*T48,*T280 Yes T189,T48,T280 OUTPUT
instr_addr_o[31:30] No No No OUTPUT
instr_rdata_i[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
instr_rdata_intg_i[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
instr_err_i Yes Yes T76,T218,T189 Yes T76,T218,T189 INPUT
data_req_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_gnt_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_rvalid_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_we_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_be_o[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_addr_o[1:0] Unreachable Unreachable Unreachable OUTPUT
data_addr_o[31:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_wdata_o[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_wdata_intg_o[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_rdata_i[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_rdata_intg_i[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_err_i Yes Yes T75,T76,T172 Yes T75,T76,T172 INPUT
irq_software_i Yes Yes T251,T252 Yes T251,T252 INPUT
irq_timer_i Yes Yes T115,T116,T117 Yes T115,T116,T117 INPUT
irq_external_i Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
irq_fast_i[14:0] Unreachable Unreachable Unreachable INPUT
irq_nm_i Yes Yes T39,T75,T76 Yes T39,T75,T76 INPUT
scramble_key_valid_i Yes Yes T190,T191,T192 Yes T190,T191,T192 INPUT
scramble_key_i[127:0] Yes Yes T2,T3,T39 Yes T3,T39,T31 INPUT
scramble_nonce_i[63:0] Yes Yes T1,T4,T31 Yes T1,T2,T3 INPUT
scramble_req_o Yes Yes T189,T190,T191 Yes T189,T190,T191 OUTPUT
debug_req_i Yes Yes T253,T48,T49 Yes T253,T48,T49 INPUT
crash_dump_o.exception_addr[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.exception_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.last_data_addr[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.next_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.current_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
double_fault_seen_o Yes Yes T236,T237,T238 Yes T236,T237,T238 OUTPUT
fetch_enable_i[3:0] Yes Yes T1,T39,T31 Yes T1,T2,T3 INPUT
alert_minor_o No No No OUTPUT
alert_major_internal_o Yes Yes T376 Yes T376 OUTPUT
alert_major_bus_o Yes Yes T193,T187,T138 Yes T193,T187,T138 OUTPUT
core_sleep_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
scan_rst_ni Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_core
TotalCoveredPercent
Totals 38 33 86.84
Total Bits 806 772 95.78
Total Bits 0->1 403 386 95.78
Total Bits 1->0 403 386 95.78

Ports 38 33 86.84
Port Bits 806 772 95.78
Port Bits 0->1 403 386 95.78
Port Bits 1->0 403 386 95.78

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T39,T31,T33 Yes T1,T2,T3 INPUT
test_en_i No No No INPUT
ram_cfg_i.rf_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.test No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.test No No No INPUT
hart_id_i[31:0] Unreachable Unreachable Unreachable INPUT
boot_addr_i[31:0] Unreachable Unreachable Unreachable INPUT
instr_req_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
instr_gnt_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
instr_rvalid_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
instr_addr_o[1:0] Unreachable Unreachable Unreachable OUTPUT
instr_addr_o[16:2] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
instr_addr_o[27:17] No No No OUTPUT
instr_addr_o[29:28] Yes Yes *T189,*T48,*T280 Yes T189,T48,T280 OUTPUT
instr_addr_o[31:30] No No No OUTPUT
instr_rdata_i[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
instr_rdata_intg_i[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
instr_err_i Yes Yes T76,T218,T189 Yes T76,T218,T189 INPUT
data_req_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_gnt_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_rvalid_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_we_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_be_o[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_addr_o[1:0] Unreachable Unreachable Unreachable OUTPUT
data_addr_o[31:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_wdata_o[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_wdata_intg_o[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_rdata_i[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_rdata_intg_i[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_err_i Yes Yes T75,T76,T172 Yes T75,T76,T172 INPUT
irq_software_i Yes Yes T251,T252 Yes T251,T252 INPUT
irq_timer_i Yes Yes T115,T116,T117 Yes T115,T116,T117 INPUT
irq_external_i Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
irq_fast_i[14:0] Unreachable Unreachable Unreachable INPUT
irq_nm_i Yes Yes T39,T75,T76 Yes T39,T75,T76 INPUT
scramble_key_valid_i Yes Yes T190,T191,T192 Yes T190,T191,T192 INPUT
scramble_key_i[127:0] Yes Yes T2,T3,T39 Yes T3,T39,T31 INPUT
scramble_nonce_i[63:0] Yes Yes T1,T4,T31 Yes T1,T2,T3 INPUT
scramble_req_o Yes Yes T189,T190,T191 Yes T189,T190,T191 OUTPUT
debug_req_i Yes Yes T253,T48,T49 Yes T253,T48,T49 INPUT
crash_dump_o.exception_addr[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.exception_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.last_data_addr[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.next_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.current_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
double_fault_seen_o Yes Yes T236,T237,T238 Yes T236,T237,T238 OUTPUT
fetch_enable_i[3:0] Yes Yes T1,T39,T31 Yes T1,T2,T3 INPUT
alert_minor_o No No No OUTPUT
alert_major_internal_o Yes Yes T376 Yes T376 OUTPUT
alert_major_bus_o Yes Yes T193,T187,T138 Yes T193,T187,T138 OUTPUT
core_sleep_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
scan_rst_ni Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range
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