Unified Coverage Report :: Module :: prim_filter

Module : prim_filter

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup.u_prim_filter	59.84	63.64	44.44			71.43
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup.u_prim_filter	59.84	63.64	44.44			71.43
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup.u_prim_filter	91.53	100.00	88.89			85.71
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup.u_prim_filter	91.53	100.00	88.89			85.71
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup.u_prim_filter	91.53	100.00	88.89			85.71
tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_activity	100.00	100.00	100.00			100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_bus_reset	100.00	100.00	100.00			100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_sense	100.00	100.00	100.00			100.00
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup.u_prim_filter	100.00	100.00	100.00			100.00
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup.u_prim_filter	100.00	100.00	100.00			100.00
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup.u_prim_filter	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup.u_prim_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
59.84	63.64	44.44			71.43

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
67.58	76.47	44.44			81.82

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
25.56	26.32	23.08			27.27		gen_wkup_detect[4].u_pinmux_wkup

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_async.prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup.u_prim_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
59.84	63.64	44.44			71.43

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
67.58	76.47	44.44			81.82

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
45.52	52.63	38.46			45.45		gen_wkup_detect[6].u_pinmux_wkup

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_async.prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup.u_prim_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.53	100.00	88.89			85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.27	100.00	88.89			90.91

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
56.72	63.16	61.54			45.45		gen_wkup_detect[3].u_pinmux_wkup

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_async.prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup.u_prim_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.53	100.00	88.89			85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.27	100.00	88.89			90.91

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
64.07	68.42	69.23			54.55		gen_wkup_detect[5].u_pinmux_wkup

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_async.prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup.u_prim_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.53	100.00	88.89			85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.27	100.00	88.89			90.91

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
61.50	68.42	61.54			54.55		gen_wkup_detect[7].u_pinmux_wkup

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_async.prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_activity

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.63	97.44	86.36			94.74	100.00	u_usbdev_aon_wake

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_async.prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_bus_reset

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.63	97.44	86.36			94.74	100.00	u_usbdev_aon_wake

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_async.prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_sense

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.63	97.44	86.36			94.74	100.00	u_usbdev_aon_wake

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_async.prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup.u_prim_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.33	78.95	92.31			72.73		gen_wkup_detect[0].u_pinmux_wkup

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_async.prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup.u_prim_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
64.07	68.42	69.23			54.55		gen_wkup_detect[1].u_pinmux_wkup

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_async.prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup.u_prim_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
56.72	63.16	61.54			45.45		gen_wkup_detect[2].u_pinmux_wkup

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_async.prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_filter

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	48	4	4	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	3	3	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	70	1	1	100.00

47                        always_ff @(posedge clk_i or negedge rst_ni) begin
48         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
49         1/1                stored_value_q <= 1'b0;
           Tests:       T1 T2 T3 
50         1/1              end else if (update_stored_value) begin
           Tests:       T1 T2 T3 
51         1/1                stored_value_q <= filter_synced;
           Tests:       T1 T2 T3 
52                          end
                        MISSING_ELSE
53                        end
54                      
55         1/1            assign stored_vector_d = {stored_vector_q[Cycles-2:0],filter_synced};
           Tests:       T1 T2 T3 
56         1/1            assign unused_stored_vector_q_msb = stored_vector_q[Cycles-1];
           Tests:       T1 T2 T3 
57                      
58                        always_ff @(posedge clk_i or negedge rst_ni) begin
59         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
60         1/1                stored_vector_q <= '0;
           Tests:       T1 T2 T3 
61                          end else begin
62         1/1                stored_vector_q <= stored_vector_d;
           Tests:       T1 T2 T3 
63                          end
64                        end
65                      
66         1/1            assign update_stored_value =
           Tests:       T1 T2 T3 
67                                   (stored_vector_d == {Cycles{1'b0}}) |
68                                   (stored_vector_d == {Cycles{1'b1}});
69                      
70         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_filter

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_filter

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	70	2	2	100.00
IF	48	3	3	100.00
IF	59	2	2	100.00

70           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

48             if (!rst_ni) begin
               -1-  
49               stored_value_q <= 1'b0;
                 ==>
50             end else if (update_stored_value) begin
                        -2-  
51               stored_value_q <= filter_synced;
                 ==>
52             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

59             if (!rst_ni) begin
               -1-  
60               stored_vector_q <= '0;
                 ==>
61             end else begin
62               stored_vector_q <= stored_vector_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup.u_prim_filter

	Line No.	Total	Covered	Percent
TOTAL		11	7	63.64
ALWAYS	48	4	4	100.00
CONT_ASSIGN	55	1	0	0.00
CONT_ASSIGN	56	1	0	0.00
ALWAYS	59	3	3	100.00
CONT_ASSIGN	66	1	0	0.00
CONT_ASSIGN	70	1	0	0.00

47                        always_ff @(posedge clk_i or negedge rst_ni) begin
48         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
49         1/1                stored_value_q <= 1'b0;
           Tests:       T1 T2 T3 
50         1/1              end else if (update_stored_value) begin
           Tests:       T1 T2 T3 
51         1/1                stored_value_q <= filter_synced;
           Tests:       T1 T2 T3 
52                          end
                   ==>  MISSING_ELSE
53                        end
54                      
55         0/1     ==>    assign stored_vector_d = {stored_vector_q[Cycles-2:0],filter_synced};
56         0/1     ==>    assign unused_stored_vector_q_msb = stored_vector_q[Cycles-1];
57                      
58                        always_ff @(posedge clk_i or negedge rst_ni) begin
59         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
60         1/1                stored_vector_q <= '0;
           Tests:       T1 T2 T3 
61                          end else begin
62         1/1                stored_vector_q <= stored_vector_d;
           Tests:       T1 T2 T3 
63                          end
64                        end
65                      
66         0/1     ==>    assign update_stored_value =
67                                   (stored_vector_d == {Cycles{1'b0}}) |
68                                   (stored_vector_d == {Cycles{1'b1}});
69                      
70         0/1     ==>    assign filter_o = enable_i ? stored_value_q : filter_synced;

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup.u_prim_filter

	Total	Covered	Percent
Conditions	9	4	44.44
Logical	9	4	44.44
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup.u_prim_filter

	Line No.	Total	Covered	Percent
Branches		7	5	71.43
TERNARY	70	2	1	50.00
IF	48	3	2	66.67
IF	59	2	2	100.00

70           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

48             if (!rst_ni) begin
               -1-  
49               stored_value_q <= 1'b0;
                 ==>
50             end else if (update_stored_value) begin
                        -2-  
51               stored_value_q <= filter_synced;
                 ==>
52             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

59             if (!rst_ni) begin
               -1-  
60               stored_vector_q <= '0;
                 ==>
61             end else begin
62               stored_vector_q <= stored_vector_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup.u_prim_filter

	Line No.	Total	Covered	Percent
TOTAL		11	7	63.64
ALWAYS	48	4	4	100.00
CONT_ASSIGN	55	1	0	0.00
CONT_ASSIGN	56	1	0	0.00
ALWAYS	59	3	3	100.00
CONT_ASSIGN	66	1	0	0.00
CONT_ASSIGN	70	1	0	0.00

47                        always_ff @(posedge clk_i or negedge rst_ni) begin
48         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
49         1/1                stored_value_q <= 1'b0;
           Tests:       T1 T2 T3 
50         1/1              end else if (update_stored_value) begin
           Tests:       T1 T2 T3 
51         1/1                stored_value_q <= filter_synced;
           Tests:       T1 T2 T3 
52                          end
                   ==>  MISSING_ELSE
53                        end
54                      
55         0/1     ==>    assign stored_vector_d = {stored_vector_q[Cycles-2:0],filter_synced};
56         0/1     ==>    assign unused_stored_vector_q_msb = stored_vector_q[Cycles-1];
57                      
58                        always_ff @(posedge clk_i or negedge rst_ni) begin
59         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
60         1/1                stored_vector_q <= '0;
           Tests:       T1 T2 T3 
61                          end else begin
62         1/1                stored_vector_q <= stored_vector_d;
           Tests:       T1 T2 T3 
63                          end
64                        end
65                      
66         0/1     ==>    assign update_stored_value =
67                                   (stored_vector_d == {Cycles{1'b0}}) |
68                                   (stored_vector_d == {Cycles{1'b1}});
69                      
70         0/1     ==>    assign filter_o = enable_i ? stored_value_q : filter_synced;

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup.u_prim_filter

	Total	Covered	Percent
Conditions	9	4	44.44
Logical	9	4	44.44
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup.u_prim_filter

	Line No.	Total	Covered	Percent
Branches		7	5	71.43
TERNARY	70	2	1	50.00
IF	48	3	2	66.67
IF	59	2	2	100.00

70           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

48             if (!rst_ni) begin
               -1-  
49               stored_value_q <= 1'b0;
                 ==>
50             end else if (update_stored_value) begin
                        -2-  
51               stored_value_q <= filter_synced;
                 ==>
52             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

59             if (!rst_ni) begin
               -1-  
60               stored_vector_q <= '0;
                 ==>
61             end else begin
62               stored_vector_q <= stored_vector_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup.u_prim_filter

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	48	4	4	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	3	3	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	70	1	1	100.00

47                        always_ff @(posedge clk_i or negedge rst_ni) begin
48         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
49         1/1                stored_value_q <= 1'b0;
           Tests:       T1 T2 T3 
50         1/1              end else if (update_stored_value) begin
           Tests:       T1 T2 T3 
51         1/1                stored_value_q <= filter_synced;
           Tests:       T1 T2 T3 
52                          end
                        MISSING_ELSE
53                        end
54                      
55         1/1            assign stored_vector_d = {stored_vector_q[Cycles-2:0],filter_synced};
           Tests:       T32 
56         1/1            assign unused_stored_vector_q_msb = stored_vector_q[Cycles-1];
           Tests:       T32 
57                      
58                        always_ff @(posedge clk_i or negedge rst_ni) begin
59         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
60         1/1                stored_vector_q <= '0;
           Tests:       T1 T2 T3 
61                          end else begin
62         1/1                stored_vector_q <= stored_vector_d;
           Tests:       T1 T2 T3 
63                          end
64                        end
65                      
66         1/1            assign update_stored_value =
           Tests:       T32 
67                                   (stored_vector_d == {Cycles{1'b0}}) |
68                                   (stored_vector_d == {Cycles{1'b1}});
69                      
70         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T32 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup.u_prim_filter

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T32
0	1	Covered	T32
1	0	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T32
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T32

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup.u_prim_filter

	Line No.	Total	Covered	Percent
Branches		7	6	85.71
TERNARY	70	2	1	50.00
IF	48	3	3	100.00
IF	59	2	2	100.00

70           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

48             if (!rst_ni) begin
               -1-  
49               stored_value_q <= 1'b0;
                 ==>
50             end else if (update_stored_value) begin
                        -2-  
51               stored_value_q <= filter_synced;
                 ==>
52             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T32

59             if (!rst_ni) begin
               -1-  
60               stored_vector_q <= '0;
                 ==>
61             end else begin
62               stored_vector_q <= stored_vector_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup.u_prim_filter

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	48	4	4	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	3	3	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	70	1	1	100.00

47                        always_ff @(posedge clk_i or negedge rst_ni) begin
48         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
49         1/1                stored_value_q <= 1'b0;
           Tests:       T1 T2 T3 
50         1/1              end else if (update_stored_value) begin
           Tests:       T1 T2 T3 
51         1/1                stored_value_q <= filter_synced;
           Tests:       T1 T2 T3 
52                          end
                        MISSING_ELSE
53                        end
54                      
55         1/1            assign stored_vector_d = {stored_vector_q[Cycles-2:0],filter_synced};
           Tests:       T67 T68 T20 
56         1/1            assign unused_stored_vector_q_msb = stored_vector_q[Cycles-1];
           Tests:       T67 T68 T20 
57                      
58                        always_ff @(posedge clk_i or negedge rst_ni) begin
59         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
60         1/1                stored_vector_q <= '0;
           Tests:       T1 T2 T3 
61                          end else begin
62         1/1                stored_vector_q <= stored_vector_d;
           Tests:       T1 T2 T3 
63                          end
64                        end
65                      
66         1/1            assign update_stored_value =
           Tests:       T67 T68 T20 
67                                   (stored_vector_d == {Cycles{1'b0}}) |
68                                   (stored_vector_d == {Cycles{1'b1}});
69                      
70         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T67 T68 T20 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup.u_prim_filter

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T67,T68,T20
0	1	Covered	T67,T68,T20
1	0	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T67,T68,T20
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T67,T68,T20

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup.u_prim_filter

	Line No.	Total	Covered	Percent
Branches		7	6	85.71
TERNARY	70	2	1	50.00
IF	48	3	3	100.00
IF	59	2	2	100.00

70           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

48             if (!rst_ni) begin
               -1-  
49               stored_value_q <= 1'b0;
                 ==>
50             end else if (update_stored_value) begin
                        -2-  
51               stored_value_q <= filter_synced;
                 ==>
52             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T67,T68,T20

59             if (!rst_ni) begin
               -1-  
60               stored_vector_q <= '0;
                 ==>
61             end else begin
62               stored_vector_q <= stored_vector_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup.u_prim_filter

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	48	4	4	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	3	3	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	70	1	1	100.00

47                        always_ff @(posedge clk_i or negedge rst_ni) begin
48         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
49         1/1                stored_value_q <= 1'b0;
           Tests:       T1 T2 T3 
50         1/1              end else if (update_stored_value) begin
           Tests:       T1 T2 T3 
51         1/1                stored_value_q <= filter_synced;
           Tests:       T1 T2 T3 
52                          end
                        MISSING_ELSE
53                        end
54                      
55         1/1            assign stored_vector_d = {stored_vector_q[Cycles-2:0],filter_synced};
           Tests:       T19 
56         1/1            assign unused_stored_vector_q_msb = stored_vector_q[Cycles-1];
           Tests:       T19 
57                      
58                        always_ff @(posedge clk_i or negedge rst_ni) begin
59         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
60         1/1                stored_vector_q <= '0;
           Tests:       T1 T2 T3 
61                          end else begin
62         1/1                stored_vector_q <= stored_vector_d;
           Tests:       T1 T2 T3 
63                          end
64                        end
65                      
66         1/1            assign update_stored_value =
           Tests:       T19 
67                                   (stored_vector_d == {Cycles{1'b0}}) |
68                                   (stored_vector_d == {Cycles{1'b1}});
69                      
70         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T19 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup.u_prim_filter

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T19
0	1	Covered	T19
1	0	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T19
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T19

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup.u_prim_filter

	Line No.	Total	Covered	Percent
Branches		7	6	85.71
TERNARY	70	2	1	50.00
IF	48	3	3	100.00
IF	59	2	2	100.00

70           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

48             if (!rst_ni) begin
               -1-  
49               stored_value_q <= 1'b0;
                 ==>
50             end else if (update_stored_value) begin
                        -2-  
51               stored_value_q <= filter_synced;
                 ==>
52             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T19

59             if (!rst_ni) begin
               -1-  
60               stored_vector_q <= '0;
                 ==>
61             end else begin
62               stored_vector_q <= stored_vector_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_activity

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	48	4	4	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	3	3	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	70	1	1	100.00

47                        always_ff @(posedge clk_i or negedge rst_ni) begin
48         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
49         1/1                stored_value_q <= 1'b0;
           Tests:       T1 T2 T3 
50         1/1              end else if (update_stored_value) begin
           Tests:       T1 T2 T3 
51         1/1                stored_value_q <= filter_synced;
           Tests:       T1 T2 T3 
52                          end
                        MISSING_ELSE
53                        end
54                      
55         1/1            assign stored_vector_d = {stored_vector_q[Cycles-2:0],filter_synced};
           Tests:       T1 T2 T3 
56         1/1            assign unused_stored_vector_q_msb = stored_vector_q[Cycles-1];
           Tests:       T1 T2 T3 
57                      
58                        always_ff @(posedge clk_i or negedge rst_ni) begin
59         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
60         1/1                stored_vector_q <= '0;
           Tests:       T1 T2 T3 
61                          end else begin
62         1/1                stored_vector_q <= stored_vector_d;
           Tests:       T1 T2 T3 
63                          end
64                        end
65                      
66         1/1            assign update_stored_value =
           Tests:       T1 T2 T3 
67                                   (stored_vector_d == {Cycles{1'b0}}) |
68                                   (stored_vector_d == {Cycles{1'b1}});
69                      
70         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_activity

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_activity

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	70	1	1	100.00
IF	48	3	3	100.00
IF	59	2	2	100.00

70           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==> (Unreachable)  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

48             if (!rst_ni) begin
               -1-  
49               stored_value_q <= 1'b0;
                 ==>
50             end else if (update_stored_value) begin
                        -2-  
51               stored_value_q <= filter_synced;
                 ==>
52             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

59             if (!rst_ni) begin
               -1-  
60               stored_vector_q <= '0;
                 ==>
61             end else begin
62               stored_vector_q <= stored_vector_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_bus_reset

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	48	4	4	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	3	3	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	70	1	1	100.00

47                        always_ff @(posedge clk_i or negedge rst_ni) begin
48         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
49         1/1                stored_value_q <= 1'b0;
           Tests:       T1 T2 T3 
50         1/1              end else if (update_stored_value) begin
           Tests:       T1 T2 T3 
51         1/1                stored_value_q <= filter_synced;
           Tests:       T1 T2 T3 
52                          end
                        MISSING_ELSE
53                        end
54                      
55         1/1            assign stored_vector_d = {stored_vector_q[Cycles-2:0],filter_synced};
           Tests:       T5 T6 T7 
56         1/1            assign unused_stored_vector_q_msb = stored_vector_q[Cycles-1];
           Tests:       T5 T6 T7 
57                      
58                        always_ff @(posedge clk_i or negedge rst_ni) begin
59         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
60         1/1                stored_vector_q <= '0;
           Tests:       T1 T2 T3 
61                          end else begin
62         1/1                stored_vector_q <= stored_vector_d;
           Tests:       T1 T2 T3 
63                          end
64                        end
65                      
66         1/1            assign update_stored_value =
           Tests:       T5 T6 T7 
67                                   (stored_vector_d == {Cycles{1'b0}}) |
68                                   (stored_vector_d == {Cycles{1'b1}});
69                      
70         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T5 T6 T7 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_bus_reset

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_bus_reset

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	70	1	1	100.00
IF	48	3	3	100.00
IF	59	2	2	100.00

70           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==> (Unreachable)  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

48             if (!rst_ni) begin
               -1-  
49               stored_value_q <= 1'b0;
                 ==>
50             end else if (update_stored_value) begin
                        -2-  
51               stored_value_q <= filter_synced;
                 ==>
52             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T5,T6,T7

59             if (!rst_ni) begin
               -1-  
60               stored_vector_q <= '0;
                 ==>
61             end else begin
62               stored_vector_q <= stored_vector_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_sense

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	48	4	4	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	3	3	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	70	1	1	100.00

47                        always_ff @(posedge clk_i or negedge rst_ni) begin
48         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
49         1/1                stored_value_q <= 1'b0;
           Tests:       T1 T2 T3 
50         1/1              end else if (update_stored_value) begin
           Tests:       T1 T2 T3 
51         1/1                stored_value_q <= filter_synced;
           Tests:       T1 T2 T3 
52                          end
                        MISSING_ELSE
53                        end
54                      
55         1/1            assign stored_vector_d = {stored_vector_q[Cycles-2:0],filter_synced};
           Tests:       T1 T2 T3 
56         1/1            assign unused_stored_vector_q_msb = stored_vector_q[Cycles-1];
           Tests:       T1 T2 T3 
57                      
58                        always_ff @(posedge clk_i or negedge rst_ni) begin
59         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
60         1/1                stored_vector_q <= '0;
           Tests:       T1 T2 T3 
61                          end else begin
62         1/1                stored_vector_q <= stored_vector_d;
           Tests:       T1 T2 T3 
63                          end
64                        end
65                      
66         1/1            assign update_stored_value =
           Tests:       T1 T2 T3 
67                                   (stored_vector_d == {Cycles{1'b0}}) |
68                                   (stored_vector_d == {Cycles{1'b1}});
69                      
70         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_sense

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_sense

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	70	1	1	100.00
IF	48	3	3	100.00
IF	59	2	2	100.00

70           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==> (Unreachable)  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

48             if (!rst_ni) begin
               -1-  
49               stored_value_q <= 1'b0;
                 ==>
50             end else if (update_stored_value) begin
                        -2-  
51               stored_value_q <= filter_synced;
                 ==>
52             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

59             if (!rst_ni) begin
               -1-  
60               stored_vector_q <= '0;
                 ==>
61             end else begin
62               stored_vector_q <= stored_vector_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup.u_prim_filter

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	48	4	4	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	3	3	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	70	1	1	100.00

47                        always_ff @(posedge clk_i or negedge rst_ni) begin
48         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
49         1/1                stored_value_q <= 1'b0;
           Tests:       T1 T2 T3 
50         1/1              end else if (update_stored_value) begin
           Tests:       T1 T2 T3 
51         1/1                stored_value_q <= filter_synced;
           Tests:       T1 T2 T3 
52                          end
                        MISSING_ELSE
53                        end
54                      
55         1/1            assign stored_vector_d = {stored_vector_q[Cycles-2:0],filter_synced};
           Tests:       T1 T22 T32 
56         1/1            assign unused_stored_vector_q_msb = stored_vector_q[Cycles-1];
           Tests:       T1 T22 T32 
57                      
58                        always_ff @(posedge clk_i or negedge rst_ni) begin
59         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
60         1/1                stored_vector_q <= '0;
           Tests:       T1 T2 T3 
61                          end else begin
62         1/1                stored_vector_q <= stored_vector_d;
           Tests:       T1 T2 T3 
63                          end
64                        end
65                      
66         1/1            assign update_stored_value =
           Tests:       T1 T22 T32 
67                                   (stored_vector_d == {Cycles{1'b0}}) |
68                                   (stored_vector_d == {Cycles{1'b1}});
69                      
70         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T1 T22 T32 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup.u_prim_filter

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T22,T32
0	1	Covered	T1,T22,T32
1	0	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T22,T32
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T22,T32

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T32

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup.u_prim_filter

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	70	2	2	100.00
IF	48	3	3	100.00
IF	59	2	2	100.00

70           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T32
0	Covered	T1,T2,T3

48             if (!rst_ni) begin
               -1-  
49               stored_value_q <= 1'b0;
                 ==>
50             end else if (update_stored_value) begin
                        -2-  
51               stored_value_q <= filter_synced;
                 ==>
52             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T22,T32

59             if (!rst_ni) begin
               -1-  
60               stored_vector_q <= '0;
                 ==>
61             end else begin
62               stored_vector_q <= stored_vector_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup.u_prim_filter

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	48	4	4	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	3	3	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	70	1	1	100.00

47                        always_ff @(posedge clk_i or negedge rst_ni) begin
48         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
49         1/1                stored_value_q <= 1'b0;
           Tests:       T1 T2 T3 
50         1/1              end else if (update_stored_value) begin
           Tests:       T1 T2 T3 
51         1/1                stored_value_q <= filter_synced;
           Tests:       T1 T2 T3 
52                          end
                        MISSING_ELSE
53                        end
54                      
55         1/1            assign stored_vector_d = {stored_vector_q[Cycles-2:0],filter_synced};
           Tests:       T32 T21 
56         1/1            assign unused_stored_vector_q_msb = stored_vector_q[Cycles-1];
           Tests:       T21 
57                      
58                        always_ff @(posedge clk_i or negedge rst_ni) begin
59         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
60         1/1                stored_vector_q <= '0;
           Tests:       T1 T2 T3 
61                          end else begin
62         1/1                stored_vector_q <= stored_vector_d;
           Tests:       T1 T2 T3 
63                          end
64                        end
65                      
66         1/1            assign update_stored_value =
           Tests:       T32 T21 
67                                   (stored_vector_d == {Cycles{1'b0}}) |
68                                   (stored_vector_d == {Cycles{1'b1}});
69                      
70         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T32 T21 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup.u_prim_filter

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T32,T21
0	1	Covered	T21
1	0	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T32,T21
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T32

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup.u_prim_filter

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	70	2	2	100.00
IF	48	3	3	100.00
IF	59	2	2	100.00

70           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T32
0	Covered	T1,T2,T3

48             if (!rst_ni) begin
               -1-  
49               stored_value_q <= 1'b0;
                 ==>
50             end else if (update_stored_value) begin
                        -2-  
51               stored_value_q <= filter_synced;
                 ==>
52             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T21

59             if (!rst_ni) begin
               -1-  
60               stored_vector_q <= '0;
                 ==>
61             end else begin
62               stored_vector_q <= stored_vector_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup.u_prim_filter

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	48	4	4	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	3	3	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	70	1	1	100.00

47                        always_ff @(posedge clk_i or negedge rst_ni) begin
48         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
49         1/1                stored_value_q <= 1'b0;
           Tests:       T1 T2 T3 
50         1/1              end else if (update_stored_value) begin
           Tests:       T1 T2 T3 
51         1/1                stored_value_q <= filter_synced;
           Tests:       T1 T2 T3 
52                          end
                        MISSING_ELSE
53                        end
54                      
55         1/1            assign stored_vector_d = {stored_vector_q[Cycles-2:0],filter_synced};
           Tests:       T32 
56         1/1            assign unused_stored_vector_q_msb = stored_vector_q[Cycles-1];
           Tests:       T32 
57                      
58                        always_ff @(posedge clk_i or negedge rst_ni) begin
59         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
60         1/1                stored_vector_q <= '0;
           Tests:       T1 T2 T3 
61                          end else begin
62         1/1                stored_vector_q <= stored_vector_d;
           Tests:       T1 T2 T3 
63                          end
64                        end
65                      
66         1/1            assign update_stored_value =
           Tests:       T32 
67                                   (stored_vector_d == {Cycles{1'b0}}) |
68                                   (stored_vector_d == {Cycles{1'b1}});
69                      
70         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T32 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup.u_prim_filter

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T32
0	1	Covered	T32
1	0	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T32
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T32

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T32

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup.u_prim_filter

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	70	2	2	100.00
IF	48	3	3	100.00
IF	59	2	2	100.00

70           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T32
0	Covered	T1,T2,T3

48             if (!rst_ni) begin
               -1-  
49               stored_value_q <= 1'b0;
                 ==>
50             end else if (update_stored_value) begin
                        -2-  
51               stored_value_q <= filter_synced;
                 ==>
52             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T32

59             if (!rst_ni) begin
               -1-  
60               stored_vector_q <= '0;
                 ==>
61             end else begin
62               stored_vector_q <= stored_vector_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3