Unified Coverage Report :: Module :: pinmux_jtag_breakout

Module : pinmux_jtag_breakout

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00		100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_jtag_breakout.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_dft_tap_breakout	100.00	100.00		100.00

---

Module Instance : tb.dut.top_earlgrey.u_dft_tap_breakout

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00		100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00		100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pinmux_jtag_breakout

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	17	1	1	100.00
CONT_ASSIGN	18	1	1	100.00
CONT_ASSIGN	19	1	1	100.00
CONT_ASSIGN	20	1	1	100.00
CONT_ASSIGN	21	0	0
CONT_ASSIGN	22	0	0

16                      
17         1/1            assign tck_o        = req_i.tck;
           Tests:       T81 T82 T83 
18         1/1            assign trst_no      = req_i.trst_n;
           Tests:       T81 T82 T83 
19         1/1            assign tms_o        = req_i.tms;
           Tests:       T81 T82 T83 
20         1/1            assign tdi_o        = req_i.tdi;
           Tests:       T81 T82 T83 
21         unreachable    assign rsp_o.tdo    = tdo_i;
22         unreachable    assign rsp_o.tdo_oe = tdo_oe_i;

---

Toggle Coverage for Module : pinmux_jtag_breakout

	Total	Covered	Percent
Totals	10	10	100.00
Total Bits	20	20	100.00
Total Bits 0->1	10	10	100.00
Total Bits 1->0	10	10	100.00

Ports	10	10	100.00
Port Bits	20	20	100.00
Port Bits 0->1	10	10	100.00
Port Bits 1->0	10	10	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
req_i.tdi	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
req_i.trst_n	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
req_i.tms	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
req_i.tck	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
rsp_o.tdo_oe	Yes	Yes	T81,T84,T77	Yes	T81,T84,T77	OUTPUT
rsp_o.tdo	Yes	Yes	T81,T84,T77	Yes	T81,T84,T77	OUTPUT
tck_o	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
trst_no	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tms_o	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tdi_o	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tdo_i	Unreachable	Unreachable		Unreachable		INPUT
tdo_oe_i	Unreachable	Unreachable		Unreachable		INPUT