Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	414974052	45539118	0	0
DepthKnown_A	414974052	414893250	0	0
RvalidKnown_A	414974052	414893250	0	0
WreadyKnown_A	414974052	414893250	0	0
gen_passthru_fifo.paramCheckPass	777	777	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414974052	45539118	0	0
T1	103166	13363	0	0
T2	68779	8344	0	0
T3	212795	28778	0	0
T4	180992	14337	0	0
T11	130451	13584	0	0
T22	115208	13833	0	0
T24	219043	22275	0	0
T31	97041	8680	0	0
T39	225028	22193	0	0
T97	78718	8019	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414974052	414893250	0	0
T1	103166	103111	0	0
T2	68779	68728	0	0
T3	212795	212744	0	0
T4	180992	180930	0	0
T11	130451	130396	0	0
T22	115208	115153	0	0
T24	219043	218988	0	0
T31	97041	96935	0	0
T39	225028	224911	0	0
T97	78718	78656	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414974052	414893250	0	0
T1	103166	103111	0	0
T2	68779	68728	0	0
T3	212795	212744	0	0
T4	180992	180930	0	0
T11	130451	130396	0	0
T22	115208	115153	0	0
T24	219043	218988	0	0
T31	97041	96935	0	0
T39	225028	224911	0	0
T97	78718	78656	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414974052	414893250	0	0
T1	103166	103111	0	0
T2	68779	68728	0	0
T3	212795	212744	0	0
T4	180992	180930	0	0
T11	130451	130396	0	0
T22	115208	115153	0	0
T24	219043	218988	0	0
T31	97041	96935	0	0
T39	225028	224911	0	0
T97	78718	78656	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	777	777	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T22	1	1	0	0
T24	1	1	0	0
T31	1	1	0	0
T39	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         0/1     ==>      assign wready_o = rready_i;
49         0/1     ==>      assign full_o = rready_i;
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	414974052	36006640	0	0
DepthKnown_A	414974052	414893250	0	0
RvalidKnown_A	414974052	414893250	0	0
WreadyKnown_A	414974052	414893250	0	0
gen_passthru_fifo.paramCheckPass	777	777	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414974052	36006640	0	0
T1	103166	9329	0	0
T2	68779	5671	0	0
T3	212795	18984	0	0
T4	180992	10739	0	0
T11	130451	9638	0	0
T22	115208	9490	0	0
T24	219043	18299	0	0
T31	97041	6959	0	0
T39	225028	15221	0	0
T97	78718	6352	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414974052	414893250	0	0
T1	103166	103111	0	0
T2	68779	68728	0	0
T3	212795	212744	0	0
T4	180992	180930	0	0
T11	130451	130396	0	0
T22	115208	115153	0	0
T24	219043	218988	0	0
T31	97041	96935	0	0
T39	225028	224911	0	0
T97	78718	78656	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414974052	414893250	0	0
T1	103166	103111	0	0
T2	68779	68728	0	0
T3	212795	212744	0	0
T4	180992	180930	0	0
T11	130451	130396	0	0
T22	115208	115153	0	0
T24	219043	218988	0	0
T31	97041	96935	0	0
T39	225028	224911	0	0
T97	78718	78656	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414974052	414893250	0	0
T1	103166	103111	0	0
T2	68779	68728	0	0
T3	212795	212744	0	0
T4	180992	180930	0	0
T11	130451	130396	0	0
T22	115208	115153	0	0
T24	219043	218988	0	0
T31	97041	96935	0	0
T39	225028	224911	0	0
T97	78718	78656	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	777	777	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T22	1	1	0	0
T24	1	1	0	0
T31	1	1	0	0
T39	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	414974052	31473907	0	0
DepthKnown_A	414974052	414893250	0	0
RvalidKnown_A	414974052	414893250	0	0
WreadyKnown_A	414974052	414893250	0	0
gen_passthru_fifo.paramCheckPass	777	777	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414974052	31473907	0	0
T1	103166	6313	0	0
T2	68779	5144	0	0
T3	212795	12662	0	0
T4	180992	12397	0	0
T11	130451	10469	0	0
T22	115208	7863	0	0
T24	219043	20820	0	0
T31	97041	5412	0	0
T39	225028	10251	0	0
T97	78718	4985	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414974052	414893250	0	0
T1	103166	103111	0	0
T2	68779	68728	0	0
T3	212795	212744	0	0
T4	180992	180930	0	0
T11	130451	130396	0	0
T22	115208	115153	0	0
T24	219043	218988	0	0
T31	97041	96935	0	0
T39	225028	224911	0	0
T97	78718	78656	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414974052	414893250	0	0
T1	103166	103111	0	0
T2	68779	68728	0	0
T3	212795	212744	0	0
T4	180992	180930	0	0
T11	130451	130396	0	0
T22	115208	115153	0	0
T24	219043	218988	0	0
T31	97041	96935	0	0
T39	225028	224911	0	0
T97	78718	78656	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414974052	414893250	0	0
T1	103166	103111	0	0
T2	68779	68728	0	0
T3	212795	212744	0	0
T4	180992	180930	0	0
T11	130451	130396	0	0
T22	115208	115153	0	0
T24	219043	218988	0	0
T31	97041	96935	0	0
T39	225028	224911	0	0
T97	78718	78656	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	777	777	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T22	1	1	0	0
T24	1	1	0	0
T31	1	1	0	0
T39	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T32 T80 T52 
49         1/1              assign full_o = rready_i;
           Tests:       T32 T80 T52 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	414974052	28058280	0	0
DepthKnown_A	414974052	414893250	0	0
RvalidKnown_A	414974052	414893250	0	0
WreadyKnown_A	414974052	414893250	0	0
gen_passthru_fifo.paramCheckPass	777	777	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414974052	28058280	0	0
T1	103166	6073	0	0
T2	68779	4962	0	0
T3	212795	12369	0	0
T4	180992	12177	0	0
T11	130451	10193	0	0
T22	115208	7454	0	0
T24	219043	20615	0	0
T31	97041	5293	0	0
T39	225028	9891	0	0
T97	78718	4871	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414974052	414893250	0	0
T1	103166	103111	0	0
T2	68779	68728	0	0
T3	212795	212744	0	0
T4	180992	180930	0	0
T11	130451	130396	0	0
T22	115208	115153	0	0
T24	219043	218988	0	0
T31	97041	96935	0	0
T39	225028	224911	0	0
T97	78718	78656	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414974052	414893250	0	0
T1	103166	103111	0	0
T2	68779	68728	0	0
T3	212795	212744	0	0
T4	180992	180930	0	0
T11	130451	130396	0	0
T22	115208	115153	0	0
T24	219043	218988	0	0
T31	97041	96935	0	0
T39	225028	224911	0	0
T97	78718	78656	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414974052	414893250	0	0
T1	103166	103111	0	0
T2	68779	68728	0	0
T3	212795	212744	0	0
T4	180992	180930	0	0
T11	130451	130396	0	0
T22	115208	115153	0	0
T24	219043	218988	0	0
T31	97041	96935	0	0
T39	225028	224911	0	0
T97	78718	78656	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	777	777	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T22	1	1	0	0
T24	1	1	0	0
T31	1	1	0	0
T39	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	500615052	87219	0	0
DepthKnown_A	500615052	500518157	0	0
RvalidKnown_A	500615052	500518157	0	0
WreadyKnown_A	500615052	500518157	0	0
gen_passthru_fifo.paramCheckPass	2688	2688	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500615052	87219	0	0
T1	103166	25	0	0
T2	68779	24	0	0
T3	212795	12	0	0
T4	180992	17	0	0
T11	130451	94	0	0
T22	115208	53	0	0
T24	219043	53	0	0
T31	97041	13	0	0
T39	225028	103	0	0
T97	78718	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500615052	500518157	0	0
T1	103166	103111	0	0
T2	68779	68728	0	0
T3	212795	212744	0	0
T4	180992	180930	0	0
T11	130451	130396	0	0
T22	115208	115153	0	0
T24	219043	218988	0	0
T31	97041	96935	0	0
T39	225028	224911	0	0
T97	78718	78656	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500615052	500518157	0	0
T1	103166	103111	0	0
T2	68779	68728	0	0
T3	212795	212744	0	0
T4	180992	180930	0	0
T11	130451	130396	0	0
T22	115208	115153	0	0
T24	219043	218988	0	0
T31	97041	96935	0	0
T39	225028	224911	0	0
T97	78718	78656	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500615052	500518157	0	0
T1	103166	103111	0	0
T2	68779	68728	0	0
T3	212795	212744	0	0
T4	180992	180930	0	0
T11	130451	130396	0	0
T22	115208	115153	0	0
T24	219043	218988	0	0
T31	97041	96935	0	0
T39	225028	224911	0	0
T97	78718	78656	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2688	2688	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T22	1	1	0	0
T24	1	1	0	0
T31	1	1	0	0
T39	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	500615052	87951	0	0
DepthKnown_A	500615052	500518157	0	0
RvalidKnown_A	500615052	500518157	0	0
WreadyKnown_A	500615052	500518157	0	0
gen_passthru_fifo.paramCheckPass	2688	2688	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500615052	87951	0	0
T1	103166	25	0	0
T2	68779	24	0	0
T3	212795	12	0	0
T4	180992	17	0	0
T11	130451	94	0	0
T22	115208	53	0	0
T24	219043	53	0	0
T31	97041	13	0	0
T39	225028	103	0	0
T97	78718	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500615052	500518157	0	0
T1	103166	103111	0	0
T2	68779	68728	0	0
T3	212795	212744	0	0
T4	180992	180930	0	0
T11	130451	130396	0	0
T22	115208	115153	0	0
T24	219043	218988	0	0
T31	97041	96935	0	0
T39	225028	224911	0	0
T97	78718	78656	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500615052	500518157	0	0
T1	103166	103111	0	0
T2	68779	68728	0	0
T3	212795	212744	0	0
T4	180992	180930	0	0
T11	130451	130396	0	0
T22	115208	115153	0	0
T24	219043	218988	0	0
T31	97041	96935	0	0
T39	225028	224911	0	0
T97	78718	78656	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500615052	500518157	0	0
T1	103166	103111	0	0
T2	68779	68728	0	0
T3	212795	212744	0	0
T4	180992	180930	0	0
T11	130451	130396	0	0
T22	115208	115153	0	0
T24	219043	218988	0	0
T31	97041	96935	0	0
T39	225028	224911	0	0
T97	78718	78656	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2688	2688	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T22	1	1	0	0
T24	1	1	0	0
T31	1	1	0	0
T39	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	500615052	41687	0	0
DepthKnown_A	500615052	500518157	0	0
RvalidKnown_A	500615052	500518157	0	0
WreadyKnown_A	500615052	500518157	0	0
gen_passthru_fifo.paramCheckPass	2688	2688	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500615052	41687	0	0
T1	103166	22	0	0
T2	68779	23	0	0
T3	212795	11	0	0
T4	180992	14	0	0
T11	130451	93	0	0
T22	115208	50	0	0
T24	219043	52	0	0
T31	97041	12	0	0
T39	225028	95	0	0
T97	78718	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500615052	500518157	0	0
T1	103166	103111	0	0
T2	68779	68728	0	0
T3	212795	212744	0	0
T4	180992	180930	0	0
T11	130451	130396	0	0
T22	115208	115153	0	0
T24	219043	218988	0	0
T31	97041	96935	0	0
T39	225028	224911	0	0
T97	78718	78656	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500615052	500518157	0	0
T1	103166	103111	0	0
T2	68779	68728	0	0
T3	212795	212744	0	0
T4	180992	180930	0	0
T11	130451	130396	0	0
T22	115208	115153	0	0
T24	219043	218988	0	0
T31	97041	96935	0	0
T39	225028	224911	0	0
T97	78718	78656	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500615052	500518157	0	0
T1	103166	103111	0	0
T2	68779	68728	0	0
T3	212795	212744	0	0
T4	180992	180930	0	0
T11	130451	130396	0	0
T22	115208	115153	0	0
T24	219043	218988	0	0
T31	97041	96935	0	0
T39	225028	224911	0	0
T97	78718	78656	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2688	2688	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T22	1	1	0	0
T24	1	1	0	0
T31	1	1	0	0
T39	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	500615052	41687	0	0
DepthKnown_A	500615052	500518157	0	0
RvalidKnown_A	500615052	500518157	0	0
WreadyKnown_A	500615052	500518157	0	0
gen_passthru_fifo.paramCheckPass	2688	2688	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500615052	41687	0	0
T1	103166	22	0	0
T2	68779	23	0	0
T3	212795	11	0	0
T4	180992	14	0	0
T11	130451	93	0	0
T22	115208	50	0	0
T24	219043	52	0	0
T31	97041	12	0	0
T39	225028	95	0	0
T97	78718	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500615052	500518157	0	0
T1	103166	103111	0	0
T2	68779	68728	0	0
T3	212795	212744	0	0
T4	180992	180930	0	0
T11	130451	130396	0	0
T22	115208	115153	0	0
T24	219043	218988	0	0
T31	97041	96935	0	0
T39	225028	224911	0	0
T97	78718	78656	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500615052	500518157	0	0
T1	103166	103111	0	0
T2	68779	68728	0	0
T3	212795	212744	0	0
T4	180992	180930	0	0
T11	130451	130396	0	0
T22	115208	115153	0	0
T24	219043	218988	0	0
T31	97041	96935	0	0
T39	225028	224911	0	0
T97	78718	78656	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500615052	500518157	0	0
T1	103166	103111	0	0
T2	68779	68728	0	0
T3	212795	212744	0	0
T4	180992	180930	0	0
T11	130451	130396	0	0
T22	115208	115153	0	0
T24	219043	218988	0	0
T31	97041	96935	0	0
T39	225028	224911	0	0
T97	78718	78656	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2688	2688	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T22	1	1	0	0
T24	1	1	0	0
T31	1	1	0	0
T39	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	500615052	45532	0	0
DepthKnown_A	500615052	500518157	0	0
RvalidKnown_A	500615052	500518157	0	0
WreadyKnown_A	500615052	500518157	0	0
gen_passthru_fifo.paramCheckPass	2688	2688	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500615052	45532	0	0
T1	103166	3	0	0
T2	68779	1	0	0
T3	212795	1	0	0
T4	180992	3	0	0
T11	130451	1	0	0
T22	115208	3	0	0
T24	219043	1	0	0
T31	97041	1	0	0
T39	225028	8	0	0
T97	78718	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500615052	500518157	0	0
T1	103166	103111	0	0
T2	68779	68728	0	0
T3	212795	212744	0	0
T4	180992	180930	0	0
T11	130451	130396	0	0
T22	115208	115153	0	0
T24	219043	218988	0	0
T31	97041	96935	0	0
T39	225028	224911	0	0
T97	78718	78656	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500615052	500518157	0	0
T1	103166	103111	0	0
T2	68779	68728	0	0
T3	212795	212744	0	0
T4	180992	180930	0	0
T11	130451	130396	0	0
T22	115208	115153	0	0
T24	219043	218988	0	0
T31	97041	96935	0	0
T39	225028	224911	0	0
T97	78718	78656	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500615052	500518157	0	0
T1	103166	103111	0	0
T2	68779	68728	0	0
T3	212795	212744	0	0
T4	180992	180930	0	0
T11	130451	130396	0	0
T22	115208	115153	0	0
T24	219043	218988	0	0
T31	97041	96935	0	0
T39	225028	224911	0	0
T97	78718	78656	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2688	2688	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T22	1	1	0	0
T24	1	1	0	0
T31	1	1	0	0
T39	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	500615052	46264	0	0
DepthKnown_A	500615052	500518157	0	0
RvalidKnown_A	500615052	500518157	0	0
WreadyKnown_A	500615052	500518157	0	0
gen_passthru_fifo.paramCheckPass	2688	2688	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500615052	46264	0	0
T1	103166	3	0	0
T2	68779	1	0	0
T3	212795	1	0	0
T4	180992	3	0	0
T11	130451	1	0	0
T22	115208	3	0	0
T24	219043	1	0	0
T31	97041	1	0	0
T39	225028	8	0	0
T97	78718	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500615052	500518157	0	0
T1	103166	103111	0	0
T2	68779	68728	0	0
T3	212795	212744	0	0
T4	180992	180930	0	0
T11	130451	130396	0	0
T22	115208	115153	0	0
T24	219043	218988	0	0
T31	97041	96935	0	0
T39	225028	224911	0	0
T97	78718	78656	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500615052	500518157	0	0
T1	103166	103111	0	0
T2	68779	68728	0	0
T3	212795	212744	0	0
T4	180992	180930	0	0
T11	130451	130396	0	0
T22	115208	115153	0	0
T24	219043	218988	0	0
T31	97041	96935	0	0
T39	225028	224911	0	0
T97	78718	78656	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500615052	500518157	0	0
T1	103166	103111	0	0
T2	68779	68728	0	0
T3	212795	212744	0	0
T4	180992	180930	0	0
T11	130451	130396	0	0
T22	115208	115153	0	0
T24	219043	218988	0	0
T31	97041	96935	0	0
T39	225028	224911	0	0
T97	78718	78656	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2688	2688	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T22	1	1	0	0
T24	1	1	0	0
T31	1	1	0	0
T39	1	1	0	0
T97	1	1	0	0