Unified Coverage Report :: Module :: sensor_ctrl_reg_top

Module : sensor_ctrl_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.41	100.00	69.65			100.00	100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_systems_sensor_ctrl_reg_0.1/rtl/sensor_ctrl_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg	92.41	100.00	69.65			100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.41	100.00	69.65			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.72	90.70	82.88			93.29	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.38	93.69	89.00	79.23		100.00	100.00	u_sensor_ctrl_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_en_0	100.00	100.00	100.00			100.00
u_alert_en_1	100.00	100.00	100.00			100.00
u_alert_en_10	100.00	100.00	100.00			100.00
u_alert_en_2	100.00	100.00	100.00			100.00
u_alert_en_3	100.00	100.00	100.00			100.00
u_alert_en_4	100.00	100.00	100.00			100.00
u_alert_en_5	100.00	100.00	100.00			100.00
u_alert_en_6	100.00	100.00	100.00			100.00
u_alert_en_7	100.00	100.00	100.00			100.00
u_alert_en_8	100.00	100.00	100.00			100.00
u_alert_en_9	100.00	100.00	100.00			100.00
u_alert_test_fatal_alert	100.00	100.00
u_alert_test_recov_alert	100.00	100.00
u_alert_trig_val_0	100.00	100.00	100.00			100.00
u_alert_trig_val_1	100.00	100.00	100.00			100.00
u_alert_trig_val_10	100.00	100.00	100.00			100.00
u_alert_trig_val_2	100.00	100.00	100.00			100.00
u_alert_trig_val_3	100.00	100.00	100.00			100.00
u_alert_trig_val_4	100.00	100.00	100.00			100.00
u_alert_trig_val_5	100.00	100.00	100.00			100.00
u_alert_trig_val_6	100.00	100.00	100.00			100.00
u_alert_trig_val_7	100.00	100.00	100.00			100.00
u_alert_trig_val_8	100.00	100.00	100.00			100.00
u_alert_trig_val_9	100.00	100.00	100.00			100.00
u_cfg_regwen	51.48	44.44	50.00			60.00
u_chk	100.00	100.00					100.00
u_fatal_alert_en_val_0	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_1	96.30	88.89	100.00			100.00
u_fatal_alert_en_val_10	96.30	88.89	100.00			100.00
u_fatal_alert_en_val_2	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_3	96.30	88.89	100.00			100.00
u_fatal_alert_en_val_4	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_5	96.30	88.89	100.00			100.00
u_fatal_alert_en_val_6	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_7	96.30	88.89	100.00			100.00
u_fatal_alert_en_val_8	96.30	88.89	100.00			100.00
u_fatal_alert_en_val_9	96.30	88.89	100.00			100.00
u_fatal_alert_val_0	96.30	88.89	100.00			100.00
u_fatal_alert_val_1	47.78	33.33	50.00			60.00
u_fatal_alert_val_10	47.78	33.33	50.00			60.00
u_fatal_alert_val_11	96.30	88.89	100.00			100.00
u_fatal_alert_val_2	96.30	88.89	100.00			100.00
u_fatal_alert_val_3	47.78	33.33	50.00			60.00
u_fatal_alert_val_4	96.30	88.89	100.00			100.00
u_fatal_alert_val_5	47.78	33.33	50.00			60.00
u_fatal_alert_val_6	96.30	88.89	100.00			100.00
u_fatal_alert_val_7	47.78	33.33	50.00			60.00
u_fatal_alert_val_8	47.78	33.33	50.00			60.00
u_fatal_alert_val_9	47.78	33.33	50.00			60.00
u_intr_enable_init_status_change	100.00	100.00	100.00			100.00
u_intr_enable_io_status_change	100.00	100.00	100.00			100.00
u_intr_state_init_status_change	100.00	100.00	100.00			100.00
u_intr_state_io_status_change	100.00	100.00	100.00			100.00
u_intr_test_init_status_change	100.00	100.00
u_intr_test_io_status_change	100.00	100.00
u_manual_pad_attr_0_input_disable_0	80.00	80.00
u_manual_pad_attr_0_pull_en_0	80.00	80.00
u_manual_pad_attr_0_pull_select_0	80.00	80.00
u_manual_pad_attr_1_input_disable_1	80.00	80.00
u_manual_pad_attr_1_pull_en_1	80.00	80.00
u_manual_pad_attr_1_pull_select_1	80.00	80.00
u_manual_pad_attr_2_input_disable_2	80.00	80.00
u_manual_pad_attr_2_pull_en_2	80.00	80.00
u_manual_pad_attr_2_pull_select_2	80.00	80.00
u_manual_pad_attr_3_input_disable_3	80.00	80.00
u_manual_pad_attr_3_pull_en_3	80.00	80.00
u_manual_pad_attr_3_pull_select_3	80.00	80.00
u_manual_pad_attr_regwen_0	51.48	44.44	50.00			60.00
u_manual_pad_attr_regwen_1	51.48	44.44	50.00			60.00
u_manual_pad_attr_regwen_2	51.48	44.44	50.00			60.00
u_manual_pad_attr_regwen_3	51.48	44.44	50.00			60.00
u_prim_reg_we_check	100.00	100.00
u_recov_alert_val_0	100.00	100.00	100.00			100.00
u_recov_alert_val_1	100.00	100.00	100.00			100.00
u_recov_alert_val_10	100.00	100.00	100.00			100.00
u_recov_alert_val_2	100.00	100.00	100.00			100.00
u_recov_alert_val_3	100.00	100.00	100.00			100.00
u_recov_alert_val_4	100.00	100.00	100.00			100.00
u_recov_alert_val_5	100.00	100.00	100.00			100.00
u_recov_alert_val_6	100.00	100.00	100.00			100.00
u_recov_alert_val_7	100.00	100.00	100.00			100.00
u_recov_alert_val_8	100.00	100.00	100.00			100.00
u_recov_alert_val_9	100.00	100.00	100.00			100.00
u_reg_if	89.30	94.29	76.54			86.36	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_status_ast_init_done	62.59	77.78	50.00			60.00
u_status_io_pok	62.59	77.78	50.00			60.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : sensor_ctrl_reg_top

	Line No.	Total	Covered	Percent
TOTAL		296	296	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	435	1	1	100.00
CONT_ASSIGN	451	1	1	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	472	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	823	1	1	100.00
CONT_ASSIGN	855	1	1	100.00
CONT_ASSIGN	887	1	1	100.00
CONT_ASSIGN	919	1	1	100.00
CONT_ASSIGN	951	1	1	100.00
CONT_ASSIGN	983	1	1	100.00
CONT_ASSIGN	1015	1	1	100.00
CONT_ASSIGN	1047	1	1	100.00
CONT_ASSIGN	1079	1	1	100.00
CONT_ASSIGN	1111	1	1	100.00
CONT_ASSIGN	1143	1	1	100.00
CONT_ASSIGN	1175	1	1	100.00
CONT_ASSIGN	2277	1	1	100.00
CONT_ASSIGN	2280	1	1	100.00
CONT_ASSIGN	2295	1	1	100.00
CONT_ASSIGN	2311	1	1	100.00
CONT_ASSIGN	2327	1	1	100.00
CONT_ASSIGN	2334	1	1	100.00
CONT_ASSIGN	2337	1	1	100.00
CONT_ASSIGN	2352	1	1	100.00
CONT_ASSIGN	2368	1	1	100.00
CONT_ASSIGN	2384	1	1	100.00
CONT_ASSIGN	2391	1	1	100.00
CONT_ASSIGN	2394	1	1	100.00
CONT_ASSIGN	2409	1	1	100.00
CONT_ASSIGN	2425	1	1	100.00
CONT_ASSIGN	2441	1	1	100.00
CONT_ASSIGN	2448	1	1	100.00
CONT_ASSIGN	2451	1	1	100.00
CONT_ASSIGN	2466	1	1	100.00
CONT_ASSIGN	2482	1	1	100.00
CONT_ASSIGN	2498	1	1	100.00
ALWAYS	2504	30	30	100.00
CONT_ASSIGN	2536	1	1	100.00
ALWAYS	2540	1	1	100.00
CONT_ASSIGN	2573	1	1	100.00
CONT_ASSIGN	2575	1	1	100.00
CONT_ASSIGN	2577	1	1	100.00
CONT_ASSIGN	2578	1	1	100.00
CONT_ASSIGN	2580	1	1	100.00
CONT_ASSIGN	2582	1	1	100.00
CONT_ASSIGN	2583	1	1	100.00
CONT_ASSIGN	2585	1	1	100.00
CONT_ASSIGN	2587	1	1	100.00
CONT_ASSIGN	2588	1	1	100.00
CONT_ASSIGN	2590	1	1	100.00
CONT_ASSIGN	2592	1	1	100.00
CONT_ASSIGN	2593	1	1	100.00
CONT_ASSIGN	2595	1	1	100.00
CONT_ASSIGN	2596	1	1	100.00
CONT_ASSIGN	2598	1	1	100.00
CONT_ASSIGN	2600	1	1	100.00
CONT_ASSIGN	2602	1	1	100.00
CONT_ASSIGN	2604	1	1	100.00
CONT_ASSIGN	2606	1	1	100.00
CONT_ASSIGN	2608	1	1	100.00
CONT_ASSIGN	2610	1	1	100.00
CONT_ASSIGN	2612	1	1	100.00
CONT_ASSIGN	2614	1	1	100.00
CONT_ASSIGN	2616	1	1	100.00
CONT_ASSIGN	2618	1	1	100.00
CONT_ASSIGN	2619	1	1	100.00
CONT_ASSIGN	2621	1	1	100.00
CONT_ASSIGN	2622	1	1	100.00
CONT_ASSIGN	2624	1	1	100.00
CONT_ASSIGN	2625	1	1	100.00
CONT_ASSIGN	2627	1	1	100.00
CONT_ASSIGN	2628	1	1	100.00
CONT_ASSIGN	2630	1	1	100.00
CONT_ASSIGN	2631	1	1	100.00
CONT_ASSIGN	2633	1	1	100.00
CONT_ASSIGN	2634	1	1	100.00
CONT_ASSIGN	2636	1	1	100.00
CONT_ASSIGN	2637	1	1	100.00
CONT_ASSIGN	2639	1	1	100.00
CONT_ASSIGN	2640	1	1	100.00
CONT_ASSIGN	2642	1	1	100.00
CONT_ASSIGN	2643	1	1	100.00
CONT_ASSIGN	2645	1	1	100.00
CONT_ASSIGN	2646	1	1	100.00
CONT_ASSIGN	2648	1	1	100.00
CONT_ASSIGN	2649	1	1	100.00
CONT_ASSIGN	2651	1	1	100.00
CONT_ASSIGN	2652	1	1	100.00
CONT_ASSIGN	2654	1	1	100.00
CONT_ASSIGN	2656	1	1	100.00
CONT_ASSIGN	2658	1	1	100.00
CONT_ASSIGN	2660	1	1	100.00
CONT_ASSIGN	2662	1	1	100.00
CONT_ASSIGN	2664	1	1	100.00
CONT_ASSIGN	2666	1	1	100.00
CONT_ASSIGN	2668	1	1	100.00
CONT_ASSIGN	2670	1	1	100.00
CONT_ASSIGN	2672	1	1	100.00
CONT_ASSIGN	2674	1	1	100.00
CONT_ASSIGN	2675	1	1	100.00
CONT_ASSIGN	2677	1	1	100.00
CONT_ASSIGN	2679	1	1	100.00
CONT_ASSIGN	2681	1	1	100.00
CONT_ASSIGN	2683	1	1	100.00
CONT_ASSIGN	2685	1	1	100.00
CONT_ASSIGN	2687	1	1	100.00
CONT_ASSIGN	2689	1	1	100.00
CONT_ASSIGN	2691	1	1	100.00
CONT_ASSIGN	2693	1	1	100.00
CONT_ASSIGN	2695	1	1	100.00
CONT_ASSIGN	2697	1	1	100.00
CONT_ASSIGN	2698	1	1	100.00
CONT_ASSIGN	2700	1	1	100.00
CONT_ASSIGN	2701	1	1	100.00
CONT_ASSIGN	2703	1	1	100.00
CONT_ASSIGN	2704	1	1	100.00
CONT_ASSIGN	2706	1	1	100.00
CONT_ASSIGN	2707	1	1	100.00
CONT_ASSIGN	2709	1	1	100.00
CONT_ASSIGN	2710	1	1	100.00
CONT_ASSIGN	2711	1	1	100.00
CONT_ASSIGN	2713	1	1	100.00
CONT_ASSIGN	2715	1	1	100.00
CONT_ASSIGN	2717	1	1	100.00
CONT_ASSIGN	2718	1	1	100.00
CONT_ASSIGN	2719	1	1	100.00
CONT_ASSIGN	2721	1	1	100.00
CONT_ASSIGN	2723	1	1	100.00
CONT_ASSIGN	2725	1	1	100.00
CONT_ASSIGN	2726	1	1	100.00
CONT_ASSIGN	2727	1	1	100.00
CONT_ASSIGN	2729	1	1	100.00
CONT_ASSIGN	2731	1	1	100.00
CONT_ASSIGN	2733	1	1	100.00
CONT_ASSIGN	2734	1	1	100.00
CONT_ASSIGN	2735	1	1	100.00
CONT_ASSIGN	2737	1	1	100.00
CONT_ASSIGN	2739	1	1	100.00
CONT_ASSIGN	2741	1	1	100.00
ALWAYS	2745	30	30	100.00
ALWAYS	2779	85	85	100.00
CONT_ASSIGN	2962	0	0
CONT_ASSIGN	2970	1	1	100.00
CONT_ASSIGN	2971	1	1	100.00

Click here to see the source line report.

---

Cond Coverage for Module : sensor_ctrl_reg_top

	Total	Covered	Percent
Conditions	369	257	69.65
Logical	369	257	69.65
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
58-2704	70.57
2707-2735	61.11

---

Branch Coverage for Module : sensor_ctrl_reg_top

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	2536	2	2	100.00
IF	68	3	3	100.00
CASE	2780	30	30	100.00

2536         assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

68             if (!rst_ni) begin
               -1-  
69               err_q <= '0;
                 ==>
70             end else if (intg_err || reg_we_err) begin
                        -2-  
71               err_q <= 1'b1;
                 ==>
72             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T104,T360,T361
0	0	Covered	T1,T2,T3

2780           unique case (1'b1)
                      -1-  
2781             addr_hit[0]: begin
2782               reg_rdata_next[0] = intr_state_io_status_change_qs;
                   ==>
2783               reg_rdata_next[1] = intr_state_init_status_change_qs;
2784             end
2785       
2786             addr_hit[1]: begin
2787               reg_rdata_next[0] = intr_enable_io_status_change_qs;
                   ==>
2788               reg_rdata_next[1] = intr_enable_init_status_change_qs;
2789             end
2790       
2791             addr_hit[2]: begin
2792               reg_rdata_next[0] = '0;
                   ==>
2793               reg_rdata_next[1] = '0;
2794             end
2795       
2796             addr_hit[3]: begin
2797               reg_rdata_next[0] = '0;
                   ==>
2798               reg_rdata_next[1] = '0;
2799             end
2800       
2801             addr_hit[4]: begin
2802               reg_rdata_next[0] = cfg_regwen_qs;
                   ==>
2803             end
2804       
2805             addr_hit[5]: begin
2806               reg_rdata_next[0] = alert_trig_val_0_qs;
                   ==>
2807               reg_rdata_next[1] = alert_trig_val_1_qs;
2808               reg_rdata_next[2] = alert_trig_val_2_qs;
2809               reg_rdata_next[3] = alert_trig_val_3_qs;
2810               reg_rdata_next[4] = alert_trig_val_4_qs;
2811               reg_rdata_next[5] = alert_trig_val_5_qs;
2812               reg_rdata_next[6] = alert_trig_val_6_qs;
2813               reg_rdata_next[7] = alert_trig_val_7_qs;
2814               reg_rdata_next[8] = alert_trig_val_8_qs;
2815               reg_rdata_next[9] = alert_trig_val_9_qs;
2816               reg_rdata_next[10] = alert_trig_val_10_qs;
2817             end
2818       
2819             addr_hit[6]: begin
2820               reg_rdata_next[3:0] = alert_en_0_qs;
                   ==>
2821             end
2822       
2823             addr_hit[7]: begin
2824               reg_rdata_next[3:0] = alert_en_1_qs;
                   ==>
2825             end
2826       
2827             addr_hit[8]: begin
2828               reg_rdata_next[3:0] = alert_en_2_qs;
                   ==>
2829             end
2830       
2831             addr_hit[9]: begin
2832               reg_rdata_next[3:0] = alert_en_3_qs;
                   ==>
2833             end
2834       
2835             addr_hit[10]: begin
2836               reg_rdata_next[3:0] = alert_en_4_qs;
                   ==>
2837             end
2838       
2839             addr_hit[11]: begin
2840               reg_rdata_next[3:0] = alert_en_5_qs;
                   ==>
2841             end
2842       
2843             addr_hit[12]: begin
2844               reg_rdata_next[3:0] = alert_en_6_qs;
                   ==>
2845             end
2846       
2847             addr_hit[13]: begin
2848               reg_rdata_next[3:0] = alert_en_7_qs;
                   ==>
2849             end
2850       
2851             addr_hit[14]: begin
2852               reg_rdata_next[3:0] = alert_en_8_qs;
                   ==>
2853             end
2854       
2855             addr_hit[15]: begin
2856               reg_rdata_next[3:0] = alert_en_9_qs;
                   ==>
2857             end
2858       
2859             addr_hit[16]: begin
2860               reg_rdata_next[3:0] = alert_en_10_qs;
                   ==>
2861             end
2862       
2863             addr_hit[17]: begin
2864               reg_rdata_next[0] = fatal_alert_en_val_0_qs;
                   ==>
2865               reg_rdata_next[1] = fatal_alert_en_val_1_qs;
2866               reg_rdata_next[2] = fatal_alert_en_val_2_qs;
2867               reg_rdata_next[3] = fatal_alert_en_val_3_qs;
2868               reg_rdata_next[4] = fatal_alert_en_val_4_qs;
2869               reg_rdata_next[5] = fatal_alert_en_val_5_qs;
2870               reg_rdata_next[6] = fatal_alert_en_val_6_qs;
2871               reg_rdata_next[7] = fatal_alert_en_val_7_qs;
2872               reg_rdata_next[8] = fatal_alert_en_val_8_qs;
2873               reg_rdata_next[9] = fatal_alert_en_val_9_qs;
2874               reg_rdata_next[10] = fatal_alert_en_val_10_qs;
2875             end
2876       
2877             addr_hit[18]: begin
2878               reg_rdata_next[0] = recov_alert_val_0_qs;
                   ==>
2879               reg_rdata_next[1] = recov_alert_val_1_qs;
2880               reg_rdata_next[2] = recov_alert_val_2_qs;
2881               reg_rdata_next[3] = recov_alert_val_3_qs;
2882               reg_rdata_next[4] = recov_alert_val_4_qs;
2883               reg_rdata_next[5] = recov_alert_val_5_qs;
2884               reg_rdata_next[6] = recov_alert_val_6_qs;
2885               reg_rdata_next[7] = recov_alert_val_7_qs;
2886               reg_rdata_next[8] = recov_alert_val_8_qs;
2887               reg_rdata_next[9] = recov_alert_val_9_qs;
2888               reg_rdata_next[10] = recov_alert_val_10_qs;
2889             end
2890       
2891             addr_hit[19]: begin
2892               reg_rdata_next[0] = fatal_alert_val_0_qs;
                   ==>
2893               reg_rdata_next[1] = fatal_alert_val_1_qs;
2894               reg_rdata_next[2] = fatal_alert_val_2_qs;
2895               reg_rdata_next[3] = fatal_alert_val_3_qs;
2896               reg_rdata_next[4] = fatal_alert_val_4_qs;
2897               reg_rdata_next[5] = fatal_alert_val_5_qs;
2898               reg_rdata_next[6] = fatal_alert_val_6_qs;
2899               reg_rdata_next[7] = fatal_alert_val_7_qs;
2900               reg_rdata_next[8] = fatal_alert_val_8_qs;
2901               reg_rdata_next[9] = fatal_alert_val_9_qs;
2902               reg_rdata_next[10] = fatal_alert_val_10_qs;
2903               reg_rdata_next[11] = fatal_alert_val_11_qs;
2904             end
2905       
2906             addr_hit[20]: begin
2907               reg_rdata_next[0] = status_ast_init_done_qs;
                   ==>
2908               reg_rdata_next[2:1] = status_io_pok_qs;
2909             end
2910       
2911             addr_hit[21]: begin
2912               reg_rdata_next[0] = manual_pad_attr_regwen_0_qs;
                   ==>
2913             end
2914       
2915             addr_hit[22]: begin
2916               reg_rdata_next[0] = manual_pad_attr_regwen_1_qs;
                   ==>
2917             end
2918       
2919             addr_hit[23]: begin
2920               reg_rdata_next[0] = manual_pad_attr_regwen_2_qs;
                   ==>
2921             end
2922       
2923             addr_hit[24]: begin
2924               reg_rdata_next[0] = manual_pad_attr_regwen_3_qs;
                   ==>
2925             end
2926       
2927             addr_hit[25]: begin
2928               reg_rdata_next[2] = manual_pad_attr_0_pull_en_0_qs;
                   ==>
2929               reg_rdata_next[3] = manual_pad_attr_0_pull_select_0_qs;
2930               reg_rdata_next[7] = manual_pad_attr_0_input_disable_0_qs;
2931             end
2932       
2933             addr_hit[26]: begin
2934               reg_rdata_next[2] = manual_pad_attr_1_pull_en_1_qs;
                   ==>
2935               reg_rdata_next[3] = manual_pad_attr_1_pull_select_1_qs;
2936               reg_rdata_next[7] = manual_pad_attr_1_input_disable_1_qs;
2937             end
2938       
2939             addr_hit[27]: begin
2940               reg_rdata_next[2] = manual_pad_attr_2_pull_en_2_qs;
                   ==>
2941               reg_rdata_next[3] = manual_pad_attr_2_pull_select_2_qs;
2942               reg_rdata_next[7] = manual_pad_attr_2_input_disable_2_qs;
2943             end
2944       
2945             addr_hit[28]: begin
2946               reg_rdata_next[2] = manual_pad_attr_3_pull_en_3_qs;
                   ==>
2947               reg_rdata_next[3] = manual_pad_attr_3_pull_select_3_qs;
2948               reg_rdata_next[7] = manual_pad_attr_3_input_disable_3_qs;
2949             end
2950       
2951             default: begin
2952               reg_rdata_next = '1;
                   ==>

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : sensor_ctrl_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	104243070	2909	0	0
reAfterRv	104243070	2909	0	0
rePulse	104243070	2147	0	0
wePulse	104243070	762	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	104243070	2909	0	0
T1	25138	1	0	0
T2	16887	1	0	0
T3	51453	1	0	0
T4	43819	1	0	0
T11	31689	1	0	0
T22	28030	1	0	0
T24	52952	1	0	0
T31	23777	1	0	0
T39	54768	2	0	0
T97	19271	1	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	104243070	2909	0	0
T1	25138	1	0	0
T2	16887	1	0	0
T3	51453	1	0	0
T4	43819	1	0	0
T11	31689	1	0	0
T22	28030	1	0	0
T24	52952	1	0	0
T31	23777	1	0	0
T39	54768	2	0	0
T97	19271	1	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	104243070	2147	0	0
T1	25138	1	0	0
T2	16887	1	0	0
T3	51453	1	0	0
T4	43819	1	0	0
T11	31689	1	0	0
T22	28030	1	0	0
T24	52952	1	0	0
T31	23777	1	0	0
T39	54768	2	0	0
T97	19271	1	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	104243070	762	0	0
T46	0	36	0	0
T67	0	14	0	0
T69	22905	2	0	0
T70	0	2	0	0
T143	46876	0	0	0
T146	22789	0	0	0
T149	0	28	0	0
T150	0	55	0	0
T160	0	1	0	0
T161	0	12	0	0
T162	0	12	0	0
T176	10713	0	0	0
T177	9560	0	0	0
T193	40812	0	0	0
T235	68420	0	0	0
T287	23923	0	0	0
T288	54799	0	0	0
T358	0	12	0	0
T364	19155	0	0	0