Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T39,T31,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T24,T23,T120	Yes	T24,T23,T120	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T24,T23,T120	Yes	T24,T23,T120	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T32,*T80,*T88	Yes	T32,T80,T88	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T32,T80,T52	Yes	T32,T80,T52	INPUT
tl_i.a_valid	Yes	Yes	T24,T23,T120	Yes	T24,T23,T120	INPUT
tl_o.a_ready	Yes	Yes	T24,T23,T120	Yes	T24,T23,T120	OUTPUT
tl_o.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T24,T23,T120	Yes	T24,T23,T120	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T24,T23,T120	Yes	T24,T23,T120	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T24,T23,T120	Yes	T24,T23,T120	OUTPUT
tl_o.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T49,*T254,*T85	Yes	T49,T254,T85	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T24,*T23,*T120	Yes	T24,T23,T120	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T24,T23,T120	Yes	T24,T23,T120	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T172,T69,T289	Yes	T172,T69,T289	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T93,T94,T95	Yes	T93,T94,T95	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T93,T94,T95	Yes	T93,T94,T95	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T172,T69,T289	Yes	T172,T69,T289	OUTPUT
cio_rx_i	Yes	Yes	T39,T31,T24	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T24,T23,T120	Yes	T24,T23,T120	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T24,T23,T120	Yes	T24,T23,T120	OUTPUT
intr_tx_empty_o	Yes	Yes	T24,T23,T120	Yes	T24,T23,T120	OUTPUT
intr_rx_watermark_o	Yes	Yes	T24,T23,T120	Yes	T24,T23,T120	OUTPUT
intr_tx_done_o	Yes	Yes	T24,T23,T120	Yes	T24,T23,T120	OUTPUT
intr_rx_overflow_o	Yes	Yes	T24,T23,T120	Yes	T24,T23,T120	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T318,T319,T159	Yes	T318,T319,T159	OUTPUT
intr_rx_break_err_o	Yes	Yes	T318,T319,T96	Yes	T318,T319,T96	OUTPUT
intr_rx_timeout_o	Yes	Yes	T318,T319,T96	Yes	T318,T319,T96	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T318,T319,T96	Yes	T318,T319,T96	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T39,T31,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T120,T121,T204	Yes	T120,T121,T204	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T120,T121,T204	Yes	T120,T121,T204	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T32,*T80,*T88	Yes	T32,T80,T88	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T32,T80,T52	Yes	T32,T80,T52	INPUT
tl_i.a_valid	Yes	Yes	T120,T121,T172	Yes	T120,T121,T172	INPUT
tl_o.a_ready	Yes	Yes	T120,T121,T172	Yes	T120,T121,T172	OUTPUT
tl_o.d_error	Yes	Yes	T85,T87,T91	Yes	T87,T91,T250	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T120,T121,T599	Yes	T120,T121,T599	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T120,T121,T172	Yes	T120,T121,T172	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T120,T121,T172	Yes	T120,T121,T172	OUTPUT
tl_o.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T87,T90	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T49,*T254,*T87	Yes	T49,T254,T85	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T87,T89	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T120,*T121,*T599	Yes	T120,T121,T599	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T120,T121,T172	Yes	T120,T121,T172	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T172,T69,T93	Yes	T172,T69,T93	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T93,T94,T95	Yes	T93,T94,T95	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T93,T94,T95	Yes	T93,T94,T95	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T172,T69,T93	Yes	T172,T69,T93	OUTPUT
cio_rx_i	Yes	Yes	T39,T31,T33	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T120,T121,T48	Yes	T120,T121,T48	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T120,T121,T317	Yes	T120,T121,T317	OUTPUT
intr_tx_empty_o	Yes	Yes	T120,T121,T317	Yes	T120,T121,T317	OUTPUT
intr_rx_watermark_o	Yes	Yes	T120,T121,T317	Yes	T120,T121,T317	OUTPUT
intr_tx_done_o	Yes	Yes	T120,T121,T317	Yes	T120,T121,T317	OUTPUT
intr_rx_overflow_o	Yes	Yes	T120,T121,T317	Yes	T120,T121,T317	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T318,T319,T159	Yes	T318,T319,T159	OUTPUT
intr_rx_break_err_o	Yes	Yes	T318,T319,T154	Yes	T318,T319,T154	OUTPUT
intr_rx_timeout_o	Yes	Yes	T318,T319,T159	Yes	T318,T319,T159	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T318,T319,T96	Yes	T318,T319,T96	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T39,T31,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T24,T122,T123	Yes	T24,T122,T123	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T24,T122,T123	Yes	T24,T122,T123	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T32,*T80,*T88	Yes	T32,T80,T88	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T32,T80,T52	Yes	T32,T80,T52	INPUT
tl_i.a_valid	Yes	Yes	T24,T172,T69	Yes	T24,T172,T69	INPUT
tl_o.a_ready	Yes	Yes	T24,T172,T69	Yes	T24,T172,T69	OUTPUT
tl_o.d_error	Yes	Yes	T85,T87,T91	Yes	T85,T87,T91	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T24,T122,T123	Yes	T24,T122,T123	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T24,T172,T122	Yes	T24,T172,T69	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T24,T172,T122	Yes	T24,T172,T69	OUTPUT
tl_o.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T85,*T87,*T89	Yes	T85,T86,T87	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T24,*T122,*T123	Yes	T24,T122,T123	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T24,T172,T69	Yes	T24,T172,T69	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T172,T69,T289	Yes	T172,T69,T289	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T93,T94,T170	Yes	T93,T94,T170	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T93,T94,T170	Yes	T93,T94,T170	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T172,T69,T289	Yes	T172,T69,T289	OUTPUT
cio_rx_i	Yes	Yes	T24,T25,T122	Yes	T24,T10,T25	INPUT
cio_tx_o	Yes	Yes	T24,T122,T123	Yes	T24,T122,T123	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T24,T122,T123	Yes	T24,T122,T123	OUTPUT
intr_tx_empty_o	Yes	Yes	T24,T122,T123	Yes	T24,T122,T123	OUTPUT
intr_rx_watermark_o	Yes	Yes	T24,T122,T123	Yes	T24,T122,T123	OUTPUT
intr_tx_done_o	Yes	Yes	T24,T122,T123	Yes	T24,T122,T123	OUTPUT
intr_rx_overflow_o	Yes	Yes	T24,T122,T123	Yes	T24,T122,T123	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T318,T319,T154	Yes	T318,T319,T154	OUTPUT
intr_rx_break_err_o	Yes	Yes	T318,T319,T96	Yes	T318,T319,T96	OUTPUT
intr_rx_timeout_o	Yes	Yes	T318,T319,T159	Yes	T318,T319,T159	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T318,T319	Yes	T318,T319	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T39,T31,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T23,T9,T60	Yes	T23,T9,T60	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T23,T9,T60	Yes	T23,T9,T60	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T32,*T80,*T88	Yes	T32,T80,T88	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T32,T80,T52	Yes	T32,T80,T52	INPUT
tl_i.a_valid	Yes	Yes	T23,T172,T69	Yes	T23,T172,T69	INPUT
tl_o.a_ready	Yes	Yes	T23,T172,T69	Yes	T23,T172,T69	OUTPUT
tl_o.d_error	Yes	Yes	T86,T87,T90	Yes	T86,T87,T90	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T23,T9,T60	Yes	T23,T9,T60	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T23,T172,T9	Yes	T23,T172,T69	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T23,T172,T9	Yes	T23,T172,T69	OUTPUT
tl_o.d_sink	Yes	Yes	T86,T87,T90	Yes	T85,T86,T87	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T87,*T90,*T89	Yes	T85,T87,T90	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T23,*T9,*T60	Yes	T23,T9,T60	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T23,T172,T69	Yes	T23,T172,T69	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T172,T69,T93	Yes	T172,T69,T93	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T93,T94,T95	Yes	T93,T94,T95	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T93,T94,T95	Yes	T93,T94,T95	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T172,T69,T93	Yes	T172,T69,T93	OUTPUT
cio_rx_i	Yes	Yes	T23,T60,T124	Yes	T23,T60,T124	INPUT
cio_tx_o	Yes	Yes	T23,T60,T124	Yes	T23,T60,T124	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T23,T60,T318	Yes	T23,T60,T318	OUTPUT
intr_tx_empty_o	Yes	Yes	T23,T60,T318	Yes	T23,T60,T318	OUTPUT
intr_rx_watermark_o	Yes	Yes	T23,T60,T318	Yes	T23,T60,T318	OUTPUT
intr_tx_done_o	Yes	Yes	T23,T60,T318	Yes	T23,T60,T318	OUTPUT
intr_rx_overflow_o	Yes	Yes	T23,T60,T318	Yes	T23,T60,T318	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T318,T319	Yes	T318,T319	OUTPUT
intr_rx_break_err_o	Yes	Yes	T318,T319,T155	Yes	T318,T319,T155	OUTPUT
intr_rx_timeout_o	Yes	Yes	T318,T319,T96	Yes	T318,T319,T96	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T318,T319,T153	Yes	T318,T319,T153	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T39,T31,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T34,T9,T61	Yes	T34,T9,T61	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T34,T9,T61	Yes	T34,T9,T61	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T32,*T80,*T88	Yes	T32,T80,T88	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T32,T80,T52	Yes	T32,T80,T52	INPUT
tl_i.a_valid	Yes	Yes	T172,T69,T34	Yes	T172,T69,T34	INPUT
tl_o.a_ready	Yes	Yes	T172,T69,T34	Yes	T172,T69,T34	OUTPUT
tl_o.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T87,T89	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T34,T9,T61	Yes	T34,T9,T61	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T172,T34,T9	Yes	T172,T69,T34	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T172,T34,T9	Yes	T172,T69,T34	OUTPUT
tl_o.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T87,T89	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T85,*T87,*T90	Yes	T85,T86,T87	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T85,T87,T90	Yes	T85,T86,T87	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T34,*T9,*T61	Yes	T34,T9,T61	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T172,T69,T34	Yes	T172,T69,T34	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T172,T69,T93	Yes	T172,T69,T93	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T93,T94,T170	Yes	T93,T94,T170	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T93,T94,T170	Yes	T93,T94,T170	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T172,T69,T93	Yes	T172,T69,T93	OUTPUT
cio_rx_i	Yes	Yes	T34,T61,T125	Yes	T34,T61,T125	INPUT
cio_tx_o	Yes	Yes	T34,T61,T125	Yes	T34,T61,T125	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T34,T61,T318	Yes	T34,T61,T318	OUTPUT
intr_tx_empty_o	Yes	Yes	T34,T61,T318	Yes	T34,T61,T318	OUTPUT
intr_rx_watermark_o	Yes	Yes	T34,T61,T318	Yes	T34,T61,T318	OUTPUT
intr_tx_done_o	Yes	Yes	T34,T61,T318	Yes	T34,T61,T318	OUTPUT
intr_rx_overflow_o	Yes	Yes	T34,T61,T318	Yes	T34,T61,T318	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T318,T319	Yes	T318,T319	OUTPUT
intr_rx_break_err_o	Yes	Yes	T318,T319	Yes	T318,T319	OUTPUT
intr_rx_timeout_o	Yes	Yes	T318,T319,T597	Yes	T318,T319,T597	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T318,T319,T96	Yes	T318,T319,T96	OUTPUT

*Tests covering at least one bit in the range