Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T39,T31,T33	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T39,T31,T33	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T39,T31,T33	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T39,T31,T33	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T39,T31,T33	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T85,T91,T250	Yes	T85,T86,T87	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T87,T90,T89	Yes	T87,T90,T89	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T76,T218,T189	Yes	T76,T218,T189	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T76,T218,T189	Yes	T76,T218,T189	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T32,T80,T52	Yes	T32,T80,T52	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T32,T80,T210	Yes	T32,T80,T210	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T32,T80,T210	Yes	T32,T80,T210	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T75,T76,T172	Yes	T75,T76,T172	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T39,T31,T29	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T32,T80,T81	Yes	T32,T80,T81	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T39,T31,T29	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T39,T31,T29	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T32,T80,T81	Yes	T32,T80,T81	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T39,T31,T29	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T32,T80,T81	Yes	T32,T80,T81	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T39,T31,T33	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T32,T80,T81	Yes	T32,T80,T81	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T32,T80,T81	Yes	T32,T80,T81	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T32,T80,T81	Yes	T32,T80,T81	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T32,*T80,*T81	Yes	T32,T80,T81	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T32,T80,T81	Yes	T32,T80,T81	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T39,T31,T33	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T32,T86,T87	Yes	T32,T86,T87	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T32,T86,T87	Yes	T32,T86,T87	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T32,T86,T87	Yes	T32,T86,T87	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T32,T86,T90	Yes	T32,T86,T90	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T32,T86,T87	Yes	T32,T86,T87	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T32,T86,T87	Yes	T32,T86,T87	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T86,T87,T90	Yes	T86,T87,T90	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T86,T87,T90	Yes	T86,T87,T90	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T32,T86,T87	Yes	T32,T86,T87	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T32,T85,T91	Yes	T32,T85,T86	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T86,T87,T90	Yes	T86,T87,T90	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T86,T90,T89	Yes	T86,T90,T89	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T32,T86,T87	Yes	T32,T86,T87	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T32,T86,T87	Yes	T32,T86,T87	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T86,T87,T90	Yes	T86,T87,T90	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T32,*T87,T90	Yes	T32,T86,T87	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T86,T87,T90	Yes	T86,T87,T90	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T32,*T86,*T90	Yes	T32,T86,T87	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T32,T86,T87	Yes	T32,T86,T87	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T39,T31,T33	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T32,T253,T48	Yes	T32,T253,T48	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T32,T253,T48	Yes	T32,T253,T48	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T32,T253,T48	Yes	T32,T253,T48	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T32,T253,T48	Yes	T32,T253,T48	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T32,T253,T48	Yes	T32,T253,T48	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T253,*T48,*T49	Yes	T253,T48,T49	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T32,T253,T48	Yes	T32,T253,T48	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T39,T31,T29	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T253,T48,T49	Yes	T253,T48,T49	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T32,T253,T48	Yes	T32,T253,T48	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T39,T31,T29	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T253,*T48,*T49	Yes	T253,T48,T49	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T39,T31,T29	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T32,T253,T48	Yes	T32,T253,T48	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T33,T387,T80	Yes	T33,T387,T80	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T33,T80,T230	Yes	T33,T80,T230	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T39,T31,T33	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T69,T32,T70	Yes	T69,T32,T70	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T69,T388,T32	Yes	T69,T388,T32	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T69,T388,T32	Yes	T69,T388,T32	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T69,T32,T70	Yes	T69,T32,T70	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T69,T388,T32	Yes	T69,T388,T32	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T32,*T85,*T86	Yes	T32,T85,T86	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T69,T388,T32	Yes	T69,T388,T32	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T69,T388,T32	Yes	T69,T388,T32	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T87,T90,T89	Yes	T87,T90,T89	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T388,T269,T389	Yes	T388,T269,T389	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T32,T85,T87	Yes	T69,T32,T70	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T388,T32,T269	Yes	T69,T388,T32	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T87,T90	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T32,T87,T89	Yes	T32,T85,T86	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T86,T87,T90	Yes	T85,T87,T89	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T32,*T269,*T389	Yes	T388,T32,T269	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T69,T388,T32	Yes	T69,T388,T32	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T32,*T80,*T88	Yes	T32,T80,T88	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T32,T80,T52	Yes	T32,T80,T52	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T75,T76,T600	Yes	T75,T76,T600	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T32,*T80,*T88	Yes	T32,T80,T88	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T3,T8,T372	Yes	T3,T8,T372	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T3,T8,T372	Yes	T3,T8,T372	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T3,T8,T372	Yes	T3,T8,T372	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T3,T8,T372	Yes	T3,T8,T372	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T3,T8,T372	Yes	T3,T8,T372	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T3,T8,T372	Yes	T3,T8,T372	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T85,*T87,*T90	Yes	T85,T87,T90	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T87,T90,T89	Yes	T87,T90,T89	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T3,T205,T207	Yes	T3,T205,T207	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T3,T8,T372	Yes	T3,T8,T372	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T3,T8,T372	Yes	T3,T8,T372	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T85,T86,T90	Yes	T86,T90,T89	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T3,T8,T372	Yes	T3,T8,T372	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T8,T372	Yes	T3,T8,T372	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T3,T8,T372	Yes	T3,T8,T372	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T86,T87,T90	Yes	T85,T86,T87	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T86,*T87,*T90	Yes	T85,T86,T87	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T86,T87,T90	Yes	T86,T87,T90	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T3,*T8,*T372	Yes	T3,T8,T372	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T3,T8,T372	Yes	T3,T8,T372	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T372,T25,T69	Yes	T372,T25,T69	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T372,T25,T69	Yes	T372,T25,T69	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T372,T25,T69	Yes	T372,T25,T69	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T372,T25,T69	Yes	T372,T25,T69	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T372,T25,T69	Yes	T372,T25,T69	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T372,T25,T69	Yes	T372,T25,T69	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T86,T87,T90	Yes	T86,T87,T90	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T372,T25,T69	Yes	T372,T25,T69	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T372,T25,T69	Yes	T372,T25,T69	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T85,T87,T89	Yes	T85,T87,T89	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T372,T25,T9	Yes	T372,T25,T9	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T372,T25,T9	Yes	T372,T25,T69	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T372,T25,T9	Yes	T372,T25,T9	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T85,*T87,*T90	Yes	T85,T86,T87	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T372,*T25,*T9	Yes	T372,T25,T9	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T372,T25,T69	Yes	T372,T25,T69	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T372,T5,T6	Yes	T372,T5,T6	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T372,T5,T6	Yes	T372,T5,T6	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T372,T5,T6	Yes	T372,T5,T6	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T372,T5,T6	Yes	T372,T5,T6	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T372,T5,T6	Yes	T372,T5,T6	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T372,T5,T6	Yes	T372,T5,T6	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T372,T5,T6	Yes	T372,T5,T6	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T372,T5,T6	Yes	T372,T5,T6	INPUT
tl_usbdev_i.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T372,T5,T6	Yes	T372,T5,T6	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T372,T5,T6	Yes	T372,T5,T6	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T372,T5,T6	Yes	T372,T5,T6	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T87,*T90,*T89	Yes	T85,T86,T87	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T86,T87,T90	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T372,*T5,*T6	Yes	T372,T5,T6	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T372,T5,T6	Yes	T372,T5,T6	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T85,*T87,*T90	Yes	T85,T87,T90	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T87,T90,T89	Yes	T87,T90,T89	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T87,T89,T91	Yes	T87,T89,T91	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T39,T31,T33	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T39,T31,T178	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T87,T89,T91	Yes	T87,T89,T91	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T87,*T89,*T91	Yes	T85,T87,T89	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T87,T89,T91	Yes	T87,T89,T91	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T39,T31,T33	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T87,T90,T89	Yes	T87,T90,T89	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T85,T91,T250	Yes	T85,T86,T87	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T85,T87,T90	Yes	T86,T87,T90	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T85,T86,T87	Yes	T86,T87,T90	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T86,T87,T90	Yes	T85,T87,T90	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T86,T87,T90	Yes	T86,T87,T90	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	T87,T90,T89	Yes	T86,T87,T90	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T86,T87,T89	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T86,*T87,*T90	Yes	T86,T87,T90	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T39,T31,T33	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_hmac_o.d_ready	Yes	Yes	T39,T31,T33	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T69,T593,T314	Yes	T69,T593,T314	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T69,T593,T314	Yes	T69,T593,T314	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T69,T593,T314	Yes	T69,T593,T314	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T69,T593,T314	Yes	T69,T593,T314	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T69,T593,T314	Yes	T69,T593,T314	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T85,T87,T90	Yes	T85,T87,T90	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T593,T314,T594	Yes	T593,T314,T594	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T69,T593,T314	Yes	T69,T593,T314	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T69,T593,T314	Yes	T69,T593,T314	INPUT
tl_hmac_i.d_error	Yes	Yes	T86,T90,T89	Yes	T85,T90,T89	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T593,T314,T595	Yes	T593,T314,T595	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T593,T314,T595	Yes	T593,T314,T595	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T69,T593,T314	Yes	T593,T314,T594	INPUT
tl_hmac_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T87,*T90,*T89	Yes	T85,T86,T87	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T85,T87,T89	Yes	T85,T87,T90	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T69,*T593,*T314	Yes	T593,T314,T594	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T69,T593,T314	Yes	T69,T593,T314	INPUT
tl_kmac_o.d_ready	Yes	Yes	T39,T31,T33	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T69,T144,T404	Yes	T69,T144,T404	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T167,T181,T69	Yes	T167,T181,T69	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T167,T181,T69	Yes	T167,T181,T69	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T69,T144,T404	Yes	T69,T144,T404	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T167,T181,T69	Yes	T167,T181,T69	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T52,*T62,*T85	Yes	T52,T62,T85	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T85,T87,T90	Yes	T85,T87,T90	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T404,T405,T219	Yes	T404,T405,T219	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T167,T181,T69	Yes	T167,T181,T69	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T167,T181,T69	Yes	T167,T181,T69	INPUT
tl_kmac_i.d_error	Yes	Yes	T86,T87,T89	Yes	T86,T87,T89	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T167,T181,T133	Yes	T167,T181,T133	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T167,T181,T133	Yes	T167,T181,T133	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T167,T181,T69	Yes	T181,T144,T404	INPUT
tl_kmac_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T87,T90	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T52,*T62,*T87	Yes	T52,T62,T86	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T85,T87,T90	Yes	T85,T87,T89	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T167,*T181,*T69	Yes	T181,T144,T404	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T167,T181,T69	Yes	T167,T181,T69	INPUT
tl_aes_o.d_ready	Yes	Yes	T39,T31,T33	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T137,T69,T287	Yes	T137,T69,T287	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T137,T69,T287	Yes	T137,T69,T287	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T137,T69,T287	Yes	T137,T69,T287	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T137,T69,T287	Yes	T137,T69,T287	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T137,T69,T287	Yes	T137,T69,T287	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T62,*T85,*T86	Yes	T62,T85,T86	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T137,T69,T287	Yes	T137,T69,T287	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T137,T69,T287	Yes	T137,T69,T287	INPUT
tl_aes_i.d_error	Yes	Yes	T86,T87,T90	Yes	T86,T87,T90	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T137,T287,T133	Yes	T137,T287,T133	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T137,T287,T133	Yes	T137,T69,T287	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T137,T287,T255	Yes	T137,T69,T287	INPUT
tl_aes_i.d_sink	Yes	Yes	T86,T87,T90	Yes	T86,T87,T90	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T62,*T86,*T87	Yes	T62,T86,T87	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T86,T87,T90	Yes	T86,T87,T90	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T137,*T287,*T133	Yes	T137,T287,T133	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T137,T69,T287	Yes	T137,T69,T287	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T85,T87,T90	Yes	T86,T87,T89	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T143,T146,T147	Yes	T143,T146,T147	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T39,T31,T33	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T39,T31,T33	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T87,T89	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T85,*T87,*T90	Yes	T85,T86,T87	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T143,*T146,*T147	Yes	T143,T146,T147	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T69,T364,T143	Yes	T69,T364,T143	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T62,*T87,*T89	Yes	T62,T87,T89	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T86,T87,T89	Yes	T86,T87,T89	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T87,T90,T89	Yes	T87,T90,T89	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T91,T250,T417	Yes	T91,T250,T417	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T364,T143,T146	Yes	T364,T143,T146	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T39,T31,T33	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T39,T31,T33	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T87,T90,T89	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T62,*T87,*T89	Yes	T62,T87,T89	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T87,T89,T91	Yes	T85,T86,T87	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T364,*T143,*T146	Yes	T364,T143,T146	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T69,T143,T146	Yes	T69,T143,T146	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T69,T143,T146	Yes	T69,T143,T146	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T85,T87,T90	Yes	T85,T87,T90	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T85,T87,T90	Yes	T85,T87,T90	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T143,T146,T147	Yes	T143,T146,T147	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T39,T31,T33	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T39,T31,T33	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T85,*T87,*T90	Yes	T85,T86,T87	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T87,T90,T89	Yes	T85,T87,T90	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T143,*T146,*T147	Yes	T143,T146,T147	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T39,T31,T33	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T69,T143,T146	Yes	T69,T143,T146	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T69,T143,T146	Yes	T69,T143,T146	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T69,T143,T146	Yes	T69,T143,T146	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T69,T143,T146	Yes	T69,T143,T146	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T69,T143,T146	Yes	T69,T143,T146	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T85,T87,T90	Yes	T85,T87,T90	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T69,T143,T146	Yes	T69,T143,T146	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T69,T143,T146	Yes	T69,T143,T146	INPUT
tl_edn1_i.d_error	Yes	Yes	T85,T87,T89	Yes	T85,T87,T89	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T143,T146,T147	Yes	T143,T146,T147	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T143,T147,T133	Yes	T69,T143,T146	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T143,T147,T133	Yes	T69,T143,T146	INPUT
tl_edn1_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T87,*T90,*T89	Yes	T85,T86,T87	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T85,T87,T90	Yes	T87,T90,T89	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T143,*T146,*T147	Yes	T143,T146,T147	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T69,T143,T146	Yes	T69,T143,T146	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T87,T90	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T85,*T87,*T90	Yes	T85,T86,T87	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T1,*T3,*T4	Yes	T1,T3,T4	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_otbn_o.d_ready	Yes	Yes	T39,T31,T33	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T69,T193,T143	Yes	T69,T193,T143	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T69,T193,T143	Yes	T69,T193,T143	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T69,T193,T143	Yes	T69,T193,T143	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T69,T193,T143	Yes	T69,T193,T143	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T69,T193,T143	Yes	T69,T193,T143	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T80,*T52,*T209	Yes	T80,T52,T209	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T69,T193,T143	Yes	T69,T193,T143	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T69,T193,T143	Yes	T69,T193,T143	INPUT
tl_otbn_i.d_error	Yes	Yes	T85,T87,T90	Yes	T85,T87,T90	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T193,T143,T147	Yes	T193,T143,T147	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T193,T143,T147	Yes	T193,T143,T147	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T69,T193,T143	Yes	T193,T143,T147	INPUT
tl_otbn_i.d_sink	Yes	Yes	T85,T87,T90	Yes	T85,T87,T90	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T80,*T52,*T209	Yes	T80,T52,T209	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T85,T87,T90	Yes	T85,T86,T87	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T69,*T193,*T143	Yes	T193,T143,T147	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T69,T193,T143	Yes	T69,T193,T143	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T39,T31,T33	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T167,T181,T69	Yes	T167,T181,T69	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T167,T181,T69	Yes	T167,T181,T69	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T167,T181,T69	Yes	T167,T181,T69	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T181,T69,T133	Yes	T181,T69,T133	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T167,T181,T69	Yes	T167,T181,T69	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T167,T181,T69	Yes	T167,T181,T69	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T167,T181,T69	Yes	T167,T181,T69	INPUT
tl_keymgr_i.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T181,T133,T204	Yes	T181,T133,T204	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T181,T133,T204	Yes	T181,T69,T133	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T181,T133,T204	Yes	T181,T69,T133	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T87,*T90,*T89	Yes	T85,T86,T87	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T86,T87,T90	Yes	T85,T86,T87	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T181,*T133,*T204	Yes	T167,T181,T133	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T167,T181,T69	Yes	T167,T181,T69	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T32,*T254,*T85	Yes	T32,T254,T85	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T32,T85,T86	Yes	T32,T85,T86	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T1,T4,T39	Yes	T1,T4,T39	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T1,T4,T39	Yes	T1,T4,T39	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T32,*T86,*T87	Yes	T32,T254,T86	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T39,T31,T33	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T69,T187,T138	Yes	T69,T187,T138	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T69,T187,T138	Yes	T69,T187,T138	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T69,T187,T138	Yes	T69,T187,T138	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T69,T187,T138	Yes	T69,T187,T138	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T69,T187,T138	Yes	T69,T187,T138	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T85,*T87,*T90	Yes	T85,T87,T90	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T85,T87,T90	Yes	T85,T87,T90	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T69,T187,T138	Yes	T69,T187,T138	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T69,T187,T138	Yes	T69,T187,T138	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T85,T86,T89	Yes	T85,T90,T89	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T189,T303,T304	Yes	T189,T303,T304	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T187,T138,T189	Yes	T69,T187,T138	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T187,T138,T189	Yes	T69,T187,T138	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T85,T87,T90	Yes	T85,T86,T87	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T87,*T89,*T91	Yes	T85,T87,T90	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T187,*T138,*T189	Yes	T187,T138,T189	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T69,T187,T138	Yes	T69,T187,T138	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T39,T31,T33	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range