Unified Coverage Report :: Module :: prim_generic_usb_diff_rx

Module : prim_generic_usb_diff_rx

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.30	100.00	88.89			100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_usb_diff_rx_0/rtl/prim_generic_usb_diff_rx.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_usb_diff_rx.gen_generic.u_impl_generic	96.30	100.00	88.89			100.00

---

Module Instance : tb.dut.u_prim_usb_diff_rx.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.30	100.00	88.89			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.30	100.00	88.89			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_usb_diff_rx

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
obs_buf	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_generic_usb_diff_rx

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	31	1	1	100.00
CONT_ASSIGN	39	1	1	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00

25                        logic unused_core_pok;
26         unreachable    assign unused_calibration = calibration_i;
27         1/1            assign unused_core_pok = core_pok_h_i;
           Tests:       T1 T2 T3 
28                      
29                        wire input_p, input_n;
30         1/1            assign input_p = input_pi;
           Tests:       T10 T5 T6 
31         1/1            assign input_n = input_ni;
           Tests:       T10 T5 T6 
32                      
33                      `ifdef VERILATOR
34                        logic unused_pullup_p_en, unused_pullup_n_en;
35                        assign unused_pullup_p_en = pullup_p_en_i;
36                        assign unused_pullup_n_en = pullup_n_en_i;
37                      `else
38                        // pullup termination
39         1/1            assign (weak0, pull1) input_pi = pullup_p_en_i ? 1'b1 : 1'bz;
           Tests:       T5 T6 T7 
40         1/1            assign (weak0, pull1) input_ni = pullup_n_en_i ? 1'b1 : 1'bz;
           Tests:       T5 T35 
41                      `endif
42                      
43         1/1            assign input_o = (input_en_i) ? input_p & ~input_n : 1'b0;
           Tests:       T5 T6 T7 

---

Cond Coverage for Module : prim_generic_usb_diff_rx

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (pullup_p_en_i ? 1'b1 : 1'bz)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       40
 EXPRESSION (pullup_n_en_i ? 1'b1 : 1'bz)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T35

 LINE       43
 EXPRESSION (input_en_i ? (input_p & ((~input_n))) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       43
 SUB-EXPRESSION (input_p & ((~input_n)))
                 ---1---   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T5,T6,T7

---

Branch Coverage for Module : prim_generic_usb_diff_rx

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	39	2	2	100.00
TERNARY	40	2	2	100.00
TERNARY	43	2	2	100.00

39           assign (weak0, pull1) input_pi = pullup_p_en_i ? 1'b1 : 1'bz;
                                                            -1-  
                                                            ==>  
                                                            ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T1,T2,T3

40           assign (weak0, pull1) input_ni = pullup_n_en_i ? 1'b1 : 1'bz;
                                                            -1-  
                                                            ==>  
                                                            ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T35
0	Covered	T1,T2,T3

43           assign input_o = (input_en_i) ? input_p & ~input_n : 1'b0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T1,T2,T3