Unified Coverage Report :: Module :: rv_core_addr_trans

Module : rv_core_addr_trans

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans	100.00	100.00	100.00			100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.36	100.00	92.59			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.74	96.47	89.29	99.75		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.36	100.00	92.59			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.74	96.47	89.29	99.75		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sel_region	94.88	100.00	86.67			100.00	92.86

Line Coverage for Module : rv_core_addr_trans

	Line No.	Total	Covered	Percent
TOTAL		71	71	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	84	1	1	100.00

40                          for (genvar j = 1; j < AddrWidth; j++) begin : gen_addr_masks_lower_bits
41         62/62              assign input_masks[i][j] = ~&region_cfg_i[i].matching_region[j-1:0];
           Tests:       T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T190 T192 T239  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192 
42                          end
43                      
44                          // pack things into region controls
45         2/2              assign region_ctrls[i].output_mask = ~input_masks[i];
           Tests:       T190 T192 T239  | T190 T192 T239 
46         2/2              assign region_ctrls[i].remap_addr = region_cfg_i[i].remap_addr;
           Tests:       T32 T190 T192  | T32 T190 T192 
47                        end
48                      
49                        logic [NumRegions-1:0] all_matches;
50                        for (genvar i = 0; i < NumRegions; i++) begin : gen_region_matches
51         2/2              assign all_matches[i] = region_cfg_i[i].en &
           Tests:       T1 T2 T3  | T1 T2 T3 
52                                                  ((region_cfg_i[i].matching_region & input_masks[i]) ==
53                                                  (addr_i & input_masks[i]));
54                        end
55                      
56                        logic sel_match;
57                        region_ctrls_t sel_region;
58                        prim_arbiter_fixed #(
59                          .N(NumRegions),
60                          .DW($bits(region_ctrls_t)),
61                          .EnDataPort(1)
62                        ) u_sel_region (
63                          .clk_i,
64                          .rst_ni,
65                          .req_i(all_matches),
66                          .data_i(region_ctrls),
67                          .gnt_o(),
68                          .idx_o(),
69                          .valid_o(sel_match),
70                          .data_o(sel_region),
71                          .ready_i(1'b1)
72                        );
73                      
74                        // if there is a match, mask off the address bits and remap
75                        // if there is no match, just use incoming address
76         1/1            assign addr_o = sel_match ?
           Tests:       T1 T2 T3 
77                          (addr_i & sel_region.output_mask) | (sel_region.remap_addr & ~sel_region.output_mask) :
78                          addr_i;
79                      
80                        // unused clock/reset, only needed for assertions
81                        logic unused_clk;
82                        logic unused_rst_n;
83         1/1            assign unused_clk = clk_i;
           Tests:       T1 T2 T3 
84         1/1            assign unused_rst_n = rst_ni;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : rv_core_addr_trans

	Total	Covered	Percent
Conditions	12	12	100.00
Logical	12	12	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (region_cfg_i[0].en & ((region_cfg_i[0].matching_region & input_masks[0]) == (addr_i & input_masks[0])))
             ---------1--------   ----------------------------------------2----------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T190,T192,T239
1	1	Covered	T190,T192,T239

 LINE       51
 SUB-EXPRESSION ((region_cfg_i[0].matching_region & input_masks[0]) == (addr_i & input_masks[0]))
                ----------------------------------------1----------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       51
 EXPRESSION (region_cfg_i[1].en & ((region_cfg_i[1].matching_region & input_masks[1]) == (addr_i & input_masks[1])))
             ---------1--------   ----------------------------------------2----------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T190,T192,T239
1	1	Covered	T190,T192,T239

 LINE       51
 SUB-EXPRESSION ((region_cfg_i[1].matching_region & input_masks[1]) == (addr_i & input_masks[1]))
                ----------------------------------------1----------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (sel_match ? (((addr_i & sel_region.output_mask) | (sel_region.remap_addr & (~sel_region.output_mask)))) : addr_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T190,T192,T239

---

Branch Coverage for Module : rv_core_addr_trans

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	76	2	2	100.00

76           assign addr_o = sel_match ?
                                       -1-  
                                       ==>  
                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T190,T192,T239
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans

	Line No.	Total	Covered	Percent
TOTAL		71	71	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	84	1	1	100.00

40                          for (genvar j = 1; j < AddrWidth; j++) begin : gen_addr_masks_lower_bits
41         62/62              assign input_masks[i][j] = ~&region_cfg_i[i].matching_region[j-1:0];
           Tests:       T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192 
42                          end
43                      
44                          // pack things into region controls
45         2/2              assign region_ctrls[i].output_mask = ~input_masks[i];
           Tests:       T190 T192 T239  | T190 T192 T239 
46         2/2              assign region_ctrls[i].remap_addr = region_cfg_i[i].remap_addr;
           Tests:       T190 T192 T239  | T32 T190 T192 
47                        end
48                      
49                        logic [NumRegions-1:0] all_matches;
50                        for (genvar i = 0; i < NumRegions; i++) begin : gen_region_matches
51         2/2              assign all_matches[i] = region_cfg_i[i].en &
           Tests:       T1 T2 T3  | T1 T2 T3 
52                                                  ((region_cfg_i[i].matching_region & input_masks[i]) ==
53                                                  (addr_i & input_masks[i]));
54                        end
55                      
56                        logic sel_match;
57                        region_ctrls_t sel_region;
58                        prim_arbiter_fixed #(
59                          .N(NumRegions),
60                          .DW($bits(region_ctrls_t)),
61                          .EnDataPort(1)
62                        ) u_sel_region (
63                          .clk_i,
64                          .rst_ni,
65                          .req_i(all_matches),
66                          .data_i(region_ctrls),
67                          .gnt_o(),
68                          .idx_o(),
69                          .valid_o(sel_match),
70                          .data_o(sel_region),
71                          .ready_i(1'b1)
72                        );
73                      
74                        // if there is a match, mask off the address bits and remap
75                        // if there is no match, just use incoming address
76         1/1            assign addr_o = sel_match ?
           Tests:       T1 T2 T3 
77                          (addr_i & sel_region.output_mask) | (sel_region.remap_addr & ~sel_region.output_mask) :
78                          addr_i;
79                      
80                        // unused clock/reset, only needed for assertions
81                        logic unused_clk;
82                        logic unused_rst_n;
83         1/1            assign unused_clk = clk_i;
           Tests:       T1 T2 T3 
84         1/1            assign unused_rst_n = rst_ni;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans

	Total	Covered	Percent
Conditions	12	12	100.00
Logical	12	12	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (region_cfg_i[0].en & ((region_cfg_i[0].matching_region & input_masks[0]) == (addr_i & input_masks[0])))
             ---------1--------   ----------------------------------------2----------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T190,T192,T239
1	0	Covered	T190,T192,T239
1	1	Covered	T190,T192,T239

 LINE       51
 SUB-EXPRESSION ((region_cfg_i[0].matching_region & input_masks[0]) == (addr_i & input_masks[0]))
                ----------------------------------------1----------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T190,T192,T239

 LINE       51
 EXPRESSION (region_cfg_i[1].en & ((region_cfg_i[1].matching_region & input_masks[1]) == (addr_i & input_masks[1])))
             ---------1--------   ----------------------------------------2----------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T190,T192,T239
1	0	Covered	T190,T192,T239
1	1	Covered	T190,T192,T239

 LINE       51
 SUB-EXPRESSION ((region_cfg_i[1].matching_region & input_masks[1]) == (addr_i & input_masks[1]))
                ----------------------------------------1----------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T190,T192,T239

 LINE       76
 EXPRESSION (sel_match ? (((addr_i & sel_region.output_mask) | (sel_region.remap_addr & (~sel_region.output_mask)))) : addr_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T190,T192,T239

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	76	2	2	100.00

76           assign addr_o = sel_match ?
                                       -1-  
                                       ==>  
                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T190,T192,T239
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans

	Line No.	Total	Covered	Percent
TOTAL		71	71	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	84	1	1	100.00

40                          for (genvar j = 1; j < AddrWidth; j++) begin : gen_addr_masks_lower_bits
41         62/62              assign input_masks[i][j] = ~&region_cfg_i[i].matching_region[j-1:0];
           Tests:       T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T190 T192 T239  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192  | T32 T190 T192 
42                          end
43                      
44                          // pack things into region controls
45         2/2              assign region_ctrls[i].output_mask = ~input_masks[i];
           Tests:       T190 T192 T239  | T190 T192 T239 
46         2/2              assign region_ctrls[i].remap_addr = region_cfg_i[i].remap_addr;
           Tests:       T32 T190 T192  | T32 T190 T192 
47                        end
48                      
49                        logic [NumRegions-1:0] all_matches;
50                        for (genvar i = 0; i < NumRegions; i++) begin : gen_region_matches
51         2/2              assign all_matches[i] = region_cfg_i[i].en &
           Tests:       T1 T2 T3  | T1 T2 T3 
52                                                  ((region_cfg_i[i].matching_region & input_masks[i]) ==
53                                                  (addr_i & input_masks[i]));
54                        end
55                      
56                        logic sel_match;
57                        region_ctrls_t sel_region;
58                        prim_arbiter_fixed #(
59                          .N(NumRegions),
60                          .DW($bits(region_ctrls_t)),
61                          .EnDataPort(1)
62                        ) u_sel_region (
63                          .clk_i,
64                          .rst_ni,
65                          .req_i(all_matches),
66                          .data_i(region_ctrls),
67                          .gnt_o(),
68                          .idx_o(),
69                          .valid_o(sel_match),
70                          .data_o(sel_region),
71                          .ready_i(1'b1)
72                        );
73                      
74                        // if there is a match, mask off the address bits and remap
75                        // if there is no match, just use incoming address
76         1/1            assign addr_o = sel_match ?
           Tests:       T1 T2 T3 
77                          (addr_i & sel_region.output_mask) | (sel_region.remap_addr & ~sel_region.output_mask) :
78                          addr_i;
79                      
80                        // unused clock/reset, only needed for assertions
81                        logic unused_clk;
82                        logic unused_rst_n;
83         1/1            assign unused_clk = clk_i;
           Tests:       T1 T2 T3 
84         1/1            assign unused_rst_n = rst_ni;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans

	Total	Covered	Percent
Conditions	12	12	100.00
Logical	12	12	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (region_cfg_i[0].en & ((region_cfg_i[0].matching_region & input_masks[0]) == (addr_i & input_masks[0])))
             ---------1--------   ----------------------------------------2----------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T190,T192,T239
1	1	Covered	T190,T192,T239

 LINE       51
 SUB-EXPRESSION ((region_cfg_i[0].matching_region & input_masks[0]) == (addr_i & input_masks[0]))
                ----------------------------------------1----------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       51
 EXPRESSION (region_cfg_i[1].en & ((region_cfg_i[1].matching_region & input_masks[1]) == (addr_i & input_masks[1])))
             ---------1--------   ----------------------------------------2----------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T190,T192,T239
1	1	Covered	T190,T192,T239

 LINE       51
 SUB-EXPRESSION ((region_cfg_i[1].matching_region & input_masks[1]) == (addr_i & input_masks[1]))
                ----------------------------------------1----------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (sel_match ? (((addr_i & sel_region.output_mask) | (sel_region.remap_addr & (~sel_region.output_mask)))) : addr_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T190,T192,T239

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	76	2	2	100.00

76           assign addr_o = sel_match ?
                                       -1-  
                                       ==>  
                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T190,T192,T239
0	Covered	T1,T2,T3