Unified Coverage Report :: Module :: prim_mubi4_sync

Module : prim_mubi4_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync	100.00						100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.83	99.34	100.00			100.00	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	777	777	0	0
OutputsKnown_A	105296497	104786448	0	0
gen_no_flops.OutputDelay_A	105296497	104786448	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	777	777	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T22	1	1	0	0
T24	1	1	0	0
T31	1	1	0	0
T39	1	1	0	0
T97	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105296497	104786448	0	0
T1	36435	35822	0	0
T2	17245	16877	0	0
T3	52205	51443	0	0
T4	44432	43807	0	0
T11	32125	31678	0	0
T22	40201	39891	0	0
T24	53419	52941	0	0
T31	24511	23756	0	0
T39	55223	54746	0	0
T97	20174	19259	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105296497	104786448	0	0
T1	36435	35822	0	0
T2	17245	16877	0	0
T3	52205	51443	0	0
T4	44432	43807	0	0
T11	32125	31678	0	0
T22	40201	39891	0	0
T24	53419	52941	0	0
T31	24511	23756	0	0
T39	55223	54746	0	0
T97	20174	19259	0	0

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	777	777	0	0
OutputsKnown_A	105296497	104786448	0	0
gen_no_flops.OutputDelay_A	105296497	104786448	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	777	777	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T22	1	1	0	0
T24	1	1	0	0
T31	1	1	0	0
T39	1	1	0	0
T97	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105296497	104786448	0	0
T1	36435	35822	0	0
T2	17245	16877	0	0
T3	52205	51443	0	0
T4	44432	43807	0	0
T11	32125	31678	0	0
T22	40201	39891	0	0
T24	53419	52941	0	0
T31	24511	23756	0	0
T39	55223	54746	0	0
T97	20174	19259	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105296497	104786448	0	0
T1	36435	35822	0	0
T2	17245	16877	0	0
T3	52205	51443	0	0
T4	44432	43807	0	0
T11	32125	31678	0	0
T22	40201	39891	0	0
T24	53419	52941	0	0
T31	24511	23756	0	0
T39	55223	54746	0	0
T97	20174	19259	0	0