Module Definition
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Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_pinmux_jtag_buf_lc.prim_clock_buf_tck.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_clock_buf_tck


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_pinmux_jtag_buf_rv.prim_clock_buf_tck.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_clock_buf_tck


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_pinmux_jtag_buf_dft.prim_clock_buf_tck.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_clock_buf_tck


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_buf
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2011100.00
CONT_ASSIGN2111100.00

19 logic inv; 20 1/1 assign inv = ~clk_i; Tests: T31 T29 T30  21 1/1 assign clk_o = ~inv; Tests: T31 T29 T30 
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_pinmux_jtag_buf_lc.prim_clock_buf_tck.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2011100.00
CONT_ASSIGN2111100.00

19 logic inv; 20 1/1 assign inv = ~clk_i; Tests: T31 T29 T30  21 1/1 assign clk_o = ~inv; Tests: T31 T29 T30 
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_pinmux_jtag_buf_rv.prim_clock_buf_tck.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2011100.00
CONT_ASSIGN2111100.00

19 logic inv; 20 1/1 assign inv = ~clk_i; Tests: T32 T80 T81  21 1/1 assign clk_o = ~inv; Tests: T32 T80 T81 
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_pinmux_jtag_buf_dft.prim_clock_buf_tck.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2011100.00
CONT_ASSIGN2111100.00

19 logic inv; 20 1/1 assign inv = ~clk_i; Tests: T81 T82 T83  21 1/1 assign clk_o = ~inv; Tests: T81 T82 T83