Unified Coverage Report :: Module :: prim_lc_sender

Module : prim_lc_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en	100.00	100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_lc_sender	100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.83	99.34	100.00			100.00	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_lc_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.74	96.47	89.29	99.75		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

Line Coverage for Module : prim_lc_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	66	1	1	100.00

31                        logic [lc_ctrl_pkg::TxWidth-1:0] lc_en, lc_en_out;
32         1/1            assign lc_en = lc_ctrl_pkg::TxWidth'(lc_en_i);
           Tests:       T1 T2 T3 
33                      
34                        if (AsyncOn) begin : gen_flops
35                          prim_sec_anchor_flop #(
36                            .Width(lc_ctrl_pkg::TxWidth),
37                            .ResetValue(lc_ctrl_pkg::TxWidth'(ResetValue))
38                          ) u_prim_flop (
39                            .clk_i,
40                            .rst_ni,
41                            .d_i   ( lc_en     ),
42                            .q_o   ( lc_en_out )
43                          );
44                        end else begin : gen_no_flops
45                          for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
46                            prim_sec_anchor_buf u_prim_buf (
47                              .in_i(lc_en[k]),
48                              .out_o(lc_en_out[k])
49                            );
50                          end
51                      
52                          // This unused companion logic helps remove lint errors
53                          // for modules where clock and reset are used for assertions only
54                          // or nothing at all.
55                          // This logic will be removed for sythesis since it is unloaded.
56                          lc_ctrl_pkg::lc_tx_t unused_logic;
57                          always_ff @(posedge clk_i or negedge rst_ni) begin
58                            if (!rst_ni) begin
59                               unused_logic <= lc_ctrl_pkg::Off;
60                            end else begin
61                               unused_logic <= lc_en_i;
62                            end
63                          end
64                        end
65                      
66         1/1            assign lc_en_o = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	66	1	1	100.00

31                        logic [lc_ctrl_pkg::TxWidth-1:0] lc_en, lc_en_out;
32         1/1            assign lc_en = lc_ctrl_pkg::TxWidth'(lc_en_i);
           Tests:       T1 T2 T3 
33                      
34                        if (AsyncOn) begin : gen_flops
35                          prim_sec_anchor_flop #(
36                            .Width(lc_ctrl_pkg::TxWidth),
37                            .ResetValue(lc_ctrl_pkg::TxWidth'(ResetValue))
38                          ) u_prim_flop (
39                            .clk_i,
40                            .rst_ni,
41                            .d_i   ( lc_en     ),
42                            .q_o   ( lc_en_out )
43                          );
44                        end else begin : gen_no_flops
45                          for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
46                            prim_sec_anchor_buf u_prim_buf (
47                              .in_i(lc_en[k]),
48                              .out_o(lc_en_out[k])
49                            );
50                          end
51                      
52                          // This unused companion logic helps remove lint errors
53                          // for modules where clock and reset are used for assertions only
54                          // or nothing at all.
55                          // This logic will be removed for sythesis since it is unloaded.
56                          lc_ctrl_pkg::lc_tx_t unused_logic;
57                          always_ff @(posedge clk_i or negedge rst_ni) begin
58                            if (!rst_ni) begin
59                               unused_logic <= lc_ctrl_pkg::Off;
60                            end else begin
61                               unused_logic <= lc_en_i;
62                            end
63                          end
64                        end
65                      
66         1/1            assign lc_en_o = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_lc_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	66	1	1	100.00

31                        logic [lc_ctrl_pkg::TxWidth-1:0] lc_en, lc_en_out;
32         1/1            assign lc_en = lc_ctrl_pkg::TxWidth'(lc_en_i);
           Tests:       T1 T2 T3 
33                      
34                        if (AsyncOn) begin : gen_flops
35                          prim_sec_anchor_flop #(
36                            .Width(lc_ctrl_pkg::TxWidth),
37                            .ResetValue(lc_ctrl_pkg::TxWidth'(ResetValue))
38                          ) u_prim_flop (
39                            .clk_i,
40                            .rst_ni,
41                            .d_i   ( lc_en     ),
42                            .q_o   ( lc_en_out )
43                          );
44                        end else begin : gen_no_flops
45                          for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
46                            prim_sec_anchor_buf u_prim_buf (
47                              .in_i(lc_en[k]),
48                              .out_o(lc_en_out[k])
49                            );
50                          end
51                      
52                          // This unused companion logic helps remove lint errors
53                          // for modules where clock and reset are used for assertions only
54                          // or nothing at all.
55                          // This logic will be removed for sythesis since it is unloaded.
56                          lc_ctrl_pkg::lc_tx_t unused_logic;
57                          always_ff @(posedge clk_i or negedge rst_ni) begin
58                            if (!rst_ni) begin
59                               unused_logic <= lc_ctrl_pkg::Off;
60                            end else begin
61                               unused_logic <= lc_en_i;
62                            end
63                          end
64                        end
65                      
66         1/1            assign lc_en_o = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T236 T376 T237