0825c81be0| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | chip_sw_example_tests | chip_sw_example_flash | 3.367m | 2.718ms | 3 | 3 | 100.00 |
| chip_sw_example_rom | 1.799m | 2.788ms | 3 | 3 | 100.00 | ||
| chip_sw_example_manufacturer | 3.347m | 3.585ms | 3 | 3 | 100.00 | ||
| chip_sw_example_concurrency | 3.050m | 3.118ms | 3 | 3 | 100.00 | ||
| V1 | csr_hw_reset | chip_csr_hw_reset | 5.263m | 7.383ms | 5 | 5 | 100.00 |
| V1 | csr_rw | chip_csr_rw | 8.415m | 6.827ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | chip_csr_bit_bash | 1.124h | 56.274ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | chip_csr_aliasing | 2.307h | 53.329ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | chip_csr_mem_rw_with_rand_reset | 12.178m | 12.117ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 2.307h | 53.329ms | 5 | 5 | 100.00 |
| chip_csr_rw | 8.415m | 6.827ms | 20 | 20 | 100.00 | ||
| V1 | xbar_smoke | xbar_smoke | 8.050s | 235.794us | 100 | 100 | 100.00 |
| V1 | chip_sw_gpio_out | chip_sw_gpio | 5.941m | 4.587ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_in | chip_sw_gpio | 5.941m | 4.587ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 5.941m | 4.587ms | 3 | 3 | 100.00 |
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 7.317m | 4.873ms | 5 | 5 | 100.00 |
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 7.317m | 4.873ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_idx1 | 7.642m | 4.491ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx2 | 7.380m | 4.847ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx3 | 7.428m | 4.637ms | 5 | 5 | 100.00 | ||
| V1 | chip_sw_uart_baud_rate | chip_sw_uart_rand_baudrate | 32.520m | 12.553ms | 20 | 20 | 100.00 |
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 20.833m | 8.454ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 12.047m | 7.764ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 220 | 220 | 100.00 | |||
| V2 | chip_pin_mux | chip_padctrl_attributes | 4.349m | 6.109ms | 10 | 10 | 100.00 |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 4.349m | 6.109ms | 10 | 10 | 100.00 |
| V2 | chip_sw_sleep_pin_mio_dio_val | chip_sw_sleep_pin_mio_dio_val | 3.643m | 2.779ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 4.380m | 5.321ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 4.597m | 4.465ms | 3 | 3 | 100.00 |
| V2 | chip_sw_tap_strap_sampling | chip_tap_straps_dev | 3.817m | 3.747ms | 5 | 5 | 100.00 |
| chip_tap_straps_testunlock0 | 7.974m | 7.608ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 6.441m | 6.023ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 22.790m | 17.762ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_pattgen_ios | chip_sw_pattgen_ios | 3.228m | 3.089ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pwm_pulses | chip_sw_sleep_pwm_pulses | 14.634m | 8.903ms | 3 | 3 | 100.00 |
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 9.081m | 6.410ms | 6 | 6 | 100.00 |
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 9.081m | 6.410ms | 6 | 6 | 100.00 |
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 11.958m | 8.356ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_rst_inputs | chip_sw_ast_clk_rst_inputs | 47.574m | 23.714ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_flash_ctrl_ops_jitter_en | 7.387m | 3.867ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 12.222m | 6.829ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 54.355m | 18.972ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 3.323m | 3.041ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 13.089m | 7.306ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 3.248m | 2.888ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 18.456m | 9.094ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 4.105m | 3.157ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 8.499m | 5.332ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 3.330m | 2.585ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_ast_usb_clk_calib | chip_sw_usb_ast_clk_calib | 3.784m | 3.129ms | 1 | 1 | 100.00 |
| V2 | chip_sw_sensor_ctrl_ast_alerts | chip_sw_sensor_ctrl_alert | 9.521m | 5.658ms | 5 | 5 | 100.00 |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 5.416m | 4.714ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sensor_ctrl_ast_status | chip_sw_sensor_ctrl_status | 3.646m | 2.733ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 5.416m | 4.714ms | 3 | 3 | 100.00 |
| V2 | chip_sw_smoketest | chip_sw_flash_scrambling_smoketest | 3.377m | 3.426ms | 3 | 3 | 100.00 |
| chip_sw_aes_smoketest | 3.749m | 3.760ms | 3 | 3 | 100.00 | ||
| chip_sw_aon_timer_smoketest | 4.323m | 3.701ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_smoketest | 3.278m | 2.887ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_smoketest | 3.422m | 3.402ms | 3 | 3 | 100.00 | ||
| chip_sw_entropy_src_smoketest | 6.777m | 4.369ms | 3 | 3 | 100.00 | ||
| chip_sw_gpio_smoketest | 3.373m | 3.172ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_smoketest | 4.681m | 3.435ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_smoketest | 3.722m | 3.482ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_smoketest | 20.130m | 8.034ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 6.229m | 5.723ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_usbdev_smoketest | 6.240m | 5.531ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_plic_smoketest | 3.422m | 2.704ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_timer_smoketest | 2.737m | 2.815ms | 3 | 3 | 100.00 | ||
| chip_sw_rstmgr_smoketest | 2.649m | 2.708ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_smoketest | 2.984m | 3.131ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest | 3.736m | 2.876ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_smoketest | chip_sw_otp_ctrl_smoketest | 3.532m | 2.582ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 7.079m | 4.551ms | 3 | 3 | 100.00 |
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 3.816h | 80.557ms | 3 | 3 | 100.00 |
| V2 | chip_sw_secure_boot | rom_e2e_smoke | 51.928m | 15.457ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_raw_unlock | rom_raw_unlock | 3.004m | 5.667ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_idle_load | chip_sw_power_idle_load | 8.031m | 4.581ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_sleep_load | chip_sw_power_sleep_load | 5.599m | 5.160ms | 3 | 3 | 100.00 |
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 2.773h | 59.974ms | 3 | 3 | 100.00 |
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 3.249h | 64.046ms | 3 | 3 | 100.00 |
| V2 | tl_d_oob_addr_access | chip_tl_errors | 6.178m | 5.432ms | 30 | 30 | 100.00 |
| V2 | tl_d_illegal_access | chip_tl_errors | 6.178m | 5.432ms | 30 | 30 | 100.00 |
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 2.307h | 53.329ms | 5 | 5 | 100.00 |
| chip_same_csr_outstanding | 51.594m | 29.364ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 5.263m | 7.383ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 8.415m | 6.827ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | chip_csr_aliasing | 2.307h | 53.329ms | 5 | 5 | 100.00 |
| chip_same_csr_outstanding | 51.594m | 29.364ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 5.263m | 7.383ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 8.415m | 6.827ms | 20 | 20 | 100.00 | ||
| V2 | xbar_base_random_sequence | xbar_random | 1.141m | 2.512ms | 100 | 100 | 100.00 |
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 5.890s | 57.329us | 100 | 100 | 100.00 |
| xbar_smoke_large_delays | 1.562m | 11.154ms | 100 | 100 | 100.00 | ||
| xbar_smoke_slow_rsp | 1.523m | 7.833ms | 100 | 100 | 100.00 | ||
| xbar_random_zero_delays | 39.500s | 594.824us | 100 | 100 | 100.00 | ||
| xbar_random_large_delays | 16.504m | 120.315ms | 100 | 100 | 100.00 | ||
| xbar_random_slow_rsp | 15.110m | 69.761ms | 100 | 100 | 100.00 | ||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 45.660s | 1.488ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 44.370s | 1.429ms | 100 | 100 | 100.00 | ||
| V2 | xbar_error_cases | xbar_error_random | 1.134m | 2.699ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 44.370s | 1.429ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 1.759m | 3.514ms | 100 | 100 | 100.00 |
| xbar_access_same_device_slow_rsp | 30.559m | 156.531ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 57.510s | 2.715ms | 100 | 100 | 100.00 |
| V2 | xbar_stress_all | xbar_stress_all | 8.014m | 18.325ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_error | 7.798m | 16.993ms | 100 | 100 | 100.00 | ||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 12.867m | 24.693ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_reset_error | 12.819m | 29.062ms | 100 | 100 | 100.00 | ||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 51.928m | 15.457ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 46.946m | 29.939ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 49.617m | 14.391ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 38.593m | 11.270ms | 1 | 1 | 100.00 |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 54.405m | 15.116ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 53.210m | 15.704ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 49.259m | 15.349ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 49.026m | 14.665ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 37.000m | 12.211ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 52.927m | 15.370ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 53.703m | 15.681ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 48.951m | 15.079ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 50.005m | 14.737ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 1.111h | 18.296ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 1.465h | 24.102ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 1.381h | 23.913ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 1.470h | 23.912ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 1.469h | 23.032ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 1.176h | 18.365ms | 1 | 1 | 100.00 |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 1.445h | 23.347ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 1.423h | 23.158ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 1.518h | 23.293ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 1.404h | 23.343ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 35.746m | 11.630ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 48.418m | 15.249ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 48.809m | 13.627ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 49.133m | 15.055ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 46.235m | 13.524ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 33.022m | 11.346ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 48.291m | 14.382ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 47.067m | 14.902ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 48.237m | 14.724ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 42.821m | 13.905ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 38.801m | 11.576ms | 3 | 3 | 100.00 |
| rom_e2e_asm_init_dev | 52.028m | 15.914ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod | 53.132m | 15.639ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod_end | 53.946m | 15.876ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_rma | 50.160m | 14.987ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 51.424m | 15.498ms | 3 | 3 | 100.00 |
| rom_e2e_keymgr_init_rom_ext_no_meas | 53.135m | 14.785ms | 3 | 3 | 100.00 | ||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 50.051m | 15.503ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 58.394m | 17.769ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 3.763m | 2.362ms | 3 | 3 | 100.00 |
| chip_sw_aes_enc_jitter_en | 3.323m | 3.041ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_aes_multi_block | chip_sw_aes_multi_block | 0 | 0 | -- | ||
| V2 | chip_sw_aes_interrupt_encryption | chip_sw_aes_interrupt_encryption | 0 | 0 | -- | ||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 2.879m | 2.325ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_prng_reseed | chip_sw_aes_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_force_prng_reseed | chip_sw_aes_force_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 3.366m | 2.653ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_sideload | chip_sw_keymgr_sideload_aes | 25.019m | 10.116ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_debug_cable_irq | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 9.112m | 19.087ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 9.112m | 19.087ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 5.193m | 4.609ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wakeup | chip_sw_pwrmgr_smoketest | 6.229m | 5.723ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 5.193m | 4.609ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 11.024m | 7.289ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 11.024m | 7.289ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 6.526m | 6.807ms | 5 | 5 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 8.146m | 6.159ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_otbn_randomness | 10.519m | 5.700ms | 3 | 3 | 100.00 |
| chip_sw_aes_idle | 3.366m | 2.653ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_idle | 3.450m | 2.829ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_idle | 3.173m | 2.772ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 6.155m | 5.016ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_off_hmac_trans | 6.168m | 5.907ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_kmac_trans | 6.655m | 5.472ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_otbn_trans | 5.899m | 4.508ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_peri | chip_sw_clkmgr_off_peri | 17.478m | 13.314ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_div | chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 7.638m | 4.292ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 7.501m | 4.574ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 7.939m | 4.959ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 7.318m | 4.488ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 7.541m | 4.028ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 7.527m | 4.564ms | 3 | 3 | 100.00 | ||
| chip_sw_ast_clk_outputs | 11.958m | 8.356ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_external_clk_src_for_lc | chip_sw_clkmgr_external_clk_src_for_lc | 11.475m | 9.494ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_external_clk_src_for_sw | chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 7.939m | 4.959ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 7.318m | 4.488ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_jitter | chip_sw_flash_ctrl_ops_jitter_en | 7.387m | 3.867ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 12.222m | 6.829ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 54.355m | 18.972ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 3.323m | 3.041ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 13.089m | 7.306ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 3.248m | 2.888ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 18.456m | 9.094ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 4.105m | 3.157ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 8.499m | 5.332ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 3.330m | 2.585ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 2.765m | 2.781ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 8.144m | 5.165ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 13.531m | 8.070ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 55.727m | 24.702ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 3.490m | 3.670ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 2.839m | 2.810ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 22.197m | 12.317ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 3.716m | 3.532ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 6.527m | 5.153ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_init_reduced_freq | 25.100m | 18.685ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 4.921h | 153.179ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 11.958m | 8.356ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 7.592m | 5.143ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 4.846m | 3.267ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 8.828m | 5.881ms | 97 | 100 | 97.00 |
| V2 | chip_sw_clkmgr_alert_handler_clock_enables | chip_sw_alert_handler_lpg_clkoff | 21.135m | 7.533ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 20.616m | 7.426ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 6.669m | 5.376ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_lc_hw_debug_en | chip_sw_csrng_lc_hw_debug_en_test | 9.381m | 7.877ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 3.881m | 3.527ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 13.143m | 8.790ms | 3 | 3 | 100.00 |
| chip_sw_sysrst_ctrl_reset | 21.036m | 23.015ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sysrst_ctrl_inputs | chip_sw_sysrst_ctrl_inputs | 4.015m | 2.969ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_outputs | chip_sw_sysrst_ctrl_outputs | 4.279m | 3.812ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_in_irq | chip_sw_sysrst_ctrl_in_irq | 6.939m | 4.270ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_wakeup | chip_sw_sysrst_ctrl_reset | 21.036m | 23.015ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_reset | chip_sw_sysrst_ctrl_reset | 21.036m | 23.015ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ec_rst_l | chip_sw_sysrst_ctrl_ec_rst_l | 42.774m | 21.142ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_flash_wp_l | chip_sw_sysrst_ctrl_ec_rst_l | 42.774m | 21.142ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ulp_z3_wakeup | chip_sw_sysrst_ctrl_ulp_z3_wakeup | 5.737m | 5.505ms | 3 | 3 | 100.00 |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 9.112m | 19.087ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 1.517h | 26.880ms | 10 | 10 | 100.00 |
| chip_sw_entropy_src_ast_rng_req | 3.168m | 3.088ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs | 15.595m | 7.232ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_entropy_src_ast_rng_req | chip_sw_entropy_src_ast_rng_req | 3.168m | 3.088ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 20.616m | 7.426ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fuse_en_fw_read | chip_sw_entropy_src_fuse_en_fw_read_test | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_known_answer_tests | chip_sw_entropy_src_kat_test | 3.218m | 3.152ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fw_observe_many_contiguous | chip_sw_entropy_src_fw_observe_many_contiguous | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_fw_extract_and_insert | chip_sw_entropy_src_fw_extract_and_insert | 0 | 0 | -- | ||
| V2 | chip_sw_flash_init | chip_sw_flash_init | 25.702m | 24.792ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_host_access | chip_sw_flash_ctrl_access | 11.567m | 5.937ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 12.222m | 6.829ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_ctrl_ops | chip_sw_flash_ctrl_ops | 7.671m | 4.457ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en | 7.387m | 3.867ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_rma_unlocked | chip_sw_flash_rma_unlocked | 1.181h | 44.754ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_scramble | chip_sw_flash_init | 25.702m | 24.792ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_idle_low_power | chip_sw_flash_ctrl_idle_low_power | 4.649m | 4.173ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_keymgr_seeds | chip_sw_keymgr_key_derivation | 26.110m | 9.926ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_creator_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 6.693m | 5.021ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_creator_seed_wipe_on_rma | chip_sw_flash_rma_unlocked | 1.181h | 44.754ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_owner_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 6.693m | 5.021ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 6.693m | 5.021ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_wr_en | chip_sw_flash_ctrl_lc_rw_en | 6.693m | 5.021ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_seed_hw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 6.693m | 5.021ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_escalate_en | chip_sw_all_escalation_resets | 8.828m | 5.881ms | 97 | 100 | 97.00 |
| V2 | chip_sw_flash_prim_tl_access | chip_prim_tl_access | 5.001m | 10.265ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_clock_freqs | chip_sw_flash_ctrl_clock_freqs | 11.875m | 5.544ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_escalation_reset | chip_sw_flash_crash_alert | 7.621m | 4.480ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_write_clear | chip_sw_flash_crash_alert | 7.621m | 4.480ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 4.328m | 3.656ms | 3 | 3 | 100.00 |
| chip_sw_hmac_enc_jitter_en | 3.248m | 2.888ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 3.450m | 2.829ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_all_configurations | chip_sw_hmac_oneshot | 4.331m | 2.848ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_multistream_mode | chip_sw_hmac_multistream | 19.934m | 8.449ms | 3 | 3 | 100.00 |
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 11.071m | 5.871ms | 3 | 3 | 100.00 |
| chip_sw_i2c_host_tx_rx_idx1 | 9.347m | 5.229ms | 3 | 3 | 100.00 | ||
| chip_sw_i2c_host_tx_rx_idx2 | 9.340m | 5.345ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 7.566m | 4.318ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_key_derivation | chip_sw_keymgr_key_derivation | 26.110m | 9.926ms | 3 | 3 | 100.00 |
| chip_sw_keymgr_key_derivation_jitter_en | 18.456m | 9.094ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_keymgr_sideload_kmac | chip_sw_keymgr_sideload_kmac | 34.132m | 13.506ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_aes | chip_sw_keymgr_sideload_aes | 25.019m | 10.116ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_otbn | chip_sw_keymgr_sideload_otbn | 1.008h | 16.938ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 3.437m | 3.029ms | 3 | 3 | 100.00 |
| chip_sw_kmac_mode_kmac | 4.458m | 3.614ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 4.105m | 3.157ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_key_derivation | 26.110m | 9.926ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 13.709m | 13.946ms | 15 | 15 | 100.00 |
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 3.255m | 2.758ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 3.470m | 3.283ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 3.173m | 2.772ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 6.749m | 5.672ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_jtag_access | chip_tap_straps_dev | 3.817m | 3.747ms | 5 | 5 | 100.00 |
| chip_tap_straps_rma | 6.441m | 6.023ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 22.790m | 17.762ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_otp_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 3.554m | 3.084ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 13.709m | 13.946ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 13.709m | 13.946ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 13.709m | 13.946ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_key_derivation_prod | 23.962m | 9.670ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_broadcast | chip_sw_flash_ctrl_lc_rw_en | 6.693m | 5.021ms | 3 | 3 | 100.00 |
| chip_sw_flash_rma_unlocked | 1.181h | 44.754ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 8.535m | 5.055ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_dev | 13.620m | 6.941ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 16.135m | 7.340ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 14.643m | 8.505ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 13.709m | 13.946ms | 15 | 15 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 26.110m | 9.926ms | 3 | 3 | 100.00 | ||
| chip_sw_rom_ctrl_integrity_check | 7.041m | 7.847ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_execution_main | 11.721m | 9.482ms | 3 | 3 | 100.00 | ||
| chip_prim_tl_access | 5.001m | 10.265ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_lc | 11.475m | 9.494ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 7.638m | 4.292ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 7.501m | 4.574ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 7.939m | 4.959ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 7.318m | 4.488ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 7.541m | 4.028ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 7.527m | 4.564ms | 3 | 3 | 100.00 | ||
| chip_tap_straps_dev | 3.817m | 3.747ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 6.441m | 6.023ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 22.790m | 17.762ms | 5 | 5 | 100.00 | ||
| chip_rv_dm_lc_disabled | 5.378m | 12.527ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 3.578m | 3.438ms | 1 | 1 | 100.00 |
| chip_sw_lc_ctrl_raw_to_scrap | 1.801m | 3.564ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 1.732m | 3.388ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_rand_to_scrap | 3.267m | 3.312ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_test_locked | chip_sw_lc_walkthrough_testunlocks | 24.429m | 23.361ms | 3 | 3 | 100.00 |
| chip_rv_dm_lc_disabled | 5.378m | 12.527ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 1.264h | 47.532ms | 3 | 3 | 100.00 |
| chip_sw_lc_walkthrough_prod | 1.290h | 51.509ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_prodend | 11.189m | 11.290ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_rma | 1.254h | 48.915ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_testunlocks | 24.429m | 23.361ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 1.690m | 2.643ms | 3 | 3 | 100.00 |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 1.448m | 2.365ms | 3 | 3 | 100.00 | ||
| rom_volatile_raw_unlock | 1.550m | 2.493ms | 3 | 3 | 100.00 | ||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 13.709m | 13.946ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_keys | chip_sw_flash_init | 25.702m | 24.792ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 6.073m | 3.373ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 26.110m | 9.926ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 8.377m | 5.070ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 3.006m | 3.111ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_flash_init | 25.702m | 24.792ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 6.073m | 3.373ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 26.110m | 9.926ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 8.377m | 5.070ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 3.006m | 3.111ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 13.709m | 13.946ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 5.390m | 4.731ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 3.554m | 3.084ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_lc_signals | chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 8.535m | 5.055ms | 3 | 3 | 100.00 |
| chip_sw_otp_ctrl_lc_signals_dev | 13.620m | 6.941ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 16.135m | 7.340ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 14.643m | 8.505ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 13.709m | 13.946ms | 15 | 15 | 100.00 | ||
| chip_prim_tl_access | 5.001m | 10.265ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 5.001m | 10.265ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_dai_lock | chip_sw_otp_ctrl_dai_lock | 1.215h | 27.191ms | 1 | 1 | 100.00 |
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 6.582m | 9.604ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_wake_ups | chip_sw_pwrmgr_random_sleep_all_wake_ups | 17.560m | 23.961ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_wake_ups | chip_sw_pwrmgr_normal_sleep_all_wake_ups | 6.331m | 7.864ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_por_reset | chip_sw_pwrmgr_deep_sleep_por_reset | 9.090m | 8.354ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_por_reset | chip_sw_pwrmgr_normal_sleep_por_reset | 9.112m | 7.872ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_wake_ups | chip_sw_pwrmgr_deep_sleep_all_wake_ups | 19.057m | 23.344ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 17.198m | 18.016ms | 3 | 3 | 100.00 |
| chip_sw_aon_timer_wdog_bite_reset | 11.024m | 7.289ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 18.861m | 11.608ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 5.782m | 5.052ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 6.582m | 9.604ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 5.349m | 4.204ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 31.100m | 26.554ms | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 5.757m | 5.546ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 3.788m | 3.655ms | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_reset_reqs | chip_sw_pwrmgr_random_sleep_all_reset_reqs | 27.549m | 26.130ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 13.143m | 8.790ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_all_reset_reqs | 17.951m | 12.360ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_b2b_sleep_reset_req | chip_sw_pwrmgr_b2b_sleep_reset_req | 31.962m | 28.356ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 3.713m | 3.182ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 8.828m | 5.881ms | 97 | 100 | 97.00 |
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 7.041m | 7.847ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 7.041m | 7.847ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_non_sys_reset_info | chip_sw_pwrmgr_all_reset_reqs | 17.951m | 12.360ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 27.549m | 26.130ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_wdog_reset | 5.782m | 5.052ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 6.229m | 5.723ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 5.318m | 4.412ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 8.690m | 7.051ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 4.780m | 4.370ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 22.883m | 13.009ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 2.903m | 2.645ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 8.828m | 5.881ms | 97 | 100 | 97.00 |
| V2 | chip_sw_rstmgr_alert_handler_reset_enables | chip_sw_alert_handler_lpg_reset_toggle | 19.847m | 7.894ms | 3 | 3 | 100.00 |
| V2 | chip_sw_plic_all_irqs | chip_plic_all_irqs_0 | 13.832m | 6.043ms | 3 | 3 | 100.00 |
| chip_plic_all_irqs_10 | 7.946m | 3.678ms | 3 | 3 | 100.00 | ||
| chip_plic_all_irqs_20 | 8.984m | 4.888ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 4.118m | 3.114ms | 3 | 3 | 100.00 |
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 3.495m | 2.801ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_flash_mode | rom_e2e_smoke | 51.928m | 15.457ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 9.200m | 7.727ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 6.915m | 4.388ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 4.535m | 3.725ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 3.411m | 3.230ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 8.377m | 5.070ms | 3 | 3 | 100.00 |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 8.499m | 5.332ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sleep_sram_ret_contents | chip_sw_sleep_sram_ret_contents_no_scramble | 6.885m | 7.249ms | 3 | 3 | 100.00 |
| chip_sw_sleep_sram_ret_contents_scramble | 9.078m | 7.670ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 11.721m | 9.482ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 8.828m | 5.881ms | 97 | 100 | 97.00 |
| chip_sw_data_integrity_escalation | 9.081m | 6.410ms | 6 | 6 | 100.00 | ||
| V2 | chip_sw_usbdev_mem | chip_sw_usbdev_mem | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_vbus | chip_sw_usbdev_vbus | 2.111m | 2.632ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pullup | chip_sw_usbdev_pullup | 2.974m | 2.697ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_aon_pullup | chip_sw_usbdev_aon_pullup | 4.561m | 3.645ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_sof | chip_sw_usbdev_sof | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_setup_rx | chip_sw_usbdev_setuprx | 6.127m | 4.250ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_config_host | chip_sw_usbdev_config_host | 18.846m | 8.280ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pincfg | chip_sw_usbdev_pincfg | 1.728h | 31.481ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_tx_rx | chip_sw_usbdev_dpi | 33.203m | 11.985ms | 1 | 1 | 100.00 |
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 4.505m | 3.825ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 6.749m | 5.672ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalation_nmi_reset | chip_sw_alert_handler_escalation_nmi_reset | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_escalation_methods | chip_sw_alert_handler_escalation_methods | 0 | 0 | -- | ||
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 8.828m | 5.881ms | 97 | 100 | 97.00 |
| V2 | chip_sw_alert_handler_irqs | chip_plic_all_irqs | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 3.680m | 3.194ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 22.883m | 13.009ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 6.046m | 5.271ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 5.917m | 4.069ms | 89 | 90 | 98.89 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 14.625m | 11.181ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 21.135m | 7.533ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 19.847m | 7.894ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_ok | chip_sw_alert_handler_ping_ok | 17.634m | 7.918ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 3.305h | 254.962ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 24.300m | 20.559ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 16.875m | 14.010ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 5.318m | 4.412ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 6.316m | 4.881ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 6.625m | 6.386ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_jtag_tap_sel | chip_tap_straps_rma | 6.441m | 6.023ms | 5 | 5 | 100.00 |
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 5.378m | 12.527ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_jtag | chip_rv_dm_jtag | 0 | 0 | -- | ||
| V2 | chip_rv_dm_dtm | chip_rv_dm_dtm | 0 | 0 | -- | ||
| V2 | chip_rv_dm_control_status | chip_rv_dm_control_status | 0 | 0 | -- | ||
| V2 | TOTAL | 2634 | 2644 | 99.62 | |||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 4.264m | 3.215ms | 3 | 3 | 100.00 |
| V2S | TOTAL | 3 | 3 | 100.00 | |||
| V3 | chip_sw_usb_suspend | chip_sw_usb_suspend | 0 | 0 | -- | ||
| V3 | chip_sw_coremark | chip_sw_coremark | 4.014h | 71.604ms | 1 | 1 | 100.00 |
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 18.100m | 5.628ms | 3 | 3 | 100.00 |
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 24.434m | 11.924ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 23.108m | 10.948ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 22.401m | 10.901ms | 1 | 1 | 100.00 | ||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 35.656m | 32.215ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_inject_dev | 43.471m | 31.024ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_inject_rma | 49.974m | 40.168ms | 1 | 1 | 100.00 | ||
| V3 | rom_bootstrap_rma | rom_bootstrap_rma | 0 | 0 | -- | ||
| V3 | rom_e2e_weak_straps | rom_e2e_weak_straps | 0 | 0 | -- | ||
| V3 | rom_e2e_self_hash | rom_e2e_self_hash | 1.514h | 26.465ms | 3 | 3 | 100.00 |
| V3 | manuf_cp_unlock_raw | manuf_cp_unlock_raw | 0 | 0 | -- | ||
| V3 | manuf_scrap | manuf_scrap | 0 | 0 | -- | ||
| V3 | manuf_cp_yield_test | manuf_cp_yield_test | 0 | 0 | -- | ||
| V3 | manuf_cp_ast_test_execution | manuf_cp_ast_test_execution | 0 | 0 | -- | ||
| V3 | manuf_cp_device_info_flash_wr | manuf_cp_device_info_flash_wr | 0 | 0 | -- | ||
| V3 | manuf_cp_test_lock | manuf_cp_test_lock | 0 | 0 | -- | ||
| V3 | manuf_ft_exit_token | manuf_ft_exit_token | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization_preop | manuf_ft_sku_individualization_preop | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization | manuf_ft_sku_individualization | 0 | 0 | -- | ||
| V3 | manuf_ft_provision_rma_token_and_personalization | manuf_ft_provision_rma_token_and_personalization | 0 | 0 | -- | ||
| V3 | manuf_ft_load_transport_image | manuf_ft_load_transport_image | 0 | 0 | -- | ||
| V3 | manuf_ft_load_certificates | manuf_ft_load_certificates | 0 | 0 | -- | ||
| V3 | manuf_ft_eom | manuf_ft_eom | 0 | 0 | -- | ||
| V3 | manuf_rma_entry | manuf_rma_entry | 0 | 0 | -- | ||
| V3 | manuf_sram_program_crc_functest | manuf_sram_program_crc_functest | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_normal | chip_sw_adc_ctrl_normal | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_oneshot | chip_sw_adc_ctrl_oneshot | 0 | 0 | -- | ||
| V3 | chip_sw_clkmgr_jitter_cycle_measurements | chip_sw_clkmgr_jitter_frequency | 5.364m | 3.730ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_boot_mode | chip_sw_edn_boot_mode | 6.570m | 3.349ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_auto_mode | chip_sw_edn_auto_mode | 23.321m | 7.940ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_sw_mode | chip_sw_edn_sw_mode | 25.939m | 10.098ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_kat | chip_sw_edn_kat | 7.892m | 3.581ms | 3 | 3 | 100.00 |
| V3 | chip_sw_entropy_src_bypass_mode_health_tests | chip_sw_entropy_src_bypass_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_fips_mode_health_tests | chip_sw_entropy_src_fips_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_validation | chip_sw_entropy_src_validation | 0 | 0 | -- | ||
| V3 | chip_sw_flash_memory_protection | chip_sw_flash_ctrl_mem_protection | 13.106m | 5.303ms | 3 | 3 | 100.00 |
| V3 | chip_sw_hmac_sha2_stress | chip_sw_hmac_sha2_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_stress | chip_sw_hmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_endianness | chip_sw_hmac_endianness | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_secure_wipe | chip_sw_hmac_secure_wipe | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_error_conditions | chip_sw_hmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_speed | chip_sw_i2c_speed | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_override | chip_sw_i2c_override | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_clockstretching | chip_sw_i2c_clockstretching | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_nack | chip_sw_i2c_nack | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_repeatedstart | chip_sw_i2c_repeatedstart | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_sideload_kmac_error | chip_sw_keymgr_sideload_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_attestation | chip_sw_keymgr_derive_attestation | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_sealing | chip_sw_keymgr_derive_sealing | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_sha3_stress | chip_sw_kmac_sha3_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_shake_stress | chip_sw_kmac_shake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_cshake_stress | chip_sw_kmac_cshake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_stress | chip_sw_kmac_kmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_key_sideload | chip_sw_kmac_kmac_key_sideload | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_endianess | chip_sw_kmac_endianess | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_entropy_stress | chip_sw_kmac_entropy_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_error_conditions | chip_sw_kmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_kmac_error | chip_sw_lc_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_debug_access | chip_sw_lc_ctrl_debug_access | 0 | 0 | -- | ||
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 2.628m | 2.893ms | 3 | 3 | 100.00 |
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 7.136m | 4.877ms | 1 | 1 | 100.00 |
| V3 | otp_ctrl_calibration | otp_ctrl_calibration | 0 | 0 | -- | ||
| V3 | otp_ctrl_partition_access_locked | otp_ctrl_partition_access_locked | 0 | 0 | -- | ||
| V3 | otp_ctrl_check_timeout | otp_ctrl_check_timeout | 0 | 0 | -- | ||
| V3 | chip_sw_sensor_ctrl_deep_sleep_wake_up | chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up | 5.972m | 5.162ms | 3 | 3 | 100.00 |
| V3 | chip_sw_pwrmgr_usb_clk_disabled_when_active | chip_sw_pwrmgr_usb_clk_disabled_when_active | 5.802m | 4.814ms | 3 | 3 | 100.00 |
| V3 | chip_sw_all_resets | chip_sw_pwrmgr_all_reset_reqs | 17.951m | 12.360ms | 3 | 3 | 100.00 |
| V3 | chip_sw_rom_ctrl_kmac_error | chip_sw_rom_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_rom_ctrl_digests | chip_sw_rom_ctrl_digests | 0 | 0 | -- | ||
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 8.828m | 5.881ms | 97 | 100 | 97.00 |
| V3 | tick_configuration | chip_sw_rv_timer_systick_test | 1.937h | 38.433ms | 3 | 3 | 100.00 |
| V3 | counter_wrap | chip_sw_rv_timer_systick_test | 1.937h | 38.433ms | 3 | 3 | 100.00 |
| V3 | chip_sw_spi_device_pass_through_flash_model | //sw/device/tests:spi_passthru_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_device_output_when_disabled_or_sleeping | chip_sw_spi_device_pinmux_sleep_retention | 3.919m | 3.736ms | 3 | 3 | 100.00 |
| V3 | chip_sw_spi_host_pass_through | //sw/device/tests:spi_passthru_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_configuration | //sw/device/tests:spi_host_config_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_events | chip_sw_spi_host_events | 0 | 0 | -- | ||
| V3 | chip_sw_sram_memset | chip_sw_sram_memset | 0 | 0 | -- | ||
| V3 | chip_sw_sram_readback | chip_sw_sram_readback | 0 | 0 | -- | ||
| V3 | chip_sw_sram_subword_access | chip_sw_sram_subword_access | 0 | 0 | -- | ||
| V3 | chip_sw_uart_parity | chip_sw_uart_parity | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_loopback | chip_sw_uart_line_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_system_loopback | chip_sw_uart_system_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_break | chip_sw_uart_line_break | 0 | 0 | -- | ||
| V3 | chip_sw_uart_watermarks | chip_sw_uart_tx_rx | 7.317m | 4.873ms | 5 | 5 | 100.00 |
| V3 | chip_sw_usbdev_stream | chip_sw_usbdev_stream | 55.886m | 19.067ms | 1 | 1 | 100.00 |
| V3 | chip_sw_usbdev_iso | chip_sw_usbdev_iso | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_mixed | chip_sw_usbdev_mixed | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_suspend_resume | chip_sw_usbdev_suspend_resume | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_reset | chip_sw_usbdev_aon_wake_reset | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_disconnect | chip_sw_usbdev_aon_wake_disconnect | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_toggle_restore | chip_sw_usbdev_toggle_restore | 0 | 0 | -- | ||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 24.434m | 11.924ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 23.108m | 10.948ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 22.401m | 10.901ms | 1 | 1 | 100.00 | ||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 6.868m | 5.471ms | 3 | 3 | 100.00 |
| V3 | TOTAL | 51 | 51 | 100.00 | |||
| Unmapped tests | chip_sival_flash_info_access | 3.808m | 3.517ms | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_rst_cnsty_escalation | 8.127m | 5.601ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_ecc_error_vendor_test | 3.543m | 2.514ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq | 53.621m | 16.745ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_rnd | 11.775m | 6.050ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_nmi_irq | 9.555m | 4.603ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_lowpower_cancel | 5.719m | 4.255ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_sleep_wake_5_bug | 6.328m | 5.827ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_address_translation | 3.751m | 2.375ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_lockstep_glitch | 2.251m | 2.888ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_write_clear | 3.901m | 3.613ms | 3 | 3 | 100.00 | ||
| TOTAL | 2941 | 2951 | 99.66 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 11 | 11 | 11 | 100.00 |
| V1 | 18 | 18 | 18 | 100.00 |
| V2 | 285 | 270 | 266 | 93.33 |
| V2S | 1 | 1 | 1 | 100.00 |
| V3 | 90 | 23 | 23 | 25.56 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.27 | 95.58 | 94.38 | 95.46 | -- | 95.27 | 97.35 | 99.58 |
UVM_ERROR @ * us: (rom_ctrl_fsm.sv:209) [ASSERT FAILED] SecCmCFILinear_A has 6 failures:
0.chip_sw_pwrmgr_sleep_power_glitch_reset.107628854066629719360621874838775428251752366637961962683320862485160699277129
Line 399, in log /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log
UVM_ERROR @ 3285.726436 us: (rom_ctrl_fsm.sv:209) [ASSERT FAILED] SecCmCFILinear_A
UVM_INFO @ 3285.726436 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_pwrmgr_sleep_power_glitch_reset.90008474350885617341804144246708399695251052454982087995373185929362851981398
Line 399, in log /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log
UVM_ERROR @ 3040.949977 us: (rom_ctrl_fsm.sv:209) [ASSERT FAILED] SecCmCFILinear_A
UVM_INFO @ 3040.949977 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.46630169864168189543399369486447765247306175083964466500093540657461972846880
Line 416, in log /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log
UVM_ERROR @ 10422.022280 us: (rom_ctrl_fsm.sv:209) [ASSERT FAILED] SecCmCFILinear_A
UVM_INFO @ 10422.022280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.89924209498323938281261630611840080739887820610631363514601139912424580463690
Line 432, in log /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log
UVM_ERROR @ 13779.279160 us: (rom_ctrl_fsm.sv:209) [ASSERT FAILED] SecCmCFILinear_A
UVM_INFO @ 13779.279160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 3 failures:
23.chip_sw_all_escalation_resets.99843302403494577745535662941372854585762247129196751582375172187386442766671
Line 395, in log /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/23.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 3311.662372 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 3311.662372 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.chip_sw_all_escalation_resets.93616178150189697189509045109909276697932025371369756825139009997635793847690
Line 399, in log /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/29.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 3720.007448 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 3720.007448 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 1 failures:
44.chip_sw_alert_handler_lpg_sleep_mode_alerts.43061476727832435428208250742324007728988580454836822958749413412589429622203
Line 407, in log /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
UVM_ERROR @ 3992.380580 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=2000371c MTVAL=40600800
UVM_INFO @ 3992.380580 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---