Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3690413	1			T94	98		T95	71		T96	99
values[2]	722184	1			T94	48		T95	42		T96	16
values[3]	101108	1			T95	2		T96	1		T99	1
values[4]	54971	1			T286	27		T427	172		T565	1
values[5]	37755	1			T286	6		T427	111		T669	161
values[6]	28418	1			T286	2		T427	62		T669	91
values[7]	23324	1			T427	37		T669	99		T579	26
values[8]	19988	1			T427	27		T669	68		T579	33
values[9]	17403	1			T427	26		T669	55		T579	17
values[10]	15875	1			T427	41		T669	49		T579	12
values[11]	14779	1			T427	43		T669	38		T579	25
values[12]	13994	1			T427	27		T669	33		T579	27
values[13]	13146	1			T427	15		T669	18		T579	21
values[14]	12449	1			T427	15		T669	15		T579	14
values[15]	12292	1			T427	9		T669	21		T579	8
values[16]	11476	1			T427	8		T669	20		T579	11
values[17]	10972	1			T427	11		T669	11		T579	17
values[18]	10442	1			T427	9		T669	15		T579	36
values[19]	10282	1			T427	7		T669	20		T579	35
values[20]	10046	1			T427	4		T669	17		T579	28
values[21]	9592	1			T427	5		T669	12		T579	27
values[22]	9221	1			T427	13		T669	10		T579	7
values[23]	9104	1			T427	19		T669	11		T579	24
values[24]	8825	1			T427	27		T669	8		T579	36
values[25]	8372	1			T427	15		T669	10		T579	11
values[26]	7904	1			T427	4		T669	11		T579	6
values[27]	7463	1			T427	3		T669	8		T579	11
values[28]	7128	1			T427	2		T669	12		T579	15
values[29]	6541	1			T427	7		T669	9		T579	5
values[30]	6299	1			T427	6		T669	7		T579	6
values[31]	5779	1			T427	9		T669	9		T579	3
values[32]	5525	1			T427	3		T669	8		T579	9
values[33]	5374	1			T427	6		T669	8		T579	16
values[34]	4915	1			T427	4		T669	9		T579	22
values[35]	4621	1			T427	7		T669	10		T579	16
values[36]	4443	1			T427	6		T669	13		T579	5
values[37]	4122	1			T427	3		T669	13		T579	4
values[38]	3911	1			T427	3		T669	10		T579	6
values[39]	3769	1			T427	4		T669	10		T579	4
values[40]	3632	1			T427	3		T669	11		T579	4
values[41]	3376	1			T427	4		T669	10		T579	2
values[42]	3263	1			T427	7		T669	12		T579	3
values[43]	3262	1			T427	4		T669	10		T579	4
values[44]	3190	1			T427	5		T669	10		T579	2
values[45]	3144	1			T427	5		T669	11		T579	1
values[46]	3103	1			T427	6		T669	12		T579	3
values[47]	2982	1			T427	7		T669	9		T579	3
values[48]	2936	1			T427	2		T669	11		T579	1
values[49]	2762	1			T427	4		T669	8		T579	1
values[50]	2763	1			T427	7		T669	10		T579	2
values[51]	2751	1			T427	5		T669	10		T579	2
values[52]	2702	1			T427	3		T669	9		T579	1
values[53]	2688	1			T427	1		T669	12		T579	3
values[54]	2619	1			T427	5		T669	10		T579	2
values[55]	2552	1			T427	7		T669	11		T579	3
values[56]	2459	1			T427	3		T669	9		T579	2
values[57]	2456	1			T427	1		T669	12		T579	4
values[58]	2404	1			T427	1		T669	16		T579	1
values[59]	2311	1			T427	2		T669	11		T579	6
values[60]	2409	1			T427	1		T669	13		T573	7
values[61]	2592	1			T427	1		T669	13		T573	5
values[62]	3806	1			T427	1		T669	26		T573	11
values[63]	10491	1			T427	7		T669	123		T573	67
values[64]	222044	1			T427	62		T669	639		T573	168

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4705198	1			T94	87		T95	153		T96	92
values[2]	789416	1			T94	27		T95	38		T96	30
values[3]	81522	1			T95	6		T96	2		T99	1
values[4]	13553	1			T286	1		T463	2		T427	19
values[5]	4917	1			T463	1		T427	13		T575	2
values[6]	3064	1			T427	13		T575	1		T565	3
values[7]	2390	1			T427	17		T669	2		T573	12
values[8]	2166	1			T427	9		T669	2		T573	8
values[9]	1953	1			T427	6		T669	1		T573	9
values[10]	1709	1			T427	6		T669	1		T573	7
values[11]	1696	1			T427	4		T669	1		T573	8
values[12]	1628	1			T427	7		T669	1		T573	7
values[13]	1455	1			T427	13		T669	1		T573	6
values[14]	1330	1			T427	4		T669	1		T573	1
values[15]	1283	1			T427	2		T669	1		T573	2
values[16]	1178	1			T427	3		T669	1		T573	1
values[17]	1117	1			T427	8		T669	2		T573	2
values[18]	1153	1			T427	8		T669	1		T573	7
values[19]	1033	1			T427	14		T669	2		T573	8
values[20]	968	1			T427	23		T669	2		T573	3
values[21]	964	1			T427	14		T669	3		T573	4
values[22]	846	1			T427	8		T669	1		T573	1
values[23]	717	1			T427	6		T669	1		T572	2
values[24]	697	1			T427	3		T669	1		T572	1
values[25]	744	1			T427	8		T669	2		T572	1
values[26]	678	1			T427	18		T669	1		T572	1
values[27]	683	1			T427	4		T669	2		T572	1
values[28]	664	1			T427	1		T669	3		T572	1
values[29]	620	1			T427	1		T669	2		T572	1
values[30]	614	1			T427	1		T669	2		T572	2
values[31]	679	1			T427	1		T669	6		T572	1
values[32]	712	1			T669	2		T572	1		T578	4
values[33]	671	1			T669	2		T572	1		T578	4
values[34]	621	1			T669	2		T572	4		T578	3
values[35]	626	1			T669	3		T572	5		T578	2
values[36]	580	1			T669	1		T572	4		T578	3
values[37]	538	1			T669	1		T572	2		T578	4
values[38]	500	1			T669	2		T572	2		T578	3
values[39]	495	1			T669	3		T572	1		T578	3
values[40]	456	1			T669	1		T572	1		T578	3
values[41]	468	1			T669	2		T572	1		T578	4
values[42]	484	1			T669	3		T572	2		T578	3
values[43]	440	1			T669	1		T572	1		T578	5
values[44]	430	1			T669	1		T572	1		T578	5
values[45]	446	1			T669	1		T572	1		T578	4
values[46]	451	1			T669	3		T572	1		T578	4
values[47]	442	1			T669	2		T572	1		T578	3
values[48]	445	1			T669	2		T572	5		T578	3
values[49]	398	1			T669	2		T572	3		T578	3
values[50]	365	1			T669	3		T572	2		T578	3
values[51]	400	1			T669	2		T572	2		T578	6
values[52]	424	1			T669	3		T572	2		T578	4
values[53]	404	1			T669	1		T572	1		T578	3
values[54]	374	1			T669	1		T572	2		T578	4
values[55]	376	1			T669	2		T572	2		T578	3
values[56]	401	1			T669	2		T572	1		T578	3
values[57]	414	1			T669	1		T572	4		T578	8
values[58]	375	1			T669	1		T572	7		T578	4
values[59]	387	1			T669	1		T572	3		T578	8
values[60]	414	1			T669	2		T572	2		T578	4
values[61]	487	1			T669	2		T572	4		T578	3
values[62]	700	1			T669	12		T572	6		T578	5
values[63]	2547	1			T669	20		T572	25		T578	19
values[64]	26257	1			T669	66		T572	50		T578	199

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	589323	1			T94	1		T95	1		T96	1
values[2]	2614208	1			T94	90		T95	22		T96	115
values[3]	1148245	1			T94	67		T95	82		T96	31
values[4]	146315	1			T95	2		T286	48		T184	2
values[5]	75110	1			T286	25		T427	161		T575	1
values[6]	48842	1			T286	3		T427	140		T669	188
values[7]	35180	1			T427	72		T669	136		T579	22
values[8]	27823	1			T427	56		T669	108		T579	13
values[9]	24148	1			T427	32		T669	82		T579	27
values[10]	21687	1			T427	22		T669	77		T579	23
values[11]	19554	1			T427	27		T669	44		T579	23
values[12]	17704	1			T427	33		T669	27		T579	13
values[13]	16552	1			T427	30		T669	52		T579	16
values[14]	15623	1			T427	25		T669	43		T579	20
values[15]	14596	1			T427	23		T669	30		T579	23
values[16]	14082	1			T427	15		T669	34		T579	35
values[17]	13350	1			T427	11		T669	20		T579	26
values[18]	12954	1			T427	16		T669	24		T579	23
values[19]	12435	1			T427	17		T669	21		T579	22
values[20]	11894	1			T427	15		T669	15		T579	31
values[21]	11717	1			T427	6		T669	30		T579	19
values[22]	10992	1			T427	5		T669	29		T579	9
values[23]	10464	1			T427	10		T669	25		T579	11
values[24]	10121	1			T427	12		T669	21		T579	19
values[25]	9632	1			T427	25		T669	23		T579	29
values[26]	9155	1			T427	15		T669	24		T579	40
values[27]	8836	1			T427	14		T669	27		T579	27
values[28]	8494	1			T427	15		T669	34		T579	16
values[29]	8227	1			T427	2		T669	34		T579	6
values[30]	7436	1			T427	2		T669	19		T579	9
values[31]	6661	1			T427	5		T669	17		T579	18
values[32]	6200	1			T427	5		T669	13		T579	28
values[33]	5679	1			T427	4		T669	16		T579	18
values[34]	5234	1			T427	5		T669	22		T579	17
values[35]	4942	1			T427	9		T669	33		T579	15
values[36]	4652	1			T427	5		T669	28		T579	10
values[37]	4258	1			T427	1		T669	21		T579	6
values[38]	4021	1			T427	2		T669	18		T579	7
values[39]	3873	1			T427	1		T669	16		T579	3
values[40]	3845	1			T427	1		T669	25		T579	2
values[41]	3654	1			T427	2		T669	17		T573	6
values[42]	3630	1			T427	4		T669	14		T573	5
values[43]	3564	1			T427	1		T669	22		T573	7
values[44]	3515	1			T427	1		T669	28		T573	16
values[45]	3320	1			T427	1		T669	37		T573	10
values[46]	3368	1			T427	2		T669	26		T573	13
values[47]	3287	1			T427	1		T669	21		T573	8
values[48]	3217	1			T427	2		T669	21		T573	11
values[49]	3060	1			T427	2		T669	18		T573	12
values[50]	3110	1			T427	3		T669	24		T573	12
values[51]	3079	1			T427	10		T669	30		T573	8
values[52]	2964	1			T427	10		T669	25		T573	12
values[53]	2916	1			T427	3		T669	35		T573	18
values[54]	2874	1			T427	1		T669	25		T573	14
values[55]	2888	1			T427	1		T669	23		T573	7
values[56]	2827	1			T427	1		T669	21		T573	7
values[57]	2774	1			T427	1		T669	19		T573	9
values[58]	2768	1			T427	3		T669	35		T573	9
values[59]	2651	1			T427	2		T669	14		T573	10
values[60]	2658	1			T427	4		T669	29		T573	14
values[61]	2697	1			T427	8		T669	20		T573	12
values[62]	3774	1			T427	3		T669	23		T573	20
values[63]	9773	1			T427	6		T669	44		T573	67
values[64]	215820	1			T427	102		T669	195		T573	280