Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1958514	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

34773400

1

T1

4630

T2

3027

T3

16270

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	24990750	1			T1	1677		T2	532		T3	12457
values[0x0]	10289689	1			T1	2953		T2	2495		T3	3813
values[0x1]	1451475	1			T1	285		T2	56		T3	3600

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	663651	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

36068263

1

T1

4915

T2

3083

T3

19870

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17209722	1			T1	2458		T2	1542		T3	9935
valid_sources[0x01]	17210042	1			T1	2457		T2	1541		T3	9935
valid_sources[0x02]	36947	1			T35	2		T233	3		T398	24
valid_sources[0x03]	37863	1			T35	1		T98	1		T398	18
valid_sources[0x04]	36626	1			T35	1		T233	1		T234	4
valid_sources[0x05]	37664	1			T234	4		T398	36		T171	78
valid_sources[0x06]	37380	1			T233	1		T71	4		T398	27
valid_sources[0x07]	37333	1			T234	1		T398	29		T171	90
valid_sources[0x08]	37343	1			T35	1		T233	2		T398	18
valid_sources[0x09]	37259	1			T35	1		T233	1		T398	21
valid_sources[0x0a]	37917	1			T35	1		T234	1		T398	23
valid_sources[0x0b]	36626	1			T35	1		T398	20		T171	93
valid_sources[0x0c]	37517	1			T35	1		T398	32		T171	69
valid_sources[0x0d]	36912	1			T71	2		T398	30		T171	65
valid_sources[0x0e]	37782	1			T398	20		T171	83		T558	13
valid_sources[0x0f]	36889	1			T98	3		T398	26		T171	72
valid_sources[0x10]	39041	1			T98	2		T398	22		T171	52
valid_sources[0x11]	36863	1			T71	3		T398	17		T171	83
valid_sources[0x12]	36673	1			T35	1		T233	1		T398	27
valid_sources[0x13]	36970	1			T398	19		T171	68		T558	14
valid_sources[0x14]	37248	1			T98	2		T71	1		T398	28
valid_sources[0x15]	36496	1			T35	3		T98	4		T233	1
valid_sources[0x16]	37461	1			T398	24		T171	58		T558	4
valid_sources[0x17]	36401	1			T35	2		T398	21		T171	76
valid_sources[0x18]	39124	1			T98	1		T233	1		T71	2
valid_sources[0x19]	37373	1			T98	1		T233	4		T234	1
valid_sources[0x1a]	37409	1			T234	3		T398	17		T171	87
valid_sources[0x1b]	36855	1			T398	27		T171	77		T558	5
valid_sources[0x1c]	37839	1			T398	20		T171	67		T558	2
valid_sources[0x1d]	37584	1			T234	5		T398	19		T171	75
valid_sources[0x1e]	38308	1			T234	3		T398	30		T171	100
valid_sources[0x1f]	37887	1			T35	3		T98	3		T234	2
valid_sources[0x20]	36036	1			T398	37		T171	53		T558	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24291754

1

T1

1677

T2

532

T3

12457

values[0x0]

all_enables

biggest_size

10229316

1

T1

2953

T2

2495

T3

3813

values[0x1]

all_enables

biggest_size

252330

1

T35

17

T98

21

T67

18

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2778804	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

440349

1

T94

19

T95

20

T96

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1091118	1			T94	48		T95	42		T96	34
values[0x0]	1037147	1			T94	51		T95	33		T96	40
values[0x1]	1090888	1			T94	47		T95	40		T96	42

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2151027	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1068126

1

T94

52

T95

42

T96

42

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	50401	1			T95	2		T96	1		T99	3
valid_sources[0x01]	49698	1			T95	5		T99	2		T286	4
valid_sources[0x02]	50517	1			T94	1		T96	1		T99	3
valid_sources[0x03]	51219	1			T95	2		T96	1		T99	1
valid_sources[0x04]	50314	1			T95	2		T96	1		T99	3
valid_sources[0x05]	50554	1			T94	2		T95	1		T96	2
valid_sources[0x06]	50412	1			T96	1		T99	3		T184	6
valid_sources[0x07]	51076	1			T95	2		T96	2		T99	3
valid_sources[0x08]	49991	1			T94	4		T95	1		T96	1
valid_sources[0x09]	50077	1			T99	4		T286	4		T247	1
valid_sources[0x0a]	50188	1			T95	3		T286	28		T465	7
valid_sources[0x0b]	49150	1			T95	1		T96	2		T99	2
valid_sources[0x0c]	50501	1			T96	4		T99	3		T286	2
valid_sources[0x0d]	50144	1			T95	1		T96	1		T99	2
valid_sources[0x0e]	50065	1			T95	2		T96	2		T99	1
valid_sources[0x0f]	51503	1			T94	3		T96	1		T99	3
valid_sources[0x10]	50804	1			T96	5		T99	4		T286	7
valid_sources[0x11]	50283	1			T95	4		T96	2		T99	1
valid_sources[0x12]	50876	1			T95	2		T96	4		T99	2
valid_sources[0x13]	50415	1			T96	3		T99	3		T286	2
valid_sources[0x14]	49912	1			T94	13		T96	2		T99	1
valid_sources[0x15]	51314	1			T95	4		T96	1		T99	4
valid_sources[0x16]	50565	1			T95	7		T99	1		T286	3
valid_sources[0x17]	50575	1			T94	11		T95	5		T96	3
valid_sources[0x18]	51620	1			T94	3		T95	3		T96	1
valid_sources[0x19]	50437	1			T95	2		T99	2		T465	20
valid_sources[0x1a]	50237	1			T96	4		T99	1		T247	1
valid_sources[0x1b]	49945	1			T94	4		T96	2		T99	4
valid_sources[0x1c]	50659	1			T94	21		T99	3		T286	9
valid_sources[0x1d]	50223	1			T96	1		T465	24		T461	1
valid_sources[0x1e]	50028	1			T96	5		T286	6		T247	1
valid_sources[0x1f]	50245	1			T94	11		T95	1		T96	2
valid_sources[0x20]	50649	1			T94	1		T95	1		T96	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46399

1

T94

1

T95

6

T96

2

values[0x0]

all_enables

biggest_size

347636

1

T94

17

T95

12

T96

13

values[0x1]

all_enables

biggest_size

46314

1

T94

1

T95

2

T99

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2967793	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

483122

1

T94

12

T95

25

T96

19

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1181666	1			T94	43		T95	69		T96	32
values[0x0]	1088166	1			T94	31		T95	60		T96	41
values[0x1]	1181083	1			T94	40		T95	68		T96	51

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2278244	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1172671

1

T94

45

T95

74

T96

42

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54163	1			T95	3		T96	3		T99	1
valid_sources[0x01]	52980	1			T94	1		T95	1		T99	1
valid_sources[0x02]	54142	1			T94	1		T95	6		T99	1
valid_sources[0x03]	54307	1			T94	1		T95	3		T286	10
valid_sources[0x04]	53263	1			T94	2		T95	5		T96	1
valid_sources[0x05]	54026	1			T94	3		T95	3		T96	4
valid_sources[0x06]	53902	1			T94	1		T95	2		T96	1
valid_sources[0x07]	54322	1			T94	2		T95	3		T96	2
valid_sources[0x08]	53433	1			T94	4		T95	5		T96	4
valid_sources[0x09]	53998	1			T94	1		T95	1		T247	2
valid_sources[0x0a]	53965	1			T94	6		T95	1		T96	1
valid_sources[0x0b]	54023	1			T95	4		T96	3		T99	2
valid_sources[0x0c]	54471	1			T95	6		T99	1		T286	3
valid_sources[0x0d]	53612	1			T94	3		T95	2		T96	3
valid_sources[0x0e]	53841	1			T94	3		T95	4		T96	3
valid_sources[0x0f]	55110	1			T94	2		T95	3		T96	3
valid_sources[0x10]	54154	1			T94	4		T95	7		T96	4
valid_sources[0x11]	55041	1			T94	2		T95	2		T96	1
valid_sources[0x12]	54299	1			T94	3		T95	1		T99	3
valid_sources[0x13]	53618	1			T94	2		T95	7		T96	3
valid_sources[0x14]	53037	1			T95	3		T286	9		T465	9
valid_sources[0x15]	54681	1			T94	2		T95	2		T96	1
valid_sources[0x16]	53490	1			T94	1		T95	7		T99	6
valid_sources[0x17]	53872	1			T94	2		T95	1		T96	4
valid_sources[0x18]	53830	1			T95	5		T99	1		T286	9
valid_sources[0x19]	53942	1			T94	2		T95	1		T96	3
valid_sources[0x1a]	53653	1			T94	1		T95	1		T96	3
valid_sources[0x1b]	53444	1			T95	3		T96	2		T99	7
valid_sources[0x1c]	53757	1			T94	1		T95	4		T96	1
valid_sources[0x1d]	53903	1			T94	2		T95	4		T96	1
valid_sources[0x1e]	54211	1			T94	2		T95	3		T96	4
valid_sources[0x1f]	53262	1			T94	1		T95	3		T96	1
valid_sources[0x20]	53325	1			T94	1		T96	2		T247	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

51121

1

T95

3

T96

2

T99

1

values[0x0]

all_enables

biggest_size

381021

1

T94

11

T95

22

T96

13

values[0x1]

all_enables

biggest_size

50980

1

T94

1

T96

4

T99

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2816619	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

445207

1

T94

19

T95

17

T96

21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1104910	1			T94	55		T95	42		T96	56
values[0x0]	1052116	1			T94	44		T95	30		T96	53
values[0x1]	1104800	1			T94	59		T95	35		T96	38

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2180534	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1081292

1

T94

48

T95

44

T96

49

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51036	1			T94	3		T95	2		T286	9
valid_sources[0x01]	50358	1			T94	2		T95	1		T96	7
valid_sources[0x02]	51250	1			T94	1		T96	6		T184	1
valid_sources[0x03]	51254	1			T94	6		T95	2		T96	2
valid_sources[0x04]	50779	1			T94	4		T99	1		T184	1
valid_sources[0x05]	50312	1			T94	3		T95	3		T286	3
valid_sources[0x06]	51072	1			T94	1		T95	1		T96	3
valid_sources[0x07]	51520	1			T96	9		T286	8		T184	2
valid_sources[0x08]	51004	1			T94	2		T95	2		T96	2
valid_sources[0x09]	51622	1			T94	1		T99	6		T286	14
valid_sources[0x0a]	51147	1			T94	1		T95	2		T96	3
valid_sources[0x0b]	51112	1			T94	3		T95	4		T96	2
valid_sources[0x0c]	51219	1			T94	3		T95	1		T96	6
valid_sources[0x0d]	50965	1			T95	1		T96	3		T286	2
valid_sources[0x0e]	50369	1			T94	2		T95	2		T96	2
valid_sources[0x0f]	51273	1			T94	1		T95	2		T96	4
valid_sources[0x10]	51002	1			T94	1		T95	1		T96	8
valid_sources[0x11]	50556	1			T94	4		T95	3		T99	12
valid_sources[0x12]	51579	1			T94	4		T95	2		T184	2
valid_sources[0x13]	51176	1			T94	1		T95	1		T286	5
valid_sources[0x14]	50298	1			T94	1		T96	1		T99	18
valid_sources[0x15]	51851	1			T94	4		T95	2		T286	7
valid_sources[0x16]	52008	1			T94	4		T96	3		T99	16
valid_sources[0x17]	50875	1			T94	3		T95	2		T96	1
valid_sources[0x18]	52273	1			T94	5		T95	4		T286	24
valid_sources[0x19]	50539	1			T94	4		T95	1		T96	2
valid_sources[0x1a]	50724	1			T94	1		T96	3		T99	1
valid_sources[0x1b]	51853	1			T94	2		T95	1		T286	9
valid_sources[0x1c]	50848	1			T94	6		T95	1		T96	2
valid_sources[0x1d]	50949	1			T94	5		T95	1		T286	3
valid_sources[0x1e]	51401	1			T94	4		T95	3		T96	3
valid_sources[0x1f]	50417	1			T94	4		T95	2		T96	2
valid_sources[0x20]	50354	1			T94	1		T95	1		T96	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46776

1

T94

2

T95

4

T96

1

values[0x0]

all_enables

biggest_size

351855

1

T94

11

T95

13

T96

20

values[0x1]

all_enables

biggest_size

46576

1

T94

6

T286

2

T247

2