Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	471096855	56987479	0	0
DepthKnown_A	471096855	470993279	0	0
RvalidKnown_A	471096855	470993279	0	0
WreadyKnown_A	471096855	470993279	0	0
gen_passthru_fifo.paramCheckPass	1011	1011	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471096855	56987479	0	0
T1	79194	8078	0	0
T2	59963	5562	0	0
T3	211087	21162	0	0
T4	123510	16225	0	0
T5	294721	29772	0	0
T6	96786	10422	0	0
T29	74935	8926	0	0
T33	96569	8587	0	0
T103	42263	3485	0	0
T104	63494	7399	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471096855	470993279	0	0
T1	79194	79143	0	0
T2	59963	59905	0	0
T3	211087	211036	0	0
T4	123510	123459	0	0
T5	294721	294670	0	0
T6	96786	96724	0	0
T29	74935	74880	0	0
T33	96569	96459	0	0
T103	42263	42208	0	0
T104	63494	63432	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471096855	470993279	0	0
T1	79194	79143	0	0
T2	59963	59905	0	0
T3	211087	211036	0	0
T4	123510	123459	0	0
T5	294721	294670	0	0
T6	96786	96724	0	0
T29	74935	74880	0	0
T33	96569	96459	0	0
T103	42263	42208	0	0
T104	63494	63432	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471096855	470993279	0	0
T1	79194	79143	0	0
T2	59963	59905	0	0
T3	211087	211036	0	0
T4	123510	123459	0	0
T5	294721	294670	0	0
T6	96786	96724	0	0
T29	74935	74880	0	0
T33	96569	96459	0	0
T103	42263	42208	0	0
T104	63494	63432	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1011	1011	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T29	1	1	0	0
T33	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         0/1     ==>      assign wready_o = rready_i;
49         0/1     ==>      assign full_o = rready_i;
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	471096855	42543451	0	0
DepthKnown_A	471096855	470993279	0	0
RvalidKnown_A	471096855	470993279	0	0
WreadyKnown_A	471096855	470993279	0	0
gen_passthru_fifo.paramCheckPass	1011	1011	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471096855	42543451	0	0
T1	79194	6412	0	0
T2	59963	3894	0	0
T3	211087	17250	0	0
T4	123510	11032	0	0
T5	294721	25279	0	0
T6	96786	7868	0	0
T29	74935	6192	0	0
T33	96569	6855	0	0
T103	42263	1880	0	0
T104	63494	4845	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471096855	470993279	0	0
T1	79194	79143	0	0
T2	59963	59905	0	0
T3	211087	211036	0	0
T4	123510	123459	0	0
T5	294721	294670	0	0
T6	96786	96724	0	0
T29	74935	74880	0	0
T33	96569	96459	0	0
T103	42263	42208	0	0
T104	63494	63432	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471096855	470993279	0	0
T1	79194	79143	0	0
T2	59963	59905	0	0
T3	211087	211036	0	0
T4	123510	123459	0	0
T5	294721	294670	0	0
T6	96786	96724	0	0
T29	74935	74880	0	0
T33	96569	96459	0	0
T103	42263	42208	0	0
T104	63494	63432	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471096855	470993279	0	0
T1	79194	79143	0	0
T2	59963	59905	0	0
T3	211087	211036	0	0
T4	123510	123459	0	0
T5	294721	294670	0	0
T6	96786	96724	0	0
T29	74935	74880	0	0
T33	96569	96459	0	0
T103	42263	42208	0	0
T104	63494	63432	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1011	1011	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T29	1	1	0	0
T33	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	471096855	41319662	0	0
DepthKnown_A	471096855	470993279	0	0
RvalidKnown_A	471096855	470993279	0	0
WreadyKnown_A	471096855	470993279	0	0
gen_passthru_fifo.paramCheckPass	1011	1011	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471096855	41319662	0	0
T1	79194	5028	0	0
T2	59963	3196	0	0
T3	211087	20071	0	0
T4	123510	8427	0	0
T5	294721	26258	0	0
T6	96786	8154	0	0
T29	74935	4318	0	0
T33	96569	5328	0	0
T103	42263	461	0	0
T104	63494	4648	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471096855	470993279	0	0
T1	79194	79143	0	0
T2	59963	59905	0	0
T3	211087	211036	0	0
T4	123510	123459	0	0
T5	294721	294670	0	0
T6	96786	96724	0	0
T29	74935	74880	0	0
T33	96569	96459	0	0
T103	42263	42208	0	0
T104	63494	63432	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471096855	470993279	0	0
T1	79194	79143	0	0
T2	59963	59905	0	0
T3	211087	211036	0	0
T4	123510	123459	0	0
T5	294721	294670	0	0
T6	96786	96724	0	0
T29	74935	74880	0	0
T33	96569	96459	0	0
T103	42263	42208	0	0
T104	63494	63432	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471096855	470993279	0	0
T1	79194	79143	0	0
T2	59963	59905	0	0
T3	211087	211036	0	0
T4	123510	123459	0	0
T5	294721	294670	0	0
T6	96786	96724	0	0
T29	74935	74880	0	0
T33	96569	96459	0	0
T103	42263	42208	0	0
T104	63494	63432	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1011	1011	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T29	1	1	0	0
T33	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T35 T98 T67 
49         1/1              assign full_o = rready_i;
           Tests:       T35 T98 T67 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	471096855	34430842	0	0
DepthKnown_A	471096855	470993279	0	0
RvalidKnown_A	471096855	470993279	0	0
WreadyKnown_A	471096855	470993279	0	0
gen_passthru_fifo.paramCheckPass	1011	1011	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471096855	34430842	0	0
T1	79194	4915	0	0
T2	59963	3083	0	0
T3	211087	19870	0	0
T4	123510	8003	0	0
T5	294721	25957	0	0
T6	96786	7699	0	0
T29	74935	4149	0	0
T33	96569	5209	0	0
T103	42263	353	0	0
T104	63494	4470	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471096855	470993279	0	0
T1	79194	79143	0	0
T2	59963	59905	0	0
T3	211087	211036	0	0
T4	123510	123459	0	0
T5	294721	294670	0	0
T6	96786	96724	0	0
T29	74935	74880	0	0
T33	96569	96459	0	0
T103	42263	42208	0	0
T104	63494	63432	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471096855	470993279	0	0
T1	79194	79143	0	0
T2	59963	59905	0	0
T3	211087	211036	0	0
T4	123510	123459	0	0
T5	294721	294670	0	0
T6	96786	96724	0	0
T29	74935	74880	0	0
T33	96569	96459	0	0
T103	42263	42208	0	0
T104	63494	63432	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471096855	470993279	0	0
T1	79194	79143	0	0
T2	59963	59905	0	0
T3	211087	211036	0	0
T4	123510	123459	0	0
T5	294721	294670	0	0
T6	96786	96724	0	0
T29	74935	74880	0	0
T33	96569	96459	0	0
T103	42263	42208	0	0
T104	63494	63432	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1011	1011	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T29	1	1	0	0
T33	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	551640984	90318	0	0
DepthKnown_A	551640984	551521413	0	0
RvalidKnown_A	551640984	551521413	0	0
WreadyKnown_A	551640984	551521413	0	0
gen_passthru_fifo.paramCheckPass	2918	2918	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551640984	90318	0	0
T1	79194	13	0	0
T2	59963	13	0	0
T3	211087	53	0	0
T4	123510	53	0	0
T5	294721	23	0	0
T6	96786	208	0	0
T29	74935	23	0	0
T33	96569	13	0	0
T103	42263	8	0	0
T104	63494	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551640984	551521413	0	0
T1	79194	79143	0	0
T2	59963	59905	0	0
T3	211087	211036	0	0
T4	123510	123459	0	0
T5	294721	294670	0	0
T6	96786	96724	0	0
T29	74935	74880	0	0
T33	96569	96459	0	0
T103	42263	42208	0	0
T104	63494	63432	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551640984	551521413	0	0
T1	79194	79143	0	0
T2	59963	59905	0	0
T3	211087	211036	0	0
T4	123510	123459	0	0
T5	294721	294670	0	0
T6	96786	96724	0	0
T29	74935	74880	0	0
T33	96569	96459	0	0
T103	42263	42208	0	0
T104	63494	63432	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551640984	551521413	0	0
T1	79194	79143	0	0
T2	59963	59905	0	0
T3	211087	211036	0	0
T4	123510	123459	0	0
T5	294721	294670	0	0
T6	96786	96724	0	0
T29	74935	74880	0	0
T33	96569	96459	0	0
T103	42263	42208	0	0
T104	63494	63432	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2918	2918	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T29	1	1	0	0
T33	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	551640984	92952	0	0
DepthKnown_A	551640984	551521413	0	0
RvalidKnown_A	551640984	551521413	0	0
WreadyKnown_A	551640984	551521413	0	0
gen_passthru_fifo.paramCheckPass	2918	2918	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551640984	92952	0	0
T1	79194	13	0	0
T2	59963	13	0	0
T3	211087	53	0	0
T4	123510	53	0	0
T5	294721	23	0	0
T6	96786	208	0	0
T29	74935	23	0	0
T33	96569	13	0	0
T103	42263	8	0	0
T104	63494	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551640984	551521413	0	0
T1	79194	79143	0	0
T2	59963	59905	0	0
T3	211087	211036	0	0
T4	123510	123459	0	0
T5	294721	294670	0	0
T6	96786	96724	0	0
T29	74935	74880	0	0
T33	96569	96459	0	0
T103	42263	42208	0	0
T104	63494	63432	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551640984	551521413	0	0
T1	79194	79143	0	0
T2	59963	59905	0	0
T3	211087	211036	0	0
T4	123510	123459	0	0
T5	294721	294670	0	0
T6	96786	96724	0	0
T29	74935	74880	0	0
T33	96569	96459	0	0
T103	42263	42208	0	0
T104	63494	63432	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551640984	551521413	0	0
T1	79194	79143	0	0
T2	59963	59905	0	0
T3	211087	211036	0	0
T4	123510	123459	0	0
T5	294721	294670	0	0
T6	96786	96724	0	0
T29	74935	74880	0	0
T33	96569	96459	0	0
T103	42263	42208	0	0
T104	63494	63432	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2918	2918	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T29	1	1	0	0
T33	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	551640984	50650	0	0
DepthKnown_A	551640984	551521413	0	0
RvalidKnown_A	551640984	551521413	0	0
WreadyKnown_A	551640984	551521413	0	0
gen_passthru_fifo.paramCheckPass	2918	2918	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551640984	50650	0	0
T1	79194	12	0	0
T2	59963	12	0	0
T3	211087	52	0	0
T4	123510	50	0	0
T5	294721	20	0	0
T6	96786	205	0	0
T29	74935	20	0	0
T33	96569	12	0	0
T103	42263	8	0	0
T104	63494	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551640984	551521413	0	0
T1	79194	79143	0	0
T2	59963	59905	0	0
T3	211087	211036	0	0
T4	123510	123459	0	0
T5	294721	294670	0	0
T6	96786	96724	0	0
T29	74935	74880	0	0
T33	96569	96459	0	0
T103	42263	42208	0	0
T104	63494	63432	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551640984	551521413	0	0
T1	79194	79143	0	0
T2	59963	59905	0	0
T3	211087	211036	0	0
T4	123510	123459	0	0
T5	294721	294670	0	0
T6	96786	96724	0	0
T29	74935	74880	0	0
T33	96569	96459	0	0
T103	42263	42208	0	0
T104	63494	63432	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551640984	551521413	0	0
T1	79194	79143	0	0
T2	59963	59905	0	0
T3	211087	211036	0	0
T4	123510	123459	0	0
T5	294721	294670	0	0
T6	96786	96724	0	0
T29	74935	74880	0	0
T33	96569	96459	0	0
T103	42263	42208	0	0
T104	63494	63432	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2918	2918	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T29	1	1	0	0
T33	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	551640984	50650	0	0
DepthKnown_A	551640984	551521413	0	0
RvalidKnown_A	551640984	551521413	0	0
WreadyKnown_A	551640984	551521413	0	0
gen_passthru_fifo.paramCheckPass	2918	2918	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551640984	50650	0	0
T1	79194	12	0	0
T2	59963	12	0	0
T3	211087	52	0	0
T4	123510	50	0	0
T5	294721	20	0	0
T6	96786	205	0	0
T29	74935	20	0	0
T33	96569	12	0	0
T103	42263	8	0	0
T104	63494	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551640984	551521413	0	0
T1	79194	79143	0	0
T2	59963	59905	0	0
T3	211087	211036	0	0
T4	123510	123459	0	0
T5	294721	294670	0	0
T6	96786	96724	0	0
T29	74935	74880	0	0
T33	96569	96459	0	0
T103	42263	42208	0	0
T104	63494	63432	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551640984	551521413	0	0
T1	79194	79143	0	0
T2	59963	59905	0	0
T3	211087	211036	0	0
T4	123510	123459	0	0
T5	294721	294670	0	0
T6	96786	96724	0	0
T29	74935	74880	0	0
T33	96569	96459	0	0
T103	42263	42208	0	0
T104	63494	63432	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551640984	551521413	0	0
T1	79194	79143	0	0
T2	59963	59905	0	0
T3	211087	211036	0	0
T4	123510	123459	0	0
T5	294721	294670	0	0
T6	96786	96724	0	0
T29	74935	74880	0	0
T33	96569	96459	0	0
T103	42263	42208	0	0
T104	63494	63432	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2918	2918	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T29	1	1	0	0
T33	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	551640984	39668	0	0
DepthKnown_A	551640984	551521413	0	0
RvalidKnown_A	551640984	551521413	0	0
WreadyKnown_A	551640984	551521413	0	0
gen_passthru_fifo.paramCheckPass	2918	2918	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551640984	39668	0	0
T1	79194	1	0	0
T2	59963	1	0	0
T3	211087	1	0	0
T4	123510	3	0	0
T5	294721	3	0	0
T6	96786	3	0	0
T29	74935	3	0	0
T33	96569	1	0	0
T34	0	1	0	0
T103	42263	0	0	0
T104	63494	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551640984	551521413	0	0
T1	79194	79143	0	0
T2	59963	59905	0	0
T3	211087	211036	0	0
T4	123510	123459	0	0
T5	294721	294670	0	0
T6	96786	96724	0	0
T29	74935	74880	0	0
T33	96569	96459	0	0
T103	42263	42208	0	0
T104	63494	63432	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551640984	551521413	0	0
T1	79194	79143	0	0
T2	59963	59905	0	0
T3	211087	211036	0	0
T4	123510	123459	0	0
T5	294721	294670	0	0
T6	96786	96724	0	0
T29	74935	74880	0	0
T33	96569	96459	0	0
T103	42263	42208	0	0
T104	63494	63432	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551640984	551521413	0	0
T1	79194	79143	0	0
T2	59963	59905	0	0
T3	211087	211036	0	0
T4	123510	123459	0	0
T5	294721	294670	0	0
T6	96786	96724	0	0
T29	74935	74880	0	0
T33	96569	96459	0	0
T103	42263	42208	0	0
T104	63494	63432	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2918	2918	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T29	1	1	0	0
T33	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	551640984	42302	0	0
DepthKnown_A	551640984	551521413	0	0
RvalidKnown_A	551640984	551521413	0	0
WreadyKnown_A	551640984	551521413	0	0
gen_passthru_fifo.paramCheckPass	2918	2918	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551640984	42302	0	0
T1	79194	1	0	0
T2	59963	1	0	0
T3	211087	1	0	0
T4	123510	3	0	0
T5	294721	3	0	0
T6	96786	3	0	0
T29	74935	3	0	0
T33	96569	1	0	0
T34	0	1	0	0
T103	42263	0	0	0
T104	63494	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551640984	551521413	0	0
T1	79194	79143	0	0
T2	59963	59905	0	0
T3	211087	211036	0	0
T4	123510	123459	0	0
T5	294721	294670	0	0
T6	96786	96724	0	0
T29	74935	74880	0	0
T33	96569	96459	0	0
T103	42263	42208	0	0
T104	63494	63432	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551640984	551521413	0	0
T1	79194	79143	0	0
T2	59963	59905	0	0
T3	211087	211036	0	0
T4	123510	123459	0	0
T5	294721	294670	0	0
T6	96786	96724	0	0
T29	74935	74880	0	0
T33	96569	96459	0	0
T103	42263	42208	0	0
T104	63494	63432	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551640984	551521413	0	0
T1	79194	79143	0	0
T2	59963	59905	0	0
T3	211087	211036	0	0
T4	123510	123459	0	0
T5	294721	294670	0	0
T6	96786	96724	0	0
T29	74935	74880	0	0
T33	96569	96459	0	0
T103	42263	42208	0	0
T104	63494	63432	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2918	2918	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T29	1	1	0	0
T33	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0