Unified Coverage Report :: Module :: sensor_ctrl_reg_top

Module : sensor_ctrl_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.75	100.00	71.00			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_systems_sensor_ctrl_reg_0.1/rtl/sensor_ctrl_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg	92.75	100.00	71.00			100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.75	100.00	71.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.32	92.68	85.17			95.45	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.45	93.69	89.00	79.58		100.00	100.00	u_sensor_ctrl_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_en_0	100.00	100.00	100.00			100.00
u_alert_en_1	100.00	100.00	100.00			100.00
u_alert_en_10	100.00	100.00	100.00			100.00
u_alert_en_2	100.00	100.00	100.00			100.00
u_alert_en_3	100.00	100.00	100.00			100.00
u_alert_en_4	100.00	100.00	100.00			100.00
u_alert_en_5	100.00	100.00	100.00			100.00
u_alert_en_6	100.00	100.00	100.00			100.00
u_alert_en_7	100.00	100.00	100.00			100.00
u_alert_en_8	100.00	100.00	100.00			100.00
u_alert_en_9	100.00	100.00	100.00			100.00
u_alert_test_fatal_alert	100.00	100.00
u_alert_test_recov_alert	100.00	100.00
u_alert_trig_val_0	100.00	100.00	100.00			100.00
u_alert_trig_val_1	100.00	100.00	100.00			100.00
u_alert_trig_val_10	100.00	100.00	100.00			100.00
u_alert_trig_val_2	100.00	100.00	100.00			100.00
u_alert_trig_val_3	100.00	100.00	100.00			100.00
u_alert_trig_val_4	100.00	100.00	100.00			100.00
u_alert_trig_val_5	100.00	100.00	100.00			100.00
u_alert_trig_val_6	100.00	100.00	100.00			100.00
u_alert_trig_val_7	100.00	100.00	100.00			100.00
u_alert_trig_val_8	100.00	100.00	100.00			100.00
u_alert_trig_val_9	100.00	100.00	100.00			100.00
u_cfg_regwen	89.63	88.89	80.00			100.00
u_chk	100.00	100.00					100.00
u_fatal_alert_en_val_0	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_1	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_10	96.30	88.89	100.00			100.00
u_fatal_alert_en_val_2	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_3	96.30	88.89	100.00			100.00
u_fatal_alert_en_val_4	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_5	96.30	88.89	100.00			100.00
u_fatal_alert_en_val_6	96.30	88.89	100.00			100.00
u_fatal_alert_en_val_7	96.30	88.89	100.00			100.00
u_fatal_alert_en_val_8	96.30	88.89	100.00			100.00
u_fatal_alert_en_val_9	96.30	88.89	100.00			100.00
u_fatal_alert_val_0	96.30	88.89	100.00			100.00
u_fatal_alert_val_1	96.30	88.89	100.00			100.00
u_fatal_alert_val_10	47.78	33.33	50.00			60.00
u_fatal_alert_val_11	96.30	88.89	100.00			100.00
u_fatal_alert_val_2	96.30	88.89	100.00			100.00
u_fatal_alert_val_3	47.78	33.33	50.00			60.00
u_fatal_alert_val_4	96.30	88.89	100.00			100.00
u_fatal_alert_val_5	47.78	33.33	50.00			60.00
u_fatal_alert_val_6	47.78	33.33	50.00			60.00
u_fatal_alert_val_7	47.78	33.33	50.00			60.00
u_fatal_alert_val_8	47.78	33.33	50.00			60.00
u_fatal_alert_val_9	47.78	33.33	50.00			60.00
u_intr_enable_init_status_change	100.00	100.00	100.00			100.00
u_intr_enable_io_status_change	100.00	100.00	100.00			100.00
u_intr_state_init_status_change	100.00	100.00	100.00			100.00
u_intr_state_io_status_change	100.00	100.00	100.00			100.00
u_intr_test_init_status_change	100.00	100.00
u_intr_test_io_status_change	100.00	100.00
u_manual_pad_attr_0_input_disable_0	80.00	80.00
u_manual_pad_attr_0_pull_en_0	80.00	80.00
u_manual_pad_attr_0_pull_select_0	80.00	80.00
u_manual_pad_attr_1_input_disable_1	80.00	80.00
u_manual_pad_attr_1_pull_en_1	80.00	80.00
u_manual_pad_attr_1_pull_select_1	80.00	80.00
u_manual_pad_attr_2_input_disable_2	80.00	80.00
u_manual_pad_attr_2_pull_en_2	80.00	80.00
u_manual_pad_attr_2_pull_select_2	80.00	80.00
u_manual_pad_attr_3_input_disable_3	80.00	80.00
u_manual_pad_attr_3_pull_en_3	80.00	80.00
u_manual_pad_attr_3_pull_select_3	80.00	80.00
u_manual_pad_attr_regwen_0	89.63	88.89	80.00			100.00
u_manual_pad_attr_regwen_1	89.63	88.89	80.00			100.00
u_manual_pad_attr_regwen_2	100.00	100.00	100.00			100.00
u_manual_pad_attr_regwen_3	89.63	88.89	80.00			100.00
u_prim_reg_we_check	100.00	100.00
u_recov_alert_val_0	100.00	100.00	100.00			100.00
u_recov_alert_val_1	100.00	100.00	100.00			100.00
u_recov_alert_val_10	100.00	100.00	100.00			100.00
u_recov_alert_val_2	100.00	100.00	100.00			100.00
u_recov_alert_val_3	100.00	100.00	100.00			100.00
u_recov_alert_val_4	100.00	100.00	100.00			100.00
u_recov_alert_val_5	100.00	100.00	100.00			100.00
u_recov_alert_val_6	100.00	100.00	100.00			100.00
u_recov_alert_val_7	100.00	100.00	100.00			100.00
u_recov_alert_val_8	100.00	100.00	100.00			100.00
u_recov_alert_val_9	100.00	100.00	100.00			100.00
u_reg_if	89.30	94.29	76.54			86.36	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_status_ast_init_done	62.59	77.78	50.00			60.00
u_status_io_pok	62.59	77.78	50.00			60.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : sensor_ctrl_reg_top

	Line No.	Total	Covered	Percent
TOTAL		296	296	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	435	1	1	100.00
CONT_ASSIGN	451	1	1	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	472	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	823	1	1	100.00
CONT_ASSIGN	855	1	1	100.00
CONT_ASSIGN	887	1	1	100.00
CONT_ASSIGN	919	1	1	100.00
CONT_ASSIGN	951	1	1	100.00
CONT_ASSIGN	983	1	1	100.00
CONT_ASSIGN	1015	1	1	100.00
CONT_ASSIGN	1047	1	1	100.00
CONT_ASSIGN	1079	1	1	100.00
CONT_ASSIGN	1111	1	1	100.00
CONT_ASSIGN	1143	1	1	100.00
CONT_ASSIGN	1175	1	1	100.00
CONT_ASSIGN	2277	1	1	100.00
CONT_ASSIGN	2280	1	1	100.00
CONT_ASSIGN	2295	1	1	100.00
CONT_ASSIGN	2311	1	1	100.00
CONT_ASSIGN	2327	1	1	100.00
CONT_ASSIGN	2334	1	1	100.00
CONT_ASSIGN	2337	1	1	100.00
CONT_ASSIGN	2352	1	1	100.00
CONT_ASSIGN	2368	1	1	100.00
CONT_ASSIGN	2384	1	1	100.00
CONT_ASSIGN	2391	1	1	100.00
CONT_ASSIGN	2394	1	1	100.00
CONT_ASSIGN	2409	1	1	100.00
CONT_ASSIGN	2425	1	1	100.00
CONT_ASSIGN	2441	1	1	100.00
CONT_ASSIGN	2448	1	1	100.00
CONT_ASSIGN	2451	1	1	100.00
CONT_ASSIGN	2466	1	1	100.00
CONT_ASSIGN	2482	1	1	100.00
CONT_ASSIGN	2498	1	1	100.00
ALWAYS	2504	30	30	100.00
CONT_ASSIGN	2536	1	1	100.00
ALWAYS	2540	1	1	100.00
CONT_ASSIGN	2573	1	1	100.00
CONT_ASSIGN	2575	1	1	100.00
CONT_ASSIGN	2577	1	1	100.00
CONT_ASSIGN	2578	1	1	100.00
CONT_ASSIGN	2580	1	1	100.00
CONT_ASSIGN	2582	1	1	100.00
CONT_ASSIGN	2583	1	1	100.00
CONT_ASSIGN	2585	1	1	100.00
CONT_ASSIGN	2587	1	1	100.00
CONT_ASSIGN	2588	1	1	100.00
CONT_ASSIGN	2590	1	1	100.00
CONT_ASSIGN	2592	1	1	100.00
CONT_ASSIGN	2593	1	1	100.00
CONT_ASSIGN	2595	1	1	100.00
CONT_ASSIGN	2596	1	1	100.00
CONT_ASSIGN	2598	1	1	100.00
CONT_ASSIGN	2600	1	1	100.00
CONT_ASSIGN	2602	1	1	100.00
CONT_ASSIGN	2604	1	1	100.00
CONT_ASSIGN	2606	1	1	100.00
CONT_ASSIGN	2608	1	1	100.00
CONT_ASSIGN	2610	1	1	100.00
CONT_ASSIGN	2612	1	1	100.00
CONT_ASSIGN	2614	1	1	100.00
CONT_ASSIGN	2616	1	1	100.00
CONT_ASSIGN	2618	1	1	100.00
CONT_ASSIGN	2619	1	1	100.00
CONT_ASSIGN	2621	1	1	100.00
CONT_ASSIGN	2622	1	1	100.00
CONT_ASSIGN	2624	1	1	100.00
CONT_ASSIGN	2625	1	1	100.00
CONT_ASSIGN	2627	1	1	100.00
CONT_ASSIGN	2628	1	1	100.00
CONT_ASSIGN	2630	1	1	100.00
CONT_ASSIGN	2631	1	1	100.00
CONT_ASSIGN	2633	1	1	100.00
CONT_ASSIGN	2634	1	1	100.00
CONT_ASSIGN	2636	1	1	100.00
CONT_ASSIGN	2637	1	1	100.00
CONT_ASSIGN	2639	1	1	100.00
CONT_ASSIGN	2640	1	1	100.00
CONT_ASSIGN	2642	1	1	100.00
CONT_ASSIGN	2643	1	1	100.00
CONT_ASSIGN	2645	1	1	100.00
CONT_ASSIGN	2646	1	1	100.00
CONT_ASSIGN	2648	1	1	100.00
CONT_ASSIGN	2649	1	1	100.00
CONT_ASSIGN	2651	1	1	100.00
CONT_ASSIGN	2652	1	1	100.00
CONT_ASSIGN	2654	1	1	100.00
CONT_ASSIGN	2656	1	1	100.00
CONT_ASSIGN	2658	1	1	100.00
CONT_ASSIGN	2660	1	1	100.00
CONT_ASSIGN	2662	1	1	100.00
CONT_ASSIGN	2664	1	1	100.00
CONT_ASSIGN	2666	1	1	100.00
CONT_ASSIGN	2668	1	1	100.00
CONT_ASSIGN	2670	1	1	100.00
CONT_ASSIGN	2672	1	1	100.00
CONT_ASSIGN	2674	1	1	100.00
CONT_ASSIGN	2675	1	1	100.00
CONT_ASSIGN	2677	1	1	100.00
CONT_ASSIGN	2679	1	1	100.00
CONT_ASSIGN	2681	1	1	100.00
CONT_ASSIGN	2683	1	1	100.00
CONT_ASSIGN	2685	1	1	100.00
CONT_ASSIGN	2687	1	1	100.00
CONT_ASSIGN	2689	1	1	100.00
CONT_ASSIGN	2691	1	1	100.00
CONT_ASSIGN	2693	1	1	100.00
CONT_ASSIGN	2695	1	1	100.00
CONT_ASSIGN	2697	1	1	100.00
CONT_ASSIGN	2698	1	1	100.00
CONT_ASSIGN	2700	1	1	100.00
CONT_ASSIGN	2701	1	1	100.00
CONT_ASSIGN	2703	1	1	100.00
CONT_ASSIGN	2704	1	1	100.00
CONT_ASSIGN	2706	1	1	100.00
CONT_ASSIGN	2707	1	1	100.00
CONT_ASSIGN	2709	1	1	100.00
CONT_ASSIGN	2710	1	1	100.00
CONT_ASSIGN	2711	1	1	100.00
CONT_ASSIGN	2713	1	1	100.00
CONT_ASSIGN	2715	1	1	100.00
CONT_ASSIGN	2717	1	1	100.00
CONT_ASSIGN	2718	1	1	100.00
CONT_ASSIGN	2719	1	1	100.00
CONT_ASSIGN	2721	1	1	100.00
CONT_ASSIGN	2723	1	1	100.00
CONT_ASSIGN	2725	1	1	100.00
CONT_ASSIGN	2726	1	1	100.00
CONT_ASSIGN	2727	1	1	100.00
CONT_ASSIGN	2729	1	1	100.00
CONT_ASSIGN	2731	1	1	100.00
CONT_ASSIGN	2733	1	1	100.00
CONT_ASSIGN	2734	1	1	100.00
CONT_ASSIGN	2735	1	1	100.00
CONT_ASSIGN	2737	1	1	100.00
CONT_ASSIGN	2739	1	1	100.00
CONT_ASSIGN	2741	1	1	100.00
ALWAYS	2745	30	30	100.00
ALWAYS	2779	85	85	100.00
CONT_ASSIGN	2962	0	0
CONT_ASSIGN	2970	1	1	100.00
CONT_ASSIGN	2971	1	1	100.00

Click here to see the source line report.

---

Cond Coverage for Module : sensor_ctrl_reg_top

	Total	Covered	Percent
Conditions	369	262	71.00
Logical	369	262	71.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T76,T178,T163

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T116,T373,T374
1	0	Not Covered

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T116,T373,T374
0	1	0	Not Covered
1	0	0	Covered	T116,T373,T374

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       823
 EXPRESSION (alert_en_0_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T163,T74,T164

 LINE       855
 EXPRESSION (alert_en_1_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T163,T74,T165

 LINE       887
 EXPRESSION (alert_en_2_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T163,T74,T164

 LINE       919
 EXPRESSION (alert_en_3_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T163,T74,T164

 LINE       951
 EXPRESSION (alert_en_4_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T163,T74,T165

 LINE       983
 EXPRESSION (alert_en_5_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T163,T74,T164

 LINE       1015
 EXPRESSION (alert_en_6_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T163,T74,T164

 LINE       1047
 EXPRESSION (alert_en_7_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T163,T74,T164

 LINE       1079
 EXPRESSION (alert_en_8_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T163,T74,T164

 LINE       1111
 EXPRESSION (alert_en_9_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T163,T74,T164

 LINE       1143
 EXPRESSION (alert_en_10_we & cfg_regwen_qs)
             -------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T163,T74,T164

 LINE       1175
 EXPRESSION (fatal_alert_en_we & cfg_regwen_qs)
             --------1--------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T165,T35,T141

 LINE       2280
 EXPRESSION (manual_pad_attr_0_we & manual_pad_attr_regwen_0_qs)
             ----------1---------   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T21,T22,T23

 LINE       2337
 EXPRESSION (manual_pad_attr_1_we & manual_pad_attr_regwen_1_qs)
             ----------1---------   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T21,T22,T23

 LINE       2394
 EXPRESSION (manual_pad_attr_2_we & manual_pad_attr_regwen_2_qs)
             ----------1---------   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T21,T22,T23

 LINE       2451
 EXPRESSION (manual_pad_attr_3_we & manual_pad_attr_regwen_3_qs)
             ----------1---------   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T21,T22,T23

 LINE       2505
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_INTR_STATE_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2506
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_INTR_ENABLE_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2507
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_INTR_TEST_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2508
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_TEST_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2509
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_CFG_REGWEN_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2510
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_TRIG_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2511
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_0_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2512
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_1_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2513
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_2_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2514
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_3_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2515
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_4_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2516
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_5_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2517
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_6_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2518
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_7_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2519
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_8_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2520
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_9_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2521
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_10_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2522
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_FATAL_ALERT_EN_OFFSET)
            ----------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2523
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_RECOV_ALERT_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2524
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_FATAL_ALERT_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2525
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_STATUS_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2526
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_REGWEN_0_OFFSET)
            ---------------------------------------1--------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2527
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_REGWEN_1_OFFSET)
            ---------------------------------------1--------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2528
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_REGWEN_2_OFFSET)
            ---------------------------------------1--------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2529
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_REGWEN_3_OFFSET)
            ---------------------------------------1--------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2530
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_0_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2531
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_1_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2532
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_2_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2533
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_3_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2536
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2536
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T76,T178,T163
1	0	Covered	T1,T2,T3

 LINE       2540
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | (addr_hit[17] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[18] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[19] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T76,T178,T163
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b0011 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b0011 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b0011 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b1 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T1,T2,T3
29 (addr_hit[28] & ((|(4'...	Not Covered
28 (addr_hit[27] & ((|(4'...	Not Covered
27 (addr_hit[26] & ((|(4'...	Not Covered
26 (addr_hit[25] & ((|(4'...	Not Covered
25 (addr_hit[24] & ((|(4'...	Not Covered
24 (addr_hit[23] & ((|(4'...	Not Covered
23 (addr_hit[22] & ((|(4'...	Not Covered
22 (addr_hit[21] & ((|(4'...	Not Covered
21 (addr_hit[20] & ((|(4'...	Not Covered
20 (addr_hit[19] & ((|(4'...	Covered	T21,T22,T23
19 (addr_hit[18] & ((|(4'...	Covered	T21,T22,T23
18 (addr_hit[17] & ((|(4'...	Covered	T21,T22,T23
17 (addr_hit[16] & ((|(4'...	Not Covered
16 (addr_hit[15] & ((|(4'...	Not Covered
15 (addr_hit[14] & ((|(4'...	Not Covered
14 (addr_hit[13] & ((|(4'...	Not Covered
13 (addr_hit[12] & ((|(4'...	Not Covered
12 (addr_hit[11] & ((|(4'...	Not Covered
11 (addr_hit[10] & ((|(4'...	Not Covered
10 (addr_hit[9] & ((|(4'b...	Not Covered
9 (addr_hit[8] & ((|(4'b...	Not Covered
8 (addr_hit[7] & ((|(4'b...	Not Covered
7 (addr_hit[6] & ((|(4'b...	Not Covered
6 (addr_hit[5] & ((|(4'b...	Covered	T21,T22,T23
5 (addr_hit[4] & ((|(4'b...	Not Covered
4 (addr_hit[3] & ((|(4'b...	Not Covered
3 (addr_hit[2] & ((|(4'b...	Not Covered
2 (addr_hit[1] & ((|(4'b...	Not Covered
1 (addr_hit[0] & ((|(4'b...	Covered	T1,T2,T3

 LINE       2540
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       2540
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T22,T23

 LINE       2540
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T22,T23

 LINE       2540
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T22,T23

 LINE       2540
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T22,T23

 LINE       2540
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2573
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T76,T178,T163
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T178,T123,T340

 LINE       2578
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T76,T178,T163
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T178,T123,T35

 LINE       2583
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T76,T178,T163
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T123,T191,T192

 LINE       2588
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T178,T163,T74
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T76,T35,T77

 LINE       2593
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T76,T178,T163
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T35

 LINE       2596
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T76,T178,T163
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T163,T74,T165

 LINE       2619
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T76,T178,T163
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T163,T74,T164

 LINE       2622
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T76,T178,T163
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T163,T74,T165

 LINE       2625
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T76,T178,T163
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T163,T74,T164

 LINE       2628
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T76,T178,T163
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T163,T74,T164

 LINE       2631
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T76,T178,T163
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T163,T74,T165

 LINE       2634
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T76,T178,T163
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T163,T74,T164

 LINE       2637
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T76,T178,T163
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T163,T74,T164

 LINE       2640
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T76,T178,T163
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T163,T74,T164

 LINE       2643
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T76,T178,T163
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T163,T74,T164

 LINE       2646
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T76,T178,T163
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T163,T74,T164

 LINE       2649
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T76,T178,T163
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T163,T74,T164

 LINE       2652
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T76,T178,T163
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T165,T35,T141

 LINE       2675
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T76,T178,T163
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T163,T74,T177

 LINE       2698
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T76,T178,T163
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T35

 LINE       2701
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T76,T178,T163
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T35

 LINE       2704
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T76,T178,T163
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T35

 LINE       2707
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T76,T178,T163
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T35

 LINE       2710
 EXPRESSION (addr_hit[25] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       2711
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T76,T178,T163
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T21,T22,T23

 LINE       2718
 EXPRESSION (addr_hit[26] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       2719
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T76,T178,T163
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T21,T22,T23

 LINE       2726
 EXPRESSION (addr_hit[27] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       2727
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T76,T178,T163
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T21,T22,T23

 LINE       2734
 EXPRESSION (addr_hit[28] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       2735
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T76,T178,T163
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T21,T22,T23

---

Branch Coverage for Module : sensor_ctrl_reg_top

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	2536	2	2	100.00
IF	68	3	3	100.00
CASE	2780	30	30	100.00

2536         assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

68             if (!rst_ni) begin
               -1-  
69               err_q <= '0;
                 ==>
70             end else if (intg_err || reg_we_err) begin
                        -2-  
71               err_q <= 1'b1;
                 ==>
72             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T116,T373,T374
0	0	Covered	T1,T2,T3

2780           unique case (1'b1)
                      -1-  
2781             addr_hit[0]: begin
2782               reg_rdata_next[0] = intr_state_io_status_change_qs;
                   ==>
2783               reg_rdata_next[1] = intr_state_init_status_change_qs;
2784             end
2785       
2786             addr_hit[1]: begin
2787               reg_rdata_next[0] = intr_enable_io_status_change_qs;
                   ==>
2788               reg_rdata_next[1] = intr_enable_init_status_change_qs;
2789             end
2790       
2791             addr_hit[2]: begin
2792               reg_rdata_next[0] = '0;
                   ==>
2793               reg_rdata_next[1] = '0;
2794             end
2795       
2796             addr_hit[3]: begin
2797               reg_rdata_next[0] = '0;
                   ==>
2798               reg_rdata_next[1] = '0;
2799             end
2800       
2801             addr_hit[4]: begin
2802               reg_rdata_next[0] = cfg_regwen_qs;
                   ==>
2803             end
2804       
2805             addr_hit[5]: begin
2806               reg_rdata_next[0] = alert_trig_val_0_qs;
                   ==>
2807               reg_rdata_next[1] = alert_trig_val_1_qs;
2808               reg_rdata_next[2] = alert_trig_val_2_qs;
2809               reg_rdata_next[3] = alert_trig_val_3_qs;
2810               reg_rdata_next[4] = alert_trig_val_4_qs;
2811               reg_rdata_next[5] = alert_trig_val_5_qs;
2812               reg_rdata_next[6] = alert_trig_val_6_qs;
2813               reg_rdata_next[7] = alert_trig_val_7_qs;
2814               reg_rdata_next[8] = alert_trig_val_8_qs;
2815               reg_rdata_next[9] = alert_trig_val_9_qs;
2816               reg_rdata_next[10] = alert_trig_val_10_qs;
2817             end
2818       
2819             addr_hit[6]: begin
2820               reg_rdata_next[3:0] = alert_en_0_qs;
                   ==>
2821             end
2822       
2823             addr_hit[7]: begin
2824               reg_rdata_next[3:0] = alert_en_1_qs;
                   ==>
2825             end
2826       
2827             addr_hit[8]: begin
2828               reg_rdata_next[3:0] = alert_en_2_qs;
                   ==>
2829             end
2830       
2831             addr_hit[9]: begin
2832               reg_rdata_next[3:0] = alert_en_3_qs;
                   ==>
2833             end
2834       
2835             addr_hit[10]: begin
2836               reg_rdata_next[3:0] = alert_en_4_qs;
                   ==>
2837             end
2838       
2839             addr_hit[11]: begin
2840               reg_rdata_next[3:0] = alert_en_5_qs;
                   ==>
2841             end
2842       
2843             addr_hit[12]: begin
2844               reg_rdata_next[3:0] = alert_en_6_qs;
                   ==>
2845             end
2846       
2847             addr_hit[13]: begin
2848               reg_rdata_next[3:0] = alert_en_7_qs;
                   ==>
2849             end
2850       
2851             addr_hit[14]: begin
2852               reg_rdata_next[3:0] = alert_en_8_qs;
                   ==>
2853             end
2854       
2855             addr_hit[15]: begin
2856               reg_rdata_next[3:0] = alert_en_9_qs;
                   ==>
2857             end
2858       
2859             addr_hit[16]: begin
2860               reg_rdata_next[3:0] = alert_en_10_qs;
                   ==>
2861             end
2862       
2863             addr_hit[17]: begin
2864               reg_rdata_next[0] = fatal_alert_en_val_0_qs;
                   ==>
2865               reg_rdata_next[1] = fatal_alert_en_val_1_qs;
2866               reg_rdata_next[2] = fatal_alert_en_val_2_qs;
2867               reg_rdata_next[3] = fatal_alert_en_val_3_qs;
2868               reg_rdata_next[4] = fatal_alert_en_val_4_qs;
2869               reg_rdata_next[5] = fatal_alert_en_val_5_qs;
2870               reg_rdata_next[6] = fatal_alert_en_val_6_qs;
2871               reg_rdata_next[7] = fatal_alert_en_val_7_qs;
2872               reg_rdata_next[8] = fatal_alert_en_val_8_qs;
2873               reg_rdata_next[9] = fatal_alert_en_val_9_qs;
2874               reg_rdata_next[10] = fatal_alert_en_val_10_qs;
2875             end
2876       
2877             addr_hit[18]: begin
2878               reg_rdata_next[0] = recov_alert_val_0_qs;
                   ==>
2879               reg_rdata_next[1] = recov_alert_val_1_qs;
2880               reg_rdata_next[2] = recov_alert_val_2_qs;
2881               reg_rdata_next[3] = recov_alert_val_3_qs;
2882               reg_rdata_next[4] = recov_alert_val_4_qs;
2883               reg_rdata_next[5] = recov_alert_val_5_qs;
2884               reg_rdata_next[6] = recov_alert_val_6_qs;
2885               reg_rdata_next[7] = recov_alert_val_7_qs;
2886               reg_rdata_next[8] = recov_alert_val_8_qs;
2887               reg_rdata_next[9] = recov_alert_val_9_qs;
2888               reg_rdata_next[10] = recov_alert_val_10_qs;
2889             end
2890       
2891             addr_hit[19]: begin
2892               reg_rdata_next[0] = fatal_alert_val_0_qs;
                   ==>
2893               reg_rdata_next[1] = fatal_alert_val_1_qs;
2894               reg_rdata_next[2] = fatal_alert_val_2_qs;
2895               reg_rdata_next[3] = fatal_alert_val_3_qs;
2896               reg_rdata_next[4] = fatal_alert_val_4_qs;
2897               reg_rdata_next[5] = fatal_alert_val_5_qs;
2898               reg_rdata_next[6] = fatal_alert_val_6_qs;
2899               reg_rdata_next[7] = fatal_alert_val_7_qs;
2900               reg_rdata_next[8] = fatal_alert_val_8_qs;
2901               reg_rdata_next[9] = fatal_alert_val_9_qs;
2902               reg_rdata_next[10] = fatal_alert_val_10_qs;
2903               reg_rdata_next[11] = fatal_alert_val_11_qs;
2904             end
2905       
2906             addr_hit[20]: begin
2907               reg_rdata_next[0] = status_ast_init_done_qs;
                   ==>
2908               reg_rdata_next[2:1] = status_io_pok_qs;
2909             end
2910       
2911             addr_hit[21]: begin
2912               reg_rdata_next[0] = manual_pad_attr_regwen_0_qs;
                   ==>
2913             end
2914       
2915             addr_hit[22]: begin
2916               reg_rdata_next[0] = manual_pad_attr_regwen_1_qs;
                   ==>
2917             end
2918       
2919             addr_hit[23]: begin
2920               reg_rdata_next[0] = manual_pad_attr_regwen_2_qs;
                   ==>
2921             end
2922       
2923             addr_hit[24]: begin
2924               reg_rdata_next[0] = manual_pad_attr_regwen_3_qs;
                   ==>
2925             end
2926       
2927             addr_hit[25]: begin
2928               reg_rdata_next[2] = manual_pad_attr_0_pull_en_0_qs;
                   ==>
2929               reg_rdata_next[3] = manual_pad_attr_0_pull_select_0_qs;
2930               reg_rdata_next[7] = manual_pad_attr_0_input_disable_0_qs;
2931             end
2932       
2933             addr_hit[26]: begin
2934               reg_rdata_next[2] = manual_pad_attr_1_pull_en_1_qs;
                   ==>
2935               reg_rdata_next[3] = manual_pad_attr_1_pull_select_1_qs;
2936               reg_rdata_next[7] = manual_pad_attr_1_input_disable_1_qs;
2937             end
2938       
2939             addr_hit[27]: begin
2940               reg_rdata_next[2] = manual_pad_attr_2_pull_en_2_qs;
                   ==>
2941               reg_rdata_next[3] = manual_pad_attr_2_pull_select_2_qs;
2942               reg_rdata_next[7] = manual_pad_attr_2_input_disable_2_qs;
2943             end
2944       
2945             addr_hit[28]: begin
2946               reg_rdata_next[2] = manual_pad_attr_3_pull_en_3_qs;
                   ==>
2947               reg_rdata_next[3] = manual_pad_attr_3_pull_select_3_qs;
2948               reg_rdata_next[7] = manual_pad_attr_3_input_disable_3_qs;
2949             end
2950       
2951             default: begin
2952               reg_rdata_next = '1;
                   ==>

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : sensor_ctrl_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	117369941	5467	0	0
reAfterRv	117369941	5467	0	0
rePulse	117369941	3932	0	0
wePulse	117369941	1535	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	117369941	5467	0	0
T1	19386	1	0	0
T2	14770	1	0	0
T3	51043	1	0	0
T4	30021	1	0	0
T5	71116	1	0	0
T6	23610	1	0	0
T29	18364	1	0	0
T33	23667	1	0	0
T103	10522	1	0	0
T104	15617	1	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	117369941	5467	0	0
T1	19386	1	0	0
T2	14770	1	0	0
T3	51043	1	0	0
T4	30021	1	0	0
T5	71116	1	0	0
T6	23610	1	0	0
T29	18364	1	0	0
T33	23667	1	0	0
T103	10522	1	0	0
T104	15617	1	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	117369941	3932	0	0
T1	19386	1	0	0
T2	14770	1	0	0
T3	51043	1	0	0
T4	30021	1	0	0
T5	71116	1	0	0
T6	23610	1	0	0
T29	18364	1	0	0
T33	23667	1	0	0
T103	10522	1	0	0
T104	15617	1	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	117369941	1535	0	0
T35	0	22	0	0
T64	84161	0	0	0
T74	0	14	0	0
T75	0	80	0	0
T76	27903	2	0	0
T123	0	6	0	0
T148	88254	0	0	0
T163	0	55	0	0
T164	0	28	0	0
T165	0	26	0	0
T177	0	1	0	0
T178	0	12	0	0
T207	103717	0	0	0
T245	56962	0	0	0
T246	60023	0	0	0
T273	51611	0	0	0
T282	54517	0	0	0
T292	38279	0	0	0
T293	67470	0	0	0