Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T6,T33,T31	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T6,T33,T31	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T6,T33,T31	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T6,T33,T31	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T6,T33,T31	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T95,T286,T184	Yes	T94,T95,T96	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T95,T190,T247	Yes	T95,T190,T247	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T97,T244,T213	Yes	T97,T244,T213	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T280,T97,T244	Yes	T280,T97,T244	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T35,T98,T67	Yes	T35,T98,T67	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T35,T98,T67	Yes	T35,T98,T67	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T35,T98,T67	Yes	T35,T98,T67	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T84,T245,T246	Yes	T84,T245,T246	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T33,T44,T45	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T85,T89,T97	Yes	T85,T89,T97	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T33,T44,T45	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T33,T44,T45	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T85,T89,T97	Yes	T85,T89,T97	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T33,T44,T45	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T85,T89,T97	Yes	T85,T89,T97	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T6,T33,T31	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T85,T89,T97	Yes	T85,T89,T97	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T85,T89,T35	Yes	T85,T89,T35	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T85,T89,T97	Yes	T85,T89,T97	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T85,*T89,*T97	Yes	T85,T89,T97	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T85,T89,T97	Yes	T85,T89,T97	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T6,T33,T31	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T71,T94,T95	Yes	T71,T94,T95	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T71,T94,T95	Yes	T71,T94,T95	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T71,T94,T95	Yes	T71,T94,T95	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T71,T94,T95	Yes	T71,T94,T95	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T71,T95,T96	Yes	T71,T95,T96	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T71,T94,T95	Yes	T71,T94,T95	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T71,T94,T95	Yes	T71,T94,T95	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T71,T95,T286	Yes	T71,T94,T95	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T71,T94,T95	Yes	T71,T94,T95	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T71,T94,T95	Yes	T71,T94,T95	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T71,T95,T96	Yes	T71,T94,T95	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T95,T96,T99	Yes	T94,T95,T96	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T71,*T94,*T95	Yes	T71,T95,T96	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T71,T94,T95	Yes	T71,T94,T95	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T6,T33,T31	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T97,T35,T56	Yes	T97,T35,T56	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T97,T35,T56	Yes	T97,T35,T56	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T97,T35,T56	Yes	T97,T35,T56	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T97,T35,T56	Yes	T97,T35,T56	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T97,T35,T56	Yes	T97,T35,T56	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T97,*T56,*T57	Yes	T97,T56,T57	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T97,T35,T56	Yes	T97,T35,T56	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T33,T44,T45	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T97,T56,T57	Yes	T97,T56,T57	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T97,T35,T56	Yes	T97,T35,T56	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T33,T44,T45	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T97,*T56,*T57	Yes	T97,T56,T57	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T33,T44,T45	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T97,T35,T56	Yes	T97,T35,T56	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T103,T243,T85	Yes	T103,T243,T85	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T205,T404,T98	Yes	T205,T404,T98	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T94,*T95,*T96	Yes	T94,T95,T96	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T6,T33,T31	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T76,T405,T298	Yes	T76,T405,T298	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T76,T405,T298	Yes	T76,T405,T298	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T76,T405,T298	Yes	T76,T405,T298	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T71,*T94,*T95	Yes	T71,T94,T95	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T76,T405,T298	Yes	T76,T405,T298	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T76,T405,T298	Yes	T76,T405,T298	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T94,T95,T96	Yes	T94,T96,T184	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T405,T298,T406	Yes	T405,T298,T406	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T71,T94,T95	Yes	T76,T77,T78	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T405,T298,T406	Yes	T76,T405,T298	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T71,*T96,*T190	Yes	T71,T94,T95	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T96,T99	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T298,*T407,*T408	Yes	T405,T298,T406	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T76,T405,T298	Yes	T76,T405,T298	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T97,*T35,*T98	Yes	T97,T35,T98	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T35,T98,T67	Yes	T35,T98,T67	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T280,T306,T300	Yes	T280,T306,T300	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T97,*T35,*T98	Yes	T97,T35,T98	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T10,T239,T11	Yes	T10,T239,T11	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T10,T239,T11	Yes	T10,T239,T11	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T10,T239,T11	Yes	T10,T239,T11	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T10,T239,T11	Yes	T10,T239,T11	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T10,T239,T11	Yes	T10,T239,T11	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T10,T239,T11	Yes	T10,T239,T11	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T35,*T94,*T95	Yes	T35,T94,T95	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T11,T229,T231	Yes	T11,T229,T231	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T10,T239,T11	Yes	T10,T239,T11	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T10,T239,T11	Yes	T10,T239,T11	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T94,T96,T99	Yes	T94,T96,T99	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T10,T239,T11	Yes	T10,T239,T11	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T10,T239,T11	Yes	T10,T239,T11	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T10,T239,T11	Yes	T10,T239,T11	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T94,T95,T184	Yes	T94,T96,T99	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T35,*T190,*T247	Yes	T35,T94,T95	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T94,T95,T99	Yes	T94,T95,T96	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T10,*T239,*T11	Yes	T10,T239,T11	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T10,T239,T11	Yes	T10,T239,T11	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T239,T76,T123	Yes	T239,T76,T123	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T239,T76,T123	Yes	T239,T76,T123	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T239,T76,T123	Yes	T239,T76,T123	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T239,T76,T123	Yes	T239,T76,T123	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T239,T76,T123	Yes	T239,T76,T123	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T239,T76,T123	Yes	T239,T76,T123	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T35,*T94,*T95	Yes	T35,T94,T95	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T239,T76,T123	Yes	T239,T76,T123	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T239,T76,T123	Yes	T239,T76,T123	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T94,T95,T96	Yes	T95,T96,T99	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T239,T123,T35	Yes	T239,T123,T35	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T239,T123,T409	Yes	T239,T76,T123	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T239,T123,T35	Yes	T239,T123,T35	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T35,*T96,*T184	Yes	T35,T95,T96	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T95,T96,T99	Yes	T94,T95,T96	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T239,*T123,*T409	Yes	T239,T123,T409	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T239,T76,T123	Yes	T239,T76,T123	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T7,T8,T70	Yes	T7,T8,T70	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T7,T8,T239	Yes	T7,T8,T239	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T7,T8,T70	Yes	T7,T8,T70	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T7,T8,T70	Yes	T7,T8,T70	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T7,T8,T239	Yes	T7,T8,T239	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T7,T8,T70	Yes	T7,T8,T70	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T71,*T94,*T95	Yes	T71,T94,T95	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T94,T95,T99	Yes	T94,T95,T99	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T94,T95,T99	Yes	T94,T95,T99	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T7,T8,T70	Yes	T7,T8,T70	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T7,T8,T70	Yes	T7,T8,T70	INPUT
tl_usbdev_i.d_error	Yes	Yes	T94,T95,T190	Yes	T94,T95,T190	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T7,T8,T239	Yes	T7,T8,T70	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T7,T8,T70	Yes	T7,T8,T239	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T7,T8,T70	Yes	T7,T8,T239	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T94,T95,T99	Yes	T94,T95,T99	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T71,*T94,*T190	Yes	T71,T94,T95	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T94,T95,T99	Yes	T94,T95,T99	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T7,*T8,*T239	Yes	T7,T8,T239	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T7,T8,T70	Yes	T7,T8,T70	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T94,*T95,*T96	Yes	T94,T95,T96	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T94,T96,T99	Yes	T94,T96,T99	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T6,T33,T31	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T6,T33,T118	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T94,T96,T99	Yes	T94,T95,T96	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T96,*T190,*T247	Yes	T94,T95,T96	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T6,T33,T31	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T94,T96,T99	Yes	T94,T96,T99	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T94,T96,T99	Yes	T94,T96,T99	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	T94,T96,T99	Yes	T94,T96,T99	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T95,T286,T184	Yes	T94,T95,T96	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T94,T96,T99	Yes	T94,T95,T96	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	T95,T96,T184	Yes	T94,T95,T96	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T94,*T95,*T96	Yes	T94,T95,T96	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T3,T6,T4	Yes	T3,T6,T4	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T6,T33,T31	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T94,*T95,*T96	Yes	T94,T95,T96	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_hmac_o.d_ready	Yes	Yes	T6,T33,T31	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T76,T294,T685	Yes	T76,T294,T685	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T76,T294,T685	Yes	T76,T294,T685	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T76,T294,T685	Yes	T76,T294,T685	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T76,T294,T685	Yes	T76,T294,T685	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T76,T294,T685	Yes	T76,T294,T685	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T94,*T95,*T96	Yes	T94,T95,T96	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T294,T685,T342	Yes	T294,T685,T342	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T76,T294,T685	Yes	T76,T294,T685	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T76,T294,T685	Yes	T76,T294,T685	INPUT
tl_hmac_i.d_error	Yes	Yes	T94,T95,T99	Yes	T94,T95,T99	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T294,T685,T342	Yes	T294,T685,T342	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T294,T685,T342	Yes	T294,T685,T342	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T76,T294,T685	Yes	T294,T685,T342	INPUT
tl_hmac_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T99	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T94,*T99,*T190	Yes	T94,T95,T96	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T99	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T76,*T294,*T685	Yes	T294,T685,T342	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T76,T294,T685	Yes	T76,T294,T685	INPUT
tl_kmac_o.d_ready	Yes	Yes	T6,T33,T31	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T426,T76,T295	Yes	T426,T76,T295	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T426,T189,T204	Yes	T426,T189,T204	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T426,T189,T204	Yes	T426,T189,T204	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T426,T76,T295	Yes	T426,T76,T295	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T426,T189,T204	Yes	T426,T189,T204	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T67,*T94,*T95	Yes	T67,T94,T95	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T94,T96,T184	Yes	T94,T96,T184	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T426,T295,T456	Yes	T426,T295,T456	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T426,T189,T204	Yes	T426,T189,T204	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T426,T189,T204	Yes	T426,T189,T204	INPUT
tl_kmac_i.d_error	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T426,T189,T204	Yes	T426,T189,T204	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T426,T189,T204	Yes	T426,T189,T204	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T426,T189,T204	Yes	T426,T204,T207	INPUT
tl_kmac_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T96,T99	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T67,*T94,*T95	Yes	T67,T94,T95	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T426,*T189,*T204	Yes	T426,T204,T207	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T426,T189,T204	Yes	T426,T189,T204	INPUT
tl_aes_o.d_ready	Yes	Yes	T6,T33,T31	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T676,T683,T147	Yes	T676,T683,T147	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T676,T683,T147	Yes	T676,T683,T147	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T676,T683,T147	Yes	T676,T683,T147	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T676,T683,T147	Yes	T676,T683,T147	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T676,T683,T147	Yes	T676,T683,T147	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T95,*T99,*T184	Yes	T95,T99,T184	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T94,T184,T190	Yes	T94,T184,T190	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T94,T95,T99	Yes	T94,T95,T99	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T676,T683,T147	Yes	T676,T683,T147	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T676,T683,T147	Yes	T676,T683,T147	INPUT
tl_aes_i.d_error	Yes	Yes	T94,T95,T184	Yes	T94,T95,T184	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T676,T683,T147	Yes	T676,T683,T147	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T676,T683,T147	Yes	T676,T683,T147	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T676,T683,T147	Yes	T676,T683,T147	INPUT
tl_aes_i.d_sink	Yes	Yes	T94,T95,T184	Yes	T95,T96,T99	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T94,*T184,*T190	Yes	T94,T95,T184	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T94,T184,T190	Yes	T94,T184,T190	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T676,*T683,*T147	Yes	T676,T683,T147	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T676,T683,T147	Yes	T676,T683,T147	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T94,*T95,*T96	Yes	T94,T95,T96	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T94,T96,T99	Yes	T94,T96,T99	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T94,T96,T190	Yes	T94,T96,T190	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T94,T95,T99	Yes	T94,T95,T99	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T160,T157,T161	Yes	T160,T157,T161	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T33,T44	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T6,T33,T44	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T95,*T96,*T190	Yes	T94,T95,T96	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T95,T96,T99	Yes	T94,T95,T96	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T160,*T157,*T161	Yes	T160,T157,T161	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T649,T160,T76	Yes	T649,T160,T76	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T94,*T95,*T96	Yes	T94,T95,T96	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T95,T96,T184	Yes	T95,T96,T184	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T649,T160,T157	Yes	T649,T160,T157	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T33,T44	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T6,T33,T44	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T94,*T95,*T96	Yes	T94,T95,T96	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T94,T95,T99	Yes	T94,T95,T96	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T649,*T160,*T157	Yes	T649,T160,T157	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T649,T160,T76	Yes	T649,T160,T76	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T649,T160,T76	Yes	T649,T160,T76	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T94,*T96,*T99	Yes	T94,T96,T99	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T94,T96,T99	Yes	T94,T96,T99	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T649,T160,T157	Yes	T649,T160,T157	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T33,T44	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T6,T33,T44	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T94,*T95,*T190	Yes	T94,T95,T96	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T96,T99	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T649,*T160,*T157	Yes	T649,T160,T157	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T6,T33,T31	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T160,T76,T157	Yes	T160,T76,T157	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T160,T76,T157	Yes	T160,T76,T157	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T160,T76,T157	Yes	T160,T76,T157	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T160,T76,T157	Yes	T160,T76,T157	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T160,T76,T157	Yes	T160,T76,T157	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T95,*T96,*T99	Yes	T95,T96,T99	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T96,T184,T190	Yes	T96,T184,T190	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T95,T99,T184	Yes	T95,T99,T184	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T160,T76,T157	Yes	T160,T76,T157	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T160,T76,T157	Yes	T160,T76,T157	INPUT
tl_edn1_i.d_error	Yes	Yes	T95,T190,T247	Yes	T99,T190,T247	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T160,T157,T158	Yes	T160,T157,T158	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T157,T158,T159	Yes	T160,T76,T157	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T157,T158,T159	Yes	T160,T76,T157	INPUT
tl_edn1_i.d_sink	Yes	Yes	T95,T96,T247	Yes	T96,T99,T184	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T96,*T190,*T247	Yes	T95,T99,T190	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T96,T184,T247	Yes	T184,T190,T247	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T160,*T157,*T158	Yes	T160,T157,T158	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T160,T76,T157	Yes	T160,T76,T157	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T3,T6,T4	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T35,*T94,*T95	Yes	T35,T94,T95	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T94,T95,T99	Yes	T94,T95,T99	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T94,T95,T99	Yes	T94,T99,T184	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T99,T184	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T35,*T94,*T96	Yes	T35,T94,T95	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T94,T95,T99	Yes	T94,T95,T99	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T3,*T4,*T5	Yes	T3,T4,T5	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_otbn_o.d_ready	Yes	Yes	T6,T33,T31	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T215,T76,T157	Yes	T215,T76,T157	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T215,T76,T157	Yes	T215,T76,T157	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T215,T76,T157	Yes	T215,T76,T157	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T215,T76,T157	Yes	T215,T76,T157	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T215,T76,T157	Yes	T215,T76,T157	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T98,*T67,*T233	Yes	T98,T67,T233	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T215,T76,T157	Yes	T215,T76,T157	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T215,T76,T157	Yes	T215,T76,T157	INPUT
tl_otbn_i.d_error	Yes	Yes	T94,T95,T96	Yes	T94,T95,T184	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T215,T157,T344	Yes	T215,T157,T344	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T215,T157,T344	Yes	T215,T157,T344	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T215,T76,T157	Yes	T215,T157,T344	INPUT
tl_otbn_i.d_sink	Yes	Yes	T94,T95,T184	Yes	T94,T95,T96	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T98,*T67,*T233	Yes	T98,T67,T233	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T215,*T76,*T157	Yes	T215,T157,T344	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T215,T76,T157	Yes	T215,T76,T157	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T6,T33,T31	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T189,T204,T76	Yes	T189,T204,T76	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T189,T204,T76	Yes	T189,T204,T76	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T189,T204,T76	Yes	T189,T204,T76	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T204,T76,T207	Yes	T204,T76,T207	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T189,T204,T76	Yes	T189,T204,T76	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T94,*T95,*T96	Yes	T94,T95,T96	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T94,T96,T99	Yes	T94,T96,T99	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T189,T204,T76	Yes	T189,T204,T76	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T189,T204,T76	Yes	T189,T204,T76	INPUT
tl_keymgr_i.d_error	Yes	Yes	T95,T99,T190	Yes	T99,T190,T247	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T204,T207,T248	Yes	T204,T207,T248	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T204,T207,T248	Yes	T204,T76,T207	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T204,T207,T248	Yes	T204,T76,T207	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T94,T96,T99	Yes	T94,T96,T99	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T96,*T99,*T190	Yes	T94,T95,T96	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T96,T99	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T204,*T207,*T248	Yes	T189,T204,T207	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T189,T204,T76	Yes	T189,T204,T76	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T57,*T71,*T94	Yes	T57,T71,T94	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T71,T94,T95	Yes	T71,T96,T99	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T6,T4,T5	Yes	T6,T4,T5	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T6,T4,T5	Yes	T6,T4,T5	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T95,T99,T184	Yes	T94,T95,T99	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T71,*T96,*T190	Yes	T57,T71,T94	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T94,T95,T99	Yes	T94,T96,T184	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T6,T33,T31	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T76,T208,T149	Yes	T76,T208,T149	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T76,T208,T149	Yes	T76,T208,T149	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T76,T208,T149	Yes	T76,T208,T149	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T76,T208,T149	Yes	T76,T208,T149	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T76,T208,T149	Yes	T76,T208,T149	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T35,*T440,*T441	Yes	T35,T440,T441	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T94,T96,T99	Yes	T94,T96,T99	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T76,T208,T149	Yes	T76,T208,T149	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T76,T208,T149	Yes	T76,T208,T149	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T94,T99,T184	Yes	T94,T99,T190	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T213,T35,T326	Yes	T213,T35,T326	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T208,T149,T213	Yes	T76,T208,T149	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T208,T149,T213	Yes	T76,T208,T149	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T94,T96,T99	Yes	T94,T96,T190	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T35,*T96,*T286	Yes	T35,T440,T441	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T96,T99,T286	Yes	T96,T99,T190	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T208,*T149,*T213	Yes	T208,T149,T213	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T76,T208,T149	Yes	T76,T208,T149	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T6,T33,T31	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range