Module Definition
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Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_esc_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.27 94.12 89.29 99.75 100.00 68.18 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_esc_receiver
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 14 14 100.00
Total Bits 0->1 7 7 100.00
Total Bits 1->0 7 7 100.00

Ports 7 7 100.00
Port Bits 14 14 100.00
Port Bits 0->1 7 7 100.00
Port Bits 1->0 7 7 100.00

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T6,T33,T31 Yes T1,T2,T3 INPUT
esc_req_o Yes Yes T82,T83,T84 Yes T82,T83,T84 OUTPUT
esc_rx_o.resp_n Yes Yes T82,T83,T84 Yes T82,T83,T84 OUTPUT
esc_rx_o.resp_p Yes Yes T82,T83,T84 Yes T82,T83,T84 OUTPUT
esc_tx_i.esc_n Yes Yes T82,T83,T84 Yes T82,T83,T84 INPUT
esc_tx_i.esc_p Yes Yes T82,T83,T84 Yes T82,T83,T84 INPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_esc_receiver
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 14 14 100.00
Total Bits 0->1 7 7 100.00
Total Bits 1->0 7 7 100.00

Ports 7 7 100.00
Port Bits 14 14 100.00
Port Bits 0->1 7 7 100.00
Port Bits 1->0 7 7 100.00

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T6,T33,T31 Yes T1,T2,T3 INPUT
esc_req_o Yes Yes T82,T83,T84 Yes T82,T83,T84 OUTPUT
esc_rx_o.resp_n Yes Yes T82,T83,T84 Yes T82,T83,T84 OUTPUT
esc_rx_o.resp_p Yes Yes T82,T83,T84 Yes T82,T83,T84 OUTPUT
esc_tx_i.esc_n Yes Yes T82,T83,T84 Yes T82,T83,T84 INPUT
esc_tx_i.esc_p Yes Yes T82,T83,T84 Yes T82,T83,T84 INPUT