Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_peri_ni	Yes	Yes	T6,T33,T31	Yes	T1,T2,T3	INPUT
tl_main_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T97,*T35,*T98	Yes	T97,T35,T98	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T35,T98,T67	Yes	T35,T98,T67	INPUT
tl_main_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_error	Yes	Yes	T280,T306,T300	Yes	T280,T306,T300	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T97,*T35,*T98	Yes	T97,T35,T98	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T127,T128,T249	Yes	T127,T128,T249	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T127,T128,T249	Yes	T127,T128,T249	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T97,*T35,*T98	Yes	T97,T35,T98	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T35,T98,T67	Yes	T35,T98,T67	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T127,T128,T76	Yes	T127,T128,T76	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T127,T128,T76	Yes	T127,T128,T76	INPUT
tl_uart0_i.d_error	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T127,T128,T331	Yes	T127,T128,T331	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T127,T128,T193	Yes	T127,T128,T76	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T127,T128,T193	Yes	T127,T128,T76	INPUT
tl_uart0_i.d_sink	Yes	Yes	T94,T96,T99	Yes	T94,T95,T96	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T56,*T58,*T71	Yes	T56,T58,T71	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T94,T96,T99	Yes	T94,T96,T99	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T127,*T128,*T331	Yes	T127,T128,T331	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T127,T128,T76	Yes	T127,T128,T76	INPUT
tl_uart1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T130,T131,T331	Yes	T130,T131,T331	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T130,T131,T331	Yes	T130,T131,T331	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T97,*T35,*T98	Yes	T97,T35,T98	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T35,T98,T67	Yes	T35,T98,T67	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T130,T131,T76	Yes	T130,T131,T76	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T130,T131,T76	Yes	T130,T131,T76	INPUT
tl_uart1_i.d_error	Yes	Yes	T94,T95,T247	Yes	T94,T95,T247	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T130,T131,T331	Yes	T130,T131,T331	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T130,T131,T193	Yes	T130,T131,T76	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T130,T131,T193	Yes	T130,T131,T76	INPUT
tl_uart1_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T95,T96,T99	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T71,*T247,*T465	Yes	T71,T94,T95	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T94,T96,T184	Yes	T94,T96,T99	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T130,*T131,*T331	Yes	T130,T131,T331	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T130,T131,T76	Yes	T130,T131,T76	INPUT
tl_uart2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T3,T65,T331	Yes	T3,T65,T331	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T3,T65,T331	Yes	T3,T65,T331	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T97,*T35,*T98	Yes	T97,T35,T98	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T35,T98,T67	Yes	T35,T98,T67	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T3,T76,T65	Yes	T3,T76,T65	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T3,T76,T65	Yes	T3,T76,T65	INPUT
tl_uart2_i.d_error	Yes	Yes	T95,T96,T99	Yes	T95,T99,T184	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T3,T65,T331	Yes	T3,T65,T331	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T65,T193	Yes	T3,T76,T65	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T3,T65,T193	Yes	T3,T76,T65	INPUT
tl_uart2_i.d_sink	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T71,*T95,*T96	Yes	T71,T95,T96	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T3,*T65,*T331	Yes	T3,T65,T331	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T3,T76,T65	Yes	T3,T76,T65	INPUT
tl_uart3_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T37,T331,T52	Yes	T37,T331,T52	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T37,T331,T52	Yes	T37,T331,T52	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T97,*T35,*T98	Yes	T97,T35,T98	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T35,T98,T67	Yes	T35,T98,T67	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T37,T76,T193	Yes	T37,T76,T193	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T37,T76,T193	Yes	T37,T76,T193	INPUT
tl_uart3_i.d_error	Yes	Yes	T94,T95,T99	Yes	T94,T95,T96	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T37,T331,T52	Yes	T37,T331,T52	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T37,T193,T331	Yes	T37,T76,T193	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T37,T193,T331	Yes	T37,T76,T193	INPUT
tl_uart3_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T184	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T71,*T94,*T95	Yes	T71,T94,T95	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T99	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T37,*T331,*T52	Yes	T37,T331,T52	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T37,T76,T193	Yes	T37,T76,T193	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T5,T239,T334	Yes	T5,T239,T334	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T5,T239,T334	Yes	T5,T239,T334	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T97,*T35,*T98	Yes	T97,T35,T98	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T35,T98,T67	Yes	T35,T98,T67	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T5,T239,T76	Yes	T5,T239,T76	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T5,T239,T76	Yes	T5,T239,T76	INPUT
tl_i2c0_i.d_error	Yes	Yes	T94,T95,T99	Yes	T94,T95,T99	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T5,T334,T52	Yes	T5,T334,T52	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T239,T193	Yes	T5,T239,T76	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T5,T239,T193	Yes	T5,T239,T76	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T94,*T95,*T96	Yes	T94,T95,T96	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T5,*T239,*T334	Yes	T5,T239,T334	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T5,T239,T76	Yes	T5,T239,T76	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T239,T61,T334	Yes	T239,T61,T334	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T239,T61,T334	Yes	T239,T61,T334	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T97,*T35,*T98	Yes	T97,T35,T98	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T35,T98,T67	Yes	T35,T98,T67	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T239,T61,T76	Yes	T239,T61,T76	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T239,T61,T76	Yes	T239,T61,T76	INPUT
tl_i2c1_i.d_error	Yes	Yes	T95,T99,T184	Yes	T95,T99,T184	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T61,T334,T52	Yes	T61,T334,T52	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T239,T61,T193	Yes	T239,T61,T76	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T239,T61,T193	Yes	T239,T61,T76	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T94,T95,T99	Yes	T95,T96,T99	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T99,*T184,*T190	Yes	T94,T95,T99	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T94,T99,T184	Yes	T94,T96,T99	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T239,*T61,*T334	Yes	T239,T61,T334	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T239,T61,T76	Yes	T239,T61,T76	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T239,T63,T64	Yes	T239,T63,T64	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T239,T63,T64	Yes	T239,T63,T64	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T97,*T35,*T98	Yes	T97,T35,T98	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T35,T98,T67	Yes	T35,T98,T67	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T239,T63,T76	Yes	T239,T63,T76	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T239,T63,T76	Yes	T239,T63,T76	INPUT
tl_i2c2_i.d_error	Yes	Yes	T94,T95,T184	Yes	T94,T95,T184	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T63,T64,T334	Yes	T63,T64,T334	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T239,T63,T64	Yes	T239,T63,T76	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T239,T63,T64	Yes	T239,T63,T76	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T94,T95,T99	Yes	T94,T95,T96	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T95,*T190,*T247	Yes	T94,T95,T99	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T94,T95,T99	Yes	T94,T95,T99	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T239,*T63,*T64	Yes	T239,T63,T64	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T239,T63,T76	Yes	T239,T63,T76	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T29,T123,T135	Yes	T29,T123,T135	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T29,T123,T135	Yes	T29,T123,T135	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T97,*T35,*T98	Yes	T97,T35,T98	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T35,T98,T67	Yes	T35,T98,T67	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T29,T76,T123	Yes	T29,T76,T123	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T29,T76,T123	Yes	T29,T76,T123	INPUT
tl_pattgen_i.d_error	Yes	Yes	T94,T96,T99	Yes	T95,T96,T99	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T29,T123,T135	Yes	T29,T123,T135	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T29,T123,T135	Yes	T29,T76,T123	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T29,T123,T135	Yes	T29,T76,T123	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T96,T99,T184	Yes	T96,T99,T286	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	*T67,*T96,*T286	Yes	T67,T96,T99	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T96,T99,T190	Yes	T95,T96,T99	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T29,*T123,*T135	Yes	T29,T123,T135	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T29,T76,T123	Yes	T29,T76,T123	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T32,T72,T137	Yes	T32,T72,T137	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T32,T72,T137	Yes	T32,T72,T137	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T97,*T35,*T98	Yes	T97,T35,T98	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T35,T98,T67	Yes	T35,T98,T67	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T76,T32,T72	Yes	T76,T32,T72	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T76,T32,T72	Yes	T76,T32,T72	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T94,T95,T96	Yes	T94,T96,T286	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T32,T72,T137	Yes	T32,T72,T137	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T32,T72,T137	Yes	T76,T32,T72	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T32,T72,T137	Yes	T76,T32,T72	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T94,T96,T99	Yes	T94,T95,T96	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	*T71,*T96,*T184	Yes	T71,T94,T95	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T96,T99,T286	Yes	T94,T96,T99	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T32,*T72,*T137	Yes	T32,T72,T137	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T76,T32,T72	Yes	T76,T32,T72	INPUT
tl_gpio_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T97,*T35,*T98	Yes	T97,T35,T98	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T35,T98,T67	Yes	T35,T98,T67	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_gpio_i.d_error	Yes	Yes	T94,T95,T190	Yes	T94,T95,T96	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T27,T13,T334	Yes	T27,T13,T334	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T27,T13,T334	Yes	T4,T27,T13	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T27,T13,T334	Yes	T4,T27,T13	INPUT
tl_gpio_i.d_sink	Yes	Yes	T94,T96,T99	Yes	T94,T95,T96	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T94,*T96,*T190	Yes	T94,T95,T96	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T6,*T4,*T33	Yes	T1,T2,T3	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T13,T14,T239	Yes	T13,T14,T239	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T13,T14,T239	Yes	T13,T14,T239	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T97,*T35,*T98	Yes	T97,T35,T98	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T35,T98,T67	Yes	T35,T98,T67	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T13,T14,T239	Yes	T13,T14,T239	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T13,T14,T239	Yes	T13,T14,T239	INPUT
tl_spi_device_i.d_error	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T14,T239,T11	Yes	T14,T239,T11	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T13,T14,T239	Yes	T13,T14,T239	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T13,T14,T239	Yes	T14,T239,T11	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T94,T96,T99	Yes	T94,T96,T99	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T35,*T96,*T190	Yes	T35,T94,T95	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T13,*T14,*T239	Yes	T13,T14,T239	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T13,T14,T239	Yes	T13,T14,T239	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T122,T272,T123	Yes	T122,T272,T123	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T122,T272,T123	Yes	T122,T272,T123	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T97,*T35,*T98	Yes	T97,T35,T98	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T35,T98,T67	Yes	T35,T98,T67	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T122,T272,T76	Yes	T122,T272,T76	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T122,T272,T76	Yes	T122,T272,T76	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T122,T272,T123	Yes	T122,T272,T123	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T122,T272,T123	Yes	T122,T272,T76	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T122,T272,T698	Yes	T122,T272,T76	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T95,T96,T99	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T35,*T96,*T99	Yes	T35,T94,T95	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T122,*T272,*T123	Yes	T122,T272,T123	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T122,T272,T76	Yes	T122,T272,T76	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T6,T4,T13	Yes	T6,T4,T13	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T6,T4,T13	Yes	T6,T4,T13	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T97,*T35,*T98	Yes	T97,T35,T98	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T35,T98,T67	Yes	T35,T98,T67	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T6,T4,T13	Yes	T6,T4,T13	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T6,T4,T13	Yes	T6,T4,T13	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T95,T184,T190	Yes	T95,T184,T190	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T6,T4,T13	Yes	T6,T4,T13	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T4,T13	Yes	T6,T4,T13	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T6,T4,T13	Yes	T6,T4,T13	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T99	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T71,*T96,*T286	Yes	T71,T94,T95	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T6,*T4,*T13	Yes	T6,T4,T13	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T6,T4,T13	Yes	T6,T4,T13	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T97,*T35,*T98	Yes	T97,T35,T98	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T35,T98,T67	Yes	T35,T98,T67	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T94,T184,T190	Yes	T94,T95,T96	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T33,T44,T239	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T33,T44,T24	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T71,*T95,*T96	Yes	T71,T94,T95	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T3,T130,T127	Yes	T3,T130,T127	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T3,T130,T127	Yes	T3,T130,T127	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T97,*T35,*T98	Yes	T97,T35,T98	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T35,T98,T67	Yes	T35,T98,T67	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T94,T95,T96	Yes	T94,T96,T99	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T3,T130,T127	Yes	T3,T130,T127	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T33,T44	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T3,T33,T44	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T94,*T96,*T99	Yes	T185,T186,T693	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T3,*T130,*T127	Yes	T3,T130,T127	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T97,*T35,*T98	Yes	T97,T35,T98	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T35,T98,T67	Yes	T35,T98,T67	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T94,T96,T99	Yes	T94,T96,T99	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T94,T96,T99	Yes	T94,T96,T99	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T67,*T71,*T94	Yes	T67,T71,T94	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T94,T96,T99	Yes	T94,T96,T99	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T97,*T35,*T98	Yes	T97,T35,T98	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T35,T98,T67	Yes	T35,T98,T67	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T96,T99,T184	Yes	T96,T99,T184	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T94,T96,T99	Yes	T94,T96,T99	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T185,*T186,*T67	Yes	T185,T186,T67	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T94,T96,T99	Yes	T94,T96,T99	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T34,*T187,*T188	Yes	T187,T188,T189	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T67,T94,T95	Yes	T67,T94,T95	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T67,T94,T95	Yes	T67,T94,T95	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T97,*T35,*T98	Yes	T97,T35,T98	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T35,T98,T67	Yes	T35,T98,T67	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T67,T94,T95	Yes	T67,T94,T95	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T1,T2,T3	Yes	T33,T44,T45	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T67,T94,T95	Yes	T67,T94,T95	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T67,T94,T96	Yes	T67,T94,T96	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T33,T44,T45	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T67,T184,T190	Yes	T67,T94,T95	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T96,T184	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T33,T44,T45	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T67,T94,T95	Yes	T67,T94,T95	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T33,T118,T188	Yes	T33,T118,T188	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T33,T118,T188	Yes	T33,T118,T188	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T97,*T35,*T98	Yes	T97,T35,T98	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T35,T98,T67	Yes	T35,T98,T67	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T33,T118,T188	Yes	T33,T118,T188	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T33,T118,T188	Yes	T33,T118,T188	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T94,T96,T184	Yes	T96,T99,T184	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T33,T188,T45	Yes	T33,T118,T188	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T33,T45,T197	Yes	T33,T45,T197	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T33,T188,T45	Yes	T33,T118,T188	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T97,*T328,*T67	Yes	T97,T328,T67	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T95,T96,T99	Yes	T94,T95,T96	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T33,*T45,*T197	Yes	T33,T118,T188	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T33,T118,T188	Yes	T33,T118,T188	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T97,*T35,*T98	Yes	T97,T35,T98	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T35,T98,T67	Yes	T35,T98,T67	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T178,T163,T74	Yes	T178,T163,T74	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T178,T163,T74	Yes	T76,T178,T163	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T33,T44,T45	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T35,*T95,*T96	Yes	T35,T95,T96	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T33,*T44,*T45	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T82,T83,T84	Yes	T82,T83,T84	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T82,T83,T84	Yes	T82,T83,T84	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T97,*T35,*T98	Yes	T97,T35,T98	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T35,T98,T67	Yes	T35,T98,T67	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T82,T83,T84	Yes	T82,T83,T84	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T82,T83,T84	Yes	T82,T83,T84	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T82,T83,T84	Yes	T82,T83,T84	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T82,T83,T84	Yes	T82,T83,T84	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T82,T83,T84	Yes	T82,T83,T84	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T96,T99	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T96,*T190,*T247	Yes	T94,T95,T96	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T82,*T83,*T84	Yes	T82,T83,T84	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T82,T83,T84	Yes	T82,T83,T84	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T208,T210,T149	Yes	T208,T210,T149	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T208,T210,T149	Yes	T208,T210,T149	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T97,*T35,*T98	Yes	T97,T35,T98	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T35,T98,T67	Yes	T35,T98,T67	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T76,T208,T210	Yes	T76,T208,T210	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T76,T208,T210	Yes	T76,T208,T210	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T208,T210,T149	Yes	T208,T210,T149	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T208,T210,T149	Yes	T76,T208,T210	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T208,T210,T149	Yes	T76,T208,T210	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T99	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T35,*T95,*T96	Yes	T35,T95,T99	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T95,T96,T99	Yes	T94,T95,T96	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T208,*T210,*T149	Yes	T208,T210,T149	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T76,T208,T210	Yes	T76,T208,T210	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T44,T271,T24	Yes	T44,T271,T24	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T97,*T35,*T98	Yes	T97,T35,T98	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T35,T98,T67	Yes	T35,T98,T67	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T33,T31,T36	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T44,T271,T155	Yes	T44,T271,T155	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T33,T31,T36	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T44,T155,T82	Yes	T44,T155,T82	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T94,T96,T99	Yes	T94,T95,T96	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T98,*T57,*T233	Yes	T98,T57,T233	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T94,T99,T184	Yes	T94,T99,T184	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T271,T82,T339	Yes	T271,T82,T339	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T271,T82,T339	Yes	T271,T82,T339	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T97,*T35,*T98	Yes	T97,T35,T98	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T35,T98,T67	Yes	T35,T98,T67	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T271,T82,T339	Yes	T271,T82,T339	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T271,T82,T339	Yes	T271,T82,T339	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T94,T95,T96	Yes	T94,T95,T99	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T271,T82,T339	Yes	T271,T82,T339	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T271,T82,T339	Yes	T271,T82,T339	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T271,T82,T339	Yes	T271,T82,T339	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T94,*T95,*T96	Yes	T57,T58,T440	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T271,*T82,*T339	Yes	T271,T82,T339	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T271,T82,T339	Yes	T271,T82,T339	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T28,T15,T18	Yes	T28,T15,T18	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T28,T15,T18	Yes	T28,T15,T18	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T97,*T35,*T98	Yes	T97,T35,T98	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T35,T98,T67	Yes	T35,T98,T67	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T28,T15,T18	Yes	T28,T15,T18	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T28,T15,T18	Yes	T28,T15,T18	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T286,T184,T190	Yes	T94,T190,T247	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T28,T15,T18	Yes	T28,T15,T18	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T15,T18,T69	Yes	T15,T18,T69	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T28,T15,T18	Yes	T28,T15,T18	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T94,T95,T99	Yes	T94,T95,T96	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T35,*T71,*T247	Yes	T35,T71,T94	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T94,T96,T99	Yes	T94,T96,T99	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T15,*T18,*T69	Yes	T28,T15,T18	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T28,T15,T18	Yes	T28,T15,T18	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T140,T74,T88	Yes	T140,T74,T88	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T140,T74,T88	Yes	T140,T74,T88	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T97,*T35,*T98	Yes	T97,T35,T98	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T35,T98,T67	Yes	T35,T98,T67	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T140,T76,T74	Yes	T140,T76,T74	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T140,T76,T74	Yes	T140,T76,T74	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T94,T96,T99	Yes	T94,T95,T96	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T140,T74,T334	Yes	T140,T74,T88	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T140,T74,T88	Yes	T140,T76,T74	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T140,T74,T88	Yes	T140,T76,T74	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T94,T96,T99	Yes	T94,T96,T99	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T96,*T190,*T247	Yes	T94,T95,T96	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T140,*T74,*T72	Yes	T140,T74,T88	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T140,T76,T74	Yes	T140,T76,T74	INPUT
tl_ast_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T97,*T35,*T98	Yes	T97,T35,T98	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T35,T98,T67	Yes	T35,T98,T67	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_ast_i.d_error	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T33,T44	Yes	T1,T2,T3	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T6,T33,T44	Yes	T1,T2,T3	INPUT
tl_ast_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	*T95,*T96,*T99	Yes	T94,T95,T96	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T95,*T96,*T99	Yes	T94,T95,T96	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range