Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3574858	1			T95	92		T96	74		T97	161
values[2]	714837	1			T95	43		T96	41		T97	17
values[3]	108438	1			T162	4		T189	2		T456	1
values[4]	57042	1			T457	77		T564	1		T458	1
values[5]	37553	1			T457	86		T550	209		T558	19
values[6]	27791	1			T457	90		T550	117		T558	20
values[7]	22656	1			T457	86		T550	65		T558	20
values[8]	19070	1			T457	94		T550	53		T558	15
values[9]	17003	1			T457	73		T550	66		T558	21
values[10]	15577	1			T457	97		T550	75		T558	25
values[11]	14662	1			T457	64		T550	77		T558	15
values[12]	13603	1			T457	62		T550	54		T558	6
values[13]	12385	1			T457	69		T550	38		T558	5
values[14]	12053	1			T457	104		T550	45		T558	5
values[15]	11700	1			T457	74		T550	38		T558	9
values[16]	11232	1			T457	81		T550	70		T558	7
values[17]	10881	1			T457	78		T550	43		T558	18
values[18]	10568	1			T457	83		T550	39		T558	14
values[19]	10080	1			T457	60		T550	19		T558	8
values[20]	9832	1			T457	61		T550	25		T558	9
values[21]	9405	1			T457	73		T550	29		T558	13
values[22]	9160	1			T457	54		T550	39		T558	6
values[23]	8749	1			T457	67		T550	52		T558	6
values[24]	8601	1			T457	93		T550	45		T558	8
values[25]	8442	1			T457	54		T550	42		T558	10
values[26]	7806	1			T457	54		T550	28		T558	6
values[27]	7248	1			T457	46		T550	27		T558	10
values[28]	6961	1			T457	53		T550	34		T558	14
values[29]	6571	1			T457	58		T550	23		T558	17
values[30]	6069	1			T457	49		T550	21		T558	4
values[31]	5842	1			T457	43		T550	38		T558	6
values[32]	5661	1			T457	43		T550	28		T558	6
values[33]	5081	1			T457	26		T550	19		T558	5
values[34]	4733	1			T457	33		T550	26		T558	3
values[35]	4516	1			T457	28		T550	24		T558	4
values[36]	4326	1			T457	20		T550	32		T558	3
values[37]	4155	1			T457	25		T550	22		T558	4
values[38]	3942	1			T457	31		T550	25		T558	2
values[39]	3816	1			T457	22		T550	22		T558	2
values[40]	3646	1			T457	23		T550	15		T558	2
values[41]	3561	1			T457	14		T550	15		T558	2
values[42]	3503	1			T457	9		T550	22		T558	2
values[43]	3387	1			T457	8		T550	26		T558	2
values[44]	3352	1			T457	14		T550	37		T558	2
values[45]	3248	1			T457	6		T550	22		T558	2
values[46]	3276	1			T457	12		T550	17		T558	2
values[47]	3174	1			T457	6		T550	18		T558	2
values[48]	3143	1			T457	8		T550	28		T558	2
values[49]	3080	1			T457	8		T550	32		T558	2
values[50]	2994	1			T457	4		T550	19		T558	2
values[51]	3017	1			T457	10		T550	16		T558	2
values[52]	2786	1			T457	4		T550	13		T558	2
values[53]	2789	1			T457	11		T550	13		T558	2
values[54]	2820	1			T457	5		T550	16		T558	2
values[55]	2832	1			T457	9		T550	19		T558	2
values[56]	2737	1			T457	10		T550	9		T558	2
values[57]	2738	1			T457	5		T550	10		T558	2
values[58]	2615	1			T457	2		T550	17		T558	2
values[59]	2662	1			T457	5		T550	14		T558	2
values[60]	2586	1			T457	4		T550	18		T558	2
values[61]	2791	1			T457	1		T550	20		T558	2
values[62]	4161	1			T457	5		T550	21		T558	1
values[63]	11337	1			T457	1		T550	86		T686	54
values[64]	228771	1			T550	322		T686	86		T474	242

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4589278	1			T95	125		T96	140		T97	166
values[2]	776201	1			T95	27		T96	31		T97	13
values[3]	85059	1			T162	2		T188	11		T189	17
values[4]	15397	1			T188	2		T456	2		T548	2
values[5]	5944	1			T478	1		T550	1		T685	1
values[6]	3859	1			T478	1		T558	2		T686	2
values[7]	3045	1			T558	1		T686	4		T482	6
values[8]	2546	1			T558	1		T686	5		T482	3
values[9]	2257	1			T558	2		T686	7		T482	5
values[10]	1959	1			T558	2		T686	4		T482	26
values[11]	1647	1			T558	2		T686	10		T482	30
values[12]	1609	1			T558	3		T686	12		T482	19
values[13]	1470	1			T558	2		T686	12		T482	4
values[14]	1494	1			T558	2		T686	8		T482	8
values[15]	1450	1			T558	2		T686	7		T482	12
values[16]	1385	1			T558	2		T686	9		T482	7
values[17]	1206	1			T558	2		T686	5		T482	3
values[18]	1232	1			T558	2		T686	7		T482	3
values[19]	1138	1			T558	2		T686	6		T482	11
values[20]	1069	1			T558	2		T686	10		T482	13
values[21]	923	1			T558	3		T686	5		T482	12
values[22]	921	1			T558	1		T482	4		T477	13
values[23]	901	1			T558	1		T482	4		T477	14
values[24]	762	1			T558	2		T482	9		T477	14
values[25]	695	1			T558	3		T482	5		T477	13
values[26]	679	1			T558	2		T482	3		T477	4
values[27]	642	1			T558	2		T482	7		T477	11
values[28]	654	1			T558	2		T482	2		T477	15
values[29]	650	1			T558	2		T482	4		T477	6
values[30]	631	1			T558	2		T482	5		T477	3
values[31]	614	1			T558	2		T482	9		T477	8
values[32]	571	1			T558	2		T482	3		T477	8
values[33]	550	1			T558	2		T482	13		T477	11
values[34]	552	1			T558	2		T482	17		T477	12
values[35]	517	1			T558	2		T482	20		T477	10
values[36]	558	1			T558	2		T482	14		T477	13
values[37]	527	1			T558	2		T482	5		T477	10
values[38]	487	1			T558	2		T482	3		T477	5
values[39]	485	1			T558	2		T482	2		T477	12
values[40]	456	1			T558	2		T482	3		T477	9
values[41]	486	1			T558	2		T482	1		T477	14
values[42]	469	1			T558	2		T482	2		T477	15
values[43]	482	1			T558	2		T482	2		T477	5
values[44]	431	1			T558	2		T482	2		T477	5
values[45]	461	1			T558	2		T482	2		T477	5
values[46]	481	1			T558	2		T482	3		T477	5
values[47]	447	1			T558	2		T482	4		T477	3
values[48]	440	1			T558	2		T482	9		T477	4
values[49]	425	1			T558	2		T482	2		T477	3
values[50]	446	1			T558	2		T482	5		T477	5
values[51]	445	1			T558	2		T482	2		T477	3
values[52]	405	1			T558	2		T482	1		T477	5
values[53]	393	1			T558	2		T482	1		T477	3
values[54]	382	1			T558	2		T482	1		T477	2
values[55]	383	1			T558	1		T482	1		T477	2
values[56]	389	1			T558	1		T482	1		T477	2
values[57]	371	1			T558	2		T482	2		T477	7
values[58]	377	1			T558	3		T482	3		T477	2
values[59]	381	1			T558	2		T482	1		T477	2
values[60]	340	1			T558	2		T482	2		T477	1
values[61]	409	1			T558	2		T482	1		T477	1
values[62]	691	1			T558	2		T482	7		T477	3
values[63]	2588	1			T558	3		T482	21		T477	24
values[64]	25392	1			T558	131		T482	99		T477	87

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	577380	1			T95	1		T96	1		T97	2
values[2]	2498681	1			T95	79		T96	82		T97	147
values[3]	1154274	1			T95	37		T96	33		T97	8
values[4]	144811	1			T162	2		T188	2		T456	2
values[5]	73679	1			T457	78		T562	2		T564	1
values[6]	47404	1			T457	77		T550	141		T558	79
values[7]	34978	1			T457	61		T550	123		T558	49
values[8]	27635	1			T457	71		T550	88		T558	26
values[9]	23617	1			T457	81		T550	80		T558	25
values[10]	20686	1			T457	63		T550	52		T558	36
values[11]	18653	1			T457	59		T550	49		T558	28
values[12]	17494	1			T457	82		T550	58		T558	20
values[13]	16141	1			T457	96		T550	38		T558	22
values[14]	15002	1			T457	85		T550	43		T558	9
values[15]	14382	1			T457	85		T550	49		T558	15
values[16]	13665	1			T457	65		T550	50		T558	10
values[17]	12825	1			T457	83		T550	37		T558	7
values[18]	12459	1			T457	75		T550	37		T558	5
values[19]	11788	1			T457	72		T550	22		T558	8
values[20]	11220	1			T457	96		T550	28		T558	10
values[21]	10903	1			T457	93		T550	30		T558	7
values[22]	10339	1			T457	71		T550	34		T558	7
values[23]	9983	1			T457	94		T550	41		T558	11
values[24]	9424	1			T457	107		T550	54		T558	13
values[25]	9064	1			T457	85		T550	49		T558	6
values[26]	8829	1			T457	61		T550	41		T558	9
values[27]	8335	1			T457	50		T550	29		T558	6
values[28]	7791	1			T457	46		T550	37		T558	11
values[29]	7349	1			T457	52		T550	23		T558	7
values[30]	6804	1			T457	57		T550	27		T558	1
values[31]	6792	1			T457	49		T550	35		T686	5
values[32]	6240	1			T457	29		T550	26		T686	1
values[33]	5661	1			T457	24		T550	30		T686	1
values[34]	5239	1			T457	23		T550	20		T686	3
values[35]	5065	1			T457	20		T550	19		T686	1
values[36]	4615	1			T457	16		T550	22		T686	2
values[37]	4414	1			T457	16		T550	17		T686	2
values[38]	4136	1			T457	12		T550	18		T686	1
values[39]	4011	1			T457	13		T550	19		T686	2
values[40]	3971	1			T457	12		T550	19		T686	1
values[41]	3865	1			T457	15		T550	14		T686	1
values[42]	3851	1			T457	7		T550	13		T686	1
values[43]	3799	1			T457	13		T550	19		T686	1
values[44]	3658	1			T457	12		T550	20		T686	2
values[45]	3509	1			T457	4		T550	14		T686	1
values[46]	3464	1			T457	7		T550	23		T686	2
values[47]	3524	1			T457	5		T550	20		T686	2
values[48]	3413	1			T457	4		T550	21		T686	3
values[49]	3329	1			T457	5		T550	21		T686	4
values[50]	3282	1			T457	3		T550	26		T686	14
values[51]	3196	1			T457	6		T550	35		T686	14
values[52]	3197	1			T457	8		T550	30		T686	11
values[53]	3147	1			T457	2		T550	24		T686	2
values[54]	3128	1			T457	3		T550	23		T686	2
values[55]	2923	1			T550	15		T686	7		T474	2
values[56]	2943	1			T550	17		T686	1		T474	6
values[57]	2889	1			T550	19		T686	1		T474	10
values[58]	2836	1			T550	14		T686	2		T474	4
values[59]	2841	1			T550	11		T686	1		T474	5
values[60]	2851	1			T550	20		T686	1		T474	5
values[61]	2951	1			T550	21		T686	5		T474	10
values[62]	3894	1			T550	12		T686	6		T474	8
values[63]	9974	1			T550	68		T686	22		T474	16
values[64]	222670	1			T550	262		T686	69		T474	104