Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2030292	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

36996941

1

T1

350

T2

4937

T3

5492

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	27099284	1			T1	175		T2	1826		T3	2058
values[0x0]	10381736	1			T1	175		T2	3111		T3	3434
values[0x1]	1546213	1			T1	3		T2	286		T3	234

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	641768	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

38385465

1

T1

353

T2

5223

T3

5726

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18329867	1			T1	177		T2	2612		T3	2863
valid_sources[0x01]	18328830	1			T1	176		T2	2611		T3	2863
valid_sources[0x02]	37436	1			T231	9		T406	19		T407	128
valid_sources[0x03]	38431	1			T35	2		T406	15		T880	1
valid_sources[0x04]	37654	1			T35	2		T68	1		T406	19
valid_sources[0x05]	38229	1			T68	2		T406	20		T407	256
valid_sources[0x06]	38162	1			T100	1		T406	22		T880	11
valid_sources[0x07]	37949	1			T68	1		T406	19		T880	9
valid_sources[0x08]	38127	1			T35	3		T99	3		T406	9
valid_sources[0x09]	38476	1			T35	1		T68	1		T406	12
valid_sources[0x0a]	37985	1			T35	1		T99	1		T68	1
valid_sources[0x0b]	38347	1			T35	1		T406	6		T407	768
valid_sources[0x0c]	38766	1			T35	4		T100	2		T406	9
valid_sources[0x0d]	38113	1			T68	1		T406	7		T407	384
valid_sources[0x0e]	38404	1			T100	1		T68	1		T406	27
valid_sources[0x0f]	38149	1			T35	1		T406	7		T407	768
valid_sources[0x10]	37409	1			T100	1		T232	39		T406	11
valid_sources[0x11]	37761	1			T68	2		T406	4		T880	12
valid_sources[0x12]	41026	1			T35	1		T100	2		T406	19
valid_sources[0x13]	38036	1			T68	1		T406	10		T407	512
valid_sources[0x14]	40376	1			T406	5		T407	128		T557	11
valid_sources[0x15]	37645	1			T100	1		T406	21		T407	384
valid_sources[0x16]	40740	1			T35	1		T100	1		T68	1
valid_sources[0x17]	36827	1			T35	1		T100	1		T406	21
valid_sources[0x18]	37731	1			T406	15		T407	384		T557	16
valid_sources[0x19]	38319	1			T100	1		T406	29		T407	384
valid_sources[0x1a]	38789	1			T68	1		T406	20		T880	2
valid_sources[0x1b]	38954	1			T68	1		T406	26		T407	256
valid_sources[0x1c]	38269	1			T99	3		T100	1		T68	2
valid_sources[0x1d]	37423	1			T35	1		T231	14		T406	7
valid_sources[0x1e]	38048	1			T100	3		T68	3		T406	23
valid_sources[0x1f]	37756	1			T100	2		T406	33		T880	4
valid_sources[0x20]	38081	1			T68	1		T406	4		T880	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26394409

1

T1

175

T2

1826

T3

2058

values[0x0]

all_enables

biggest_size

10329195

1

T1

175

T2

3111

T3

3434

values[0x1]

all_enables

biggest_size

273337

1

T35

17

T99

24

T100

15

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2859010	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

452306

1

T95

22

T96

16

T97

35

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1120473	1			T95	53		T96	37		T97	50
values[0x0]	1071088	1			T95	44		T96	48		T97	64
values[0x1]	1119755	1			T95	38		T96	30		T97	64

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2213450	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1097866

1

T95

49

T96

29

T97

72

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51721	1			T95	2		T96	5		T162	5
valid_sources[0x01]	51776	1			T97	7		T163	1		T188	24
valid_sources[0x02]	50905	1			T95	5		T96	1		T97	4
valid_sources[0x03]	51667	1			T95	1		T96	5		T101	6
valid_sources[0x04]	52729	1			T96	1		T101	4		T162	4
valid_sources[0x05]	52233	1			T95	5		T96	2		T188	25
valid_sources[0x06]	52021	1			T95	6		T97	4		T101	2
valid_sources[0x07]	51857	1			T95	5		T101	4		T162	2
valid_sources[0x08]	52016	1			T95	8		T96	1		T97	5
valid_sources[0x09]	51696	1			T97	12		T101	1		T162	1
valid_sources[0x0a]	51925	1			T95	6		T96	2		T97	13
valid_sources[0x0b]	50645	1			T96	1		T97	3		T163	1
valid_sources[0x0c]	51471	1			T95	1		T96	2		T97	3
valid_sources[0x0d]	51804	1			T95	2		T96	5		T97	1
valid_sources[0x0e]	52412	1			T95	4		T96	4		T97	9
valid_sources[0x0f]	51519	1			T101	6		T163	3		T188	22
valid_sources[0x10]	51467	1			T95	4		T96	2		T162	5
valid_sources[0x11]	52646	1			T95	1		T96	2		T101	1
valid_sources[0x12]	51393	1			T95	4		T96	2		T101	5
valid_sources[0x13]	51944	1			T95	2		T96	9		T97	13
valid_sources[0x14]	51433	1			T96	2		T97	4		T101	11
valid_sources[0x15]	53017	1			T96	1		T97	4		T163	3
valid_sources[0x16]	51915	1			T95	4		T96	1		T101	8
valid_sources[0x17]	51747	1			T95	2		T96	2		T163	1
valid_sources[0x18]	52064	1			T95	1		T96	3		T162	1
valid_sources[0x19]	51318	1			T95	1		T96	3		T97	3
valid_sources[0x1a]	52224	1			T95	5		T96	1		T101	1
valid_sources[0x1b]	52443	1			T95	1		T163	4		T188	20
valid_sources[0x1c]	51435	1			T95	1		T96	1		T162	1
valid_sources[0x1d]	51803	1			T96	2		T97	6		T101	5
valid_sources[0x1e]	51726	1			T96	2		T101	10		T162	6
valid_sources[0x1f]	51446	1			T95	1		T96	2		T97	3
valid_sources[0x20]	50871	1			T95	5		T96	3		T97	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47458

1

T95

5

T96

1

T97

3

values[0x0]

all_enables

biggest_size

357828

1

T95

16

T96

12

T97

27

values[0x1]

all_enables

biggest_size

47020

1

T95

1

T96

3

T97

5

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3037977	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

494094

1

T95

18

T96

18

T97

21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1208580	1			T95	48		T96	56		T97	84
values[0x0]	1114640	1			T95	56		T96	56		T97	44
values[0x1]	1208851	1			T95	48		T96	59		T97	51

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2331855	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1200216

1

T95

53

T96

58

T97

62

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54782	1			T95	1		T96	3		T97	10
valid_sources[0x01]	55089	1			T95	3		T96	1		T97	2
valid_sources[0x02]	54936	1			T96	4		T97	2		T101	5
valid_sources[0x03]	55990	1			T96	1		T101	2		T162	2
valid_sources[0x04]	54881	1			T96	4		T101	10		T163	5
valid_sources[0x05]	55433	1			T96	3		T101	3		T162	1
valid_sources[0x06]	54758	1			T95	4		T96	2		T97	6
valid_sources[0x07]	55168	1			T96	3		T101	2		T162	2
valid_sources[0x08]	54987	1			T96	3		T97	7		T101	2
valid_sources[0x09]	53973	1			T96	3		T101	4		T188	20
valid_sources[0x0a]	55522	1			T95	1		T96	4		T101	2
valid_sources[0x0b]	55228	1			T96	5		T101	6		T162	4
valid_sources[0x0c]	55064	1			T96	3		T101	4		T162	1
valid_sources[0x0d]	56550	1			T97	6		T162	1		T163	2
valid_sources[0x0e]	55113	1			T95	2		T96	3		T97	6
valid_sources[0x0f]	56372	1			T96	2		T162	3		T188	24
valid_sources[0x10]	54887	1			T96	3		T97	1		T101	1
valid_sources[0x11]	54885	1			T95	16		T96	1		T97	7
valid_sources[0x12]	55732	1			T96	2		T101	3		T162	3
valid_sources[0x13]	54876	1			T96	2		T97	9		T101	3
valid_sources[0x14]	55182	1			T96	2		T101	1		T163	2
valid_sources[0x15]	55377	1			T96	4		T97	6		T101	7
valid_sources[0x16]	55094	1			T95	3		T96	6		T97	6
valid_sources[0x17]	54988	1			T95	31		T96	4		T97	9
valid_sources[0x18]	56241	1			T96	4		T97	4		T101	1
valid_sources[0x19]	55142	1			T96	3		T101	1		T162	3
valid_sources[0x1a]	55485	1			T96	2		T97	10		T101	4
valid_sources[0x1b]	55614	1			T95	9		T96	2		T101	4
valid_sources[0x1c]	54057	1			T95	17		T96	3		T162	2
valid_sources[0x1d]	55098	1			T96	2		T101	2		T162	2
valid_sources[0x1e]	54794	1			T96	2		T101	4		T163	1
valid_sources[0x1f]	55091	1			T96	1		T101	2		T162	1
valid_sources[0x20]	55763	1			T96	3		T97	4		T101	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

51680

1

T95

2

T96

1

T97

3

values[0x0]

all_enables

biggest_size

390637

1

T95

15

T96

14

T97

18

values[0x1]

all_enables

biggest_size

51777

1

T95

1

T96

3

T101

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2879168	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

455896

1

T95

18

T96

21

T97

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1128122	1			T95	42		T96	38		T97	66
values[0x0]	1079729	1			T95	40		T96	32		T97	47
values[0x1]	1127213	1			T95	35		T96	46		T97	44

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2230979	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1104085

1

T95

33

T96

47

T97

50

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51530	1			T96	1		T97	13		T101	3
valid_sources[0x01]	50714	1			T96	2		T101	4		T162	5
valid_sources[0x02]	52146	1			T96	3		T162	3		T188	18
valid_sources[0x03]	52902	1			T95	5		T96	7		T97	13
valid_sources[0x04]	52267	1			T95	2		T96	2		T101	3
valid_sources[0x05]	52286	1			T101	3		T162	3		T163	3
valid_sources[0x06]	52062	1			T101	3		T162	1		T163	3
valid_sources[0x07]	52031	1			T163	1		T188	38		T456	56
valid_sources[0x08]	52332	1			T95	5		T96	4		T97	11
valid_sources[0x09]	51664	1			T96	3		T101	3		T162	2
valid_sources[0x0a]	52391	1			T95	1		T96	2		T101	1
valid_sources[0x0b]	51849	1			T96	1		T101	5		T162	1
valid_sources[0x0c]	52018	1			T96	2		T101	4		T162	4
valid_sources[0x0d]	53266	1			T95	5		T96	1		T101	4
valid_sources[0x0e]	52512	1			T101	3		T188	17		T189	2
valid_sources[0x0f]	51895	1			T96	2		T101	1		T162	1
valid_sources[0x10]	51762	1			T96	3		T101	2		T162	10
valid_sources[0x11]	51319	1			T96	1		T97	2		T101	4
valid_sources[0x12]	52793	1			T96	2		T97	6		T162	5
valid_sources[0x13]	51868	1			T101	3		T162	2		T163	2
valid_sources[0x14]	51908	1			T188	28		T189	1		T456	29
valid_sources[0x15]	52005	1			T101	5		T162	2		T188	23
valid_sources[0x16]	51645	1			T95	8		T96	3		T163	1
valid_sources[0x17]	53296	1			T96	1		T101	1		T162	2
valid_sources[0x18]	51824	1			T95	3		T96	2		T97	27
valid_sources[0x19]	51910	1			T96	2		T101	2		T162	1
valid_sources[0x1a]	51811	1			T96	7		T97	24		T162	3
valid_sources[0x1b]	52498	1			T96	2		T97	12		T188	25
valid_sources[0x1c]	51255	1			T95	1		T96	1		T101	2
valid_sources[0x1d]	51939	1			T96	3		T97	7		T101	1
valid_sources[0x1e]	51786	1			T96	2		T101	5		T162	3
valid_sources[0x1f]	51238	1			T96	3		T101	5		T162	2
valid_sources[0x20]	52512	1			T95	10		T96	3		T97	23

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47540

1

T95

4

T96

4

T97

2

values[0x0]

all_enables

biggest_size

360649

1

T95

13

T96

14

T97

13

values[0x1]

all_enables

biggest_size

47707

1

T95

1

T96

3

T97

3