Unified Coverage Report :: Module :: pwm

Module : pwm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_ip_pwm_0.1/rtl/pwm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pwm_aon	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_pwm_aon

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : pwm

	Total	Covered	Percent
Totals	32	32	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	32	32	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T30,T36,T42	Yes	T1,T2,T3	INPUT
clk_core_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_core_ni	Yes	Yes	T30,T36,T42	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T33,T69,T137	Yes	T33,T69,T137	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T33,T69,T137	Yes	T33,T69,T137	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T95,*T96,*T97	Yes	T95,T96,T97	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[21:19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[22]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T88,*T98,*T35	Yes	T88,T98,T35	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T35,T99,T100	Yes	T35,T99,T100	INPUT
tl_i.a_valid	Yes	Yes	T33,T75,T69	Yes	T33,T75,T69	INPUT
tl_o.a_ready	Yes	Yes	T33,T75,T69	Yes	T33,T75,T69	OUTPUT
tl_o.d_error	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T33,T69,T137	Yes	T33,T69,T137	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T33,T69,T137	Yes	T33,T75,T69	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T33,T69,T137	Yes	T33,T75,T69	OUTPUT
tl_o.d_sink	Yes	Yes	T95,T96,T101	Yes	T96,T97,T101	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T68,*T96,*T101	Yes	T68,T95,T96	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T33,*T69,*T137	Yes	T33,T69,T137	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T33,T75,T69	Yes	T33,T75,T69	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T75,T102,T103	Yes	T75,T102,T103	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T75,T102,T103	Yes	T75,T102,T103	OUTPUT
cio_pwm_o[5:0]	Yes	Yes	T33,T69,T137	Yes	T33,T69,T137	OUTPUT
cio_pwm_en_o[5:0]	Unreachable	Unreachable		Unreachable		OUTPUT

*Tests covering at least one bit in the range