Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	516490638	61815954	0	0
DepthKnown_A	516490638	516382196	0	0
RvalidKnown_A	516490638	516382196	0	0
WreadyKnown_A	516490638	516382196	0	0
gen_passthru_fifo.paramCheckPass	1025	1025	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516490638	61815954	0	0
T1	42248	3485	0	0
T2	84649	10413	0	0
T3	76631	9077	0	0
T4	104153	14117	0	0
T5	127764	12723	0	0
T6	79367	8756	0	0
T26	87872	11458	0	0
T34	36418	0	0	0
T105	61525	5768	0	0
T106	94103	11684	0	0
T121	0	56689	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516490638	516382196	0	0
T1	42248	42193	0	0
T2	84649	84598	0	0
T3	76631	76569	0	0
T4	104153	104098	0	0
T5	127764	127706	0	0
T6	79367	79305	0	0
T26	87872	87817	0	0
T34	36418	36356	0	0
T105	61525	61470	0	0
T106	94103	94052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516490638	516382196	0	0
T1	42248	42193	0	0
T2	84649	84598	0	0
T3	76631	76569	0	0
T4	104153	104098	0	0
T5	127764	127706	0	0
T6	79367	79305	0	0
T26	87872	87817	0	0
T34	36418	36356	0	0
T105	61525	61470	0	0
T106	94103	94052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516490638	516382196	0	0
T1	42248	42193	0	0
T2	84649	84598	0	0
T3	76631	76569	0	0
T4	104153	104098	0	0
T5	127764	127706	0	0
T6	79367	79305	0	0
T26	87872	87817	0	0
T34	36418	36356	0	0
T105	61525	61470	0	0
T106	94103	94052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T26	1	1	0	0
T34	1	1	0	0
T105	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         0/1     ==>      assign wready_o = rready_i;
49         0/1     ==>      assign full_o = rready_i;
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	516490638	46943805	0	0
DepthKnown_A	516490638	516382196	0	0
RvalidKnown_A	516490638	516382196	0	0
WreadyKnown_A	516490638	516382196	0	0
gen_passthru_fifo.paramCheckPass	1025	1025	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516490638	46943805	0	0
T1	42248	1880	0	0
T2	84649	7670	0	0
T3	76631	6549	0	0
T4	104153	10492	0	0
T5	127764	8925	0	0
T6	79367	6256	0	0
T26	87872	7712	0	0
T34	36418	0	0	0
T105	61525	4102	0	0
T106	94103	8831	0	0
T121	0	27945	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516490638	516382196	0	0
T1	42248	42193	0	0
T2	84649	84598	0	0
T3	76631	76569	0	0
T4	104153	104098	0	0
T5	127764	127706	0	0
T6	79367	79305	0	0
T26	87872	87817	0	0
T34	36418	36356	0	0
T105	61525	61470	0	0
T106	94103	94052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516490638	516382196	0	0
T1	42248	42193	0	0
T2	84649	84598	0	0
T3	76631	76569	0	0
T4	104153	104098	0	0
T5	127764	127706	0	0
T6	79367	79305	0	0
T26	87872	87817	0	0
T34	36418	36356	0	0
T105	61525	61470	0	0
T106	94103	94052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516490638	516382196	0	0
T1	42248	42193	0	0
T2	84649	84598	0	0
T3	76631	76569	0	0
T4	104153	104098	0	0
T5	127764	127706	0	0
T6	79367	79305	0	0
T26	87872	87817	0	0
T34	36418	36356	0	0
T105	61525	61470	0	0
T106	94103	94052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T26	1	1	0	0
T34	1	1	0	0
T105	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	516490638	43793327	0	0
DepthKnown_A	516490638	516382196	0	0
RvalidKnown_A	516490638	516382196	0	0
WreadyKnown_A	516490638	516382196	0	0
gen_passthru_fifo.paramCheckPass	1025	1025	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516490638	43793327	0	0
T1	42248	461	0	0
T2	84649	5393	0	0
T3	76631	5901	0	0
T4	104153	7047	0	0
T5	127764	8509	0	0
T6	79367	3661	0	0
T26	87872	5428	0	0
T34	36418	0	0	0
T105	61525	3348	0	0
T106	94103	8051	0	0
T121	0	6628	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516490638	516382196	0	0
T1	42248	42193	0	0
T2	84649	84598	0	0
T3	76631	76569	0	0
T4	104153	104098	0	0
T5	127764	127706	0	0
T6	79367	79305	0	0
T26	87872	87817	0	0
T34	36418	36356	0	0
T105	61525	61470	0	0
T106	94103	94052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516490638	516382196	0	0
T1	42248	42193	0	0
T2	84649	84598	0	0
T3	76631	76569	0	0
T4	104153	104098	0	0
T5	127764	127706	0	0
T6	79367	79305	0	0
T26	87872	87817	0	0
T34	36418	36356	0	0
T105	61525	61470	0	0
T106	94103	94052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516490638	516382196	0	0
T1	42248	42193	0	0
T2	84649	84598	0	0
T3	76631	76569	0	0
T4	104153	104098	0	0
T5	127764	127706	0	0
T6	79367	79305	0	0
T26	87872	87817	0	0
T34	36418	36356	0	0
T105	61525	61470	0	0
T106	94103	94052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T26	1	1	0	0
T34	1	1	0	0
T105	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T35 T99 T100 
49         1/1              assign full_o = rready_i;
           Tests:       T35 T99 T100 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	516490638	36691625	0	0
DepthKnown_A	516490638	516382196	0	0
RvalidKnown_A	516490638	516382196	0	0
WreadyKnown_A	516490638	516382196	0	0
gen_passthru_fifo.paramCheckPass	1025	1025	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516490638	36691625	0	0
T1	42248	353	0	0
T2	84649	5223	0	0
T3	76631	5726	0	0
T4	104153	6874	0	0
T5	127764	8331	0	0
T6	79367	3525	0	0
T26	87872	5189	0	0
T34	36418	0	0	0
T105	61525	3235	0	0
T106	94103	7463	0	0
T121	0	5967	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516490638	516382196	0	0
T1	42248	42193	0	0
T2	84649	84598	0	0
T3	76631	76569	0	0
T4	104153	104098	0	0
T5	127764	127706	0	0
T6	79367	79305	0	0
T26	87872	87817	0	0
T34	36418	36356	0	0
T105	61525	61470	0	0
T106	94103	94052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516490638	516382196	0	0
T1	42248	42193	0	0
T2	84649	84598	0	0
T3	76631	76569	0	0
T4	104153	104098	0	0
T5	127764	127706	0	0
T6	79367	79305	0	0
T26	87872	87817	0	0
T34	36418	36356	0	0
T105	61525	61470	0	0
T106	94103	94052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516490638	516382196	0	0
T1	42248	42193	0	0
T2	84649	84598	0	0
T3	76631	76569	0	0
T4	104153	104098	0	0
T5	127764	127706	0	0
T6	79367	79305	0	0
T26	87872	87817	0	0
T34	36418	36356	0	0
T105	61525	61470	0	0
T106	94103	94052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T26	1	1	0	0
T34	1	1	0	0
T105	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	601065426	100449	0	0
DepthKnown_A	601065426	600940780	0	0
RvalidKnown_A	601065426	600940780	0	0
WreadyKnown_A	601065426	600940780	0	0
gen_passthru_fifo.paramCheckPass	2935	2935	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601065426	100449	0	0
T1	42248	8	0	0
T2	84649	23	0	0
T3	76631	24	0	0
T4	104153	24	0	0
T5	127764	15	0	0
T6	79367	13	0	0
T26	87872	29	0	0
T34	36418	0	0	0
T105	61525	13	0	0
T106	94103	34	0	0
T121	0	34	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601065426	600940780	0	0
T1	42248	42193	0	0
T2	84649	84598	0	0
T3	76631	76569	0	0
T4	104153	104098	0	0
T5	127764	127706	0	0
T6	79367	79305	0	0
T26	87872	87817	0	0
T34	36418	36356	0	0
T105	61525	61470	0	0
T106	94103	94052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601065426	600940780	0	0
T1	42248	42193	0	0
T2	84649	84598	0	0
T3	76631	76569	0	0
T4	104153	104098	0	0
T5	127764	127706	0	0
T6	79367	79305	0	0
T26	87872	87817	0	0
T34	36418	36356	0	0
T105	61525	61470	0	0
T106	94103	94052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601065426	600940780	0	0
T1	42248	42193	0	0
T2	84649	84598	0	0
T3	76631	76569	0	0
T4	104153	104098	0	0
T5	127764	127706	0	0
T6	79367	79305	0	0
T26	87872	87817	0	0
T34	36418	36356	0	0
T105	61525	61470	0	0
T106	94103	94052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2935	2935	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T26	1	1	0	0
T34	1	1	0	0
T105	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	601065426	103659	0	0
DepthKnown_A	601065426	600940780	0	0
RvalidKnown_A	601065426	600940780	0	0
WreadyKnown_A	601065426	600940780	0	0
gen_passthru_fifo.paramCheckPass	2935	2935	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601065426	103659	0	0
T1	42248	8	0	0
T2	84649	23	0	0
T3	76631	24	0	0
T4	104153	24	0	0
T5	127764	15	0	0
T6	79367	13	0	0
T26	87872	29	0	0
T34	36418	0	0	0
T105	61525	13	0	0
T106	94103	34	0	0
T121	0	34	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601065426	600940780	0	0
T1	42248	42193	0	0
T2	84649	84598	0	0
T3	76631	76569	0	0
T4	104153	104098	0	0
T5	127764	127706	0	0
T6	79367	79305	0	0
T26	87872	87817	0	0
T34	36418	36356	0	0
T105	61525	61470	0	0
T106	94103	94052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601065426	600940780	0	0
T1	42248	42193	0	0
T2	84649	84598	0	0
T3	76631	76569	0	0
T4	104153	104098	0	0
T5	127764	127706	0	0
T6	79367	79305	0	0
T26	87872	87817	0	0
T34	36418	36356	0	0
T105	61525	61470	0	0
T106	94103	94052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601065426	600940780	0	0
T1	42248	42193	0	0
T2	84649	84598	0	0
T3	76631	76569	0	0
T4	104153	104098	0	0
T5	127764	127706	0	0
T6	79367	79305	0	0
T26	87872	87817	0	0
T34	36418	36356	0	0
T105	61525	61470	0	0
T106	94103	94052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2935	2935	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T26	1	1	0	0
T34	1	1	0	0
T105	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	601065426	53709	0	0
DepthKnown_A	601065426	600940780	0	0
RvalidKnown_A	601065426	600940780	0	0
WreadyKnown_A	601065426	600940780	0	0
gen_passthru_fifo.paramCheckPass	2935	2935	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601065426	53709	0	0
T1	42248	8	0	0
T2	84649	20	0	0
T3	76631	23	0	0
T4	104153	21	0	0
T5	127764	12	0	0
T6	79367	12	0	0
T26	87872	26	0	0
T34	36418	0	0	0
T105	61525	12	0	0
T106	94103	33	0	0
T121	0	31	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601065426	600940780	0	0
T1	42248	42193	0	0
T2	84649	84598	0	0
T3	76631	76569	0	0
T4	104153	104098	0	0
T5	127764	127706	0	0
T6	79367	79305	0	0
T26	87872	87817	0	0
T34	36418	36356	0	0
T105	61525	61470	0	0
T106	94103	94052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601065426	600940780	0	0
T1	42248	42193	0	0
T2	84649	84598	0	0
T3	76631	76569	0	0
T4	104153	104098	0	0
T5	127764	127706	0	0
T6	79367	79305	0	0
T26	87872	87817	0	0
T34	36418	36356	0	0
T105	61525	61470	0	0
T106	94103	94052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601065426	600940780	0	0
T1	42248	42193	0	0
T2	84649	84598	0	0
T3	76631	76569	0	0
T4	104153	104098	0	0
T5	127764	127706	0	0
T6	79367	79305	0	0
T26	87872	87817	0	0
T34	36418	36356	0	0
T105	61525	61470	0	0
T106	94103	94052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2935	2935	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T26	1	1	0	0
T34	1	1	0	0
T105	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	601065426	53709	0	0
DepthKnown_A	601065426	600940780	0	0
RvalidKnown_A	601065426	600940780	0	0
WreadyKnown_A	601065426	600940780	0	0
gen_passthru_fifo.paramCheckPass	2935	2935	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601065426	53709	0	0
T1	42248	8	0	0
T2	84649	20	0	0
T3	76631	23	0	0
T4	104153	21	0	0
T5	127764	12	0	0
T6	79367	12	0	0
T26	87872	26	0	0
T34	36418	0	0	0
T105	61525	12	0	0
T106	94103	33	0	0
T121	0	31	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601065426	600940780	0	0
T1	42248	42193	0	0
T2	84649	84598	0	0
T3	76631	76569	0	0
T4	104153	104098	0	0
T5	127764	127706	0	0
T6	79367	79305	0	0
T26	87872	87817	0	0
T34	36418	36356	0	0
T105	61525	61470	0	0
T106	94103	94052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601065426	600940780	0	0
T1	42248	42193	0	0
T2	84649	84598	0	0
T3	76631	76569	0	0
T4	104153	104098	0	0
T5	127764	127706	0	0
T6	79367	79305	0	0
T26	87872	87817	0	0
T34	36418	36356	0	0
T105	61525	61470	0	0
T106	94103	94052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601065426	600940780	0	0
T1	42248	42193	0	0
T2	84649	84598	0	0
T3	76631	76569	0	0
T4	104153	104098	0	0
T5	127764	127706	0	0
T6	79367	79305	0	0
T26	87872	87817	0	0
T34	36418	36356	0	0
T105	61525	61470	0	0
T106	94103	94052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2935	2935	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T26	1	1	0	0
T34	1	1	0	0
T105	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T2 T3 T4 
49         1/1              assign full_o = rready_i;
           Tests:       T2 T3 T4 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	601065426	46740	0	0
DepthKnown_A	601065426	600940780	0	0
RvalidKnown_A	601065426	600940780	0	0
WreadyKnown_A	601065426	600940780	0	0
gen_passthru_fifo.paramCheckPass	2935	2935	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601065426	46740	0	0
T2	84649	3	0	0
T3	76631	1	0	0
T4	104153	3	0	0
T5	127764	3	0	0
T6	79367	1	0	0
T7	0	3	0	0
T26	87872	3	0	0
T34	36418	0	0	0
T105	61525	1	0	0
T106	94103	1	0	0
T121	96268	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601065426	600940780	0	0
T1	42248	42193	0	0
T2	84649	84598	0	0
T3	76631	76569	0	0
T4	104153	104098	0	0
T5	127764	127706	0	0
T6	79367	79305	0	0
T26	87872	87817	0	0
T34	36418	36356	0	0
T105	61525	61470	0	0
T106	94103	94052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601065426	600940780	0	0
T1	42248	42193	0	0
T2	84649	84598	0	0
T3	76631	76569	0	0
T4	104153	104098	0	0
T5	127764	127706	0	0
T6	79367	79305	0	0
T26	87872	87817	0	0
T34	36418	36356	0	0
T105	61525	61470	0	0
T106	94103	94052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601065426	600940780	0	0
T1	42248	42193	0	0
T2	84649	84598	0	0
T3	76631	76569	0	0
T4	104153	104098	0	0
T5	127764	127706	0	0
T6	79367	79305	0	0
T26	87872	87817	0	0
T34	36418	36356	0	0
T105	61525	61470	0	0
T106	94103	94052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2935	2935	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T26	1	1	0	0
T34	1	1	0	0
T105	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T2 T3 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T2 T3 T4 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	601065426	49950	0	0
DepthKnown_A	601065426	600940780	0	0
RvalidKnown_A	601065426	600940780	0	0
WreadyKnown_A	601065426	600940780	0	0
gen_passthru_fifo.paramCheckPass	2935	2935	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601065426	49950	0	0
T2	84649	3	0	0
T3	76631	1	0	0
T4	104153	3	0	0
T5	127764	3	0	0
T6	79367	1	0	0
T7	0	3	0	0
T26	87872	3	0	0
T34	36418	0	0	0
T105	61525	1	0	0
T106	94103	1	0	0
T121	96268	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601065426	600940780	0	0
T1	42248	42193	0	0
T2	84649	84598	0	0
T3	76631	76569	0	0
T4	104153	104098	0	0
T5	127764	127706	0	0
T6	79367	79305	0	0
T26	87872	87817	0	0
T34	36418	36356	0	0
T105	61525	61470	0	0
T106	94103	94052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601065426	600940780	0	0
T1	42248	42193	0	0
T2	84649	84598	0	0
T3	76631	76569	0	0
T4	104153	104098	0	0
T5	127764	127706	0	0
T6	79367	79305	0	0
T26	87872	87817	0	0
T34	36418	36356	0	0
T105	61525	61470	0	0
T106	94103	94052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601065426	600940780	0	0
T1	42248	42193	0	0
T2	84649	84598	0	0
T3	76631	76569	0	0
T4	104153	104098	0	0
T5	127764	127706	0	0
T6	79367	79305	0	0
T26	87872	87817	0	0
T34	36418	36356	0	0
T105	61525	61470	0	0
T106	94103	94052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2935	2935	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T26	1	1	0	0
T34	1	1	0	0
T105	1	1	0	0
T106	1	1	0	0