Unified Coverage Report :: Module :: pattgen

Module : pattgen

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_ip_pattgen_0.1/rtl/pattgen.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pattgen	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_pattgen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : pattgen

	Total	Covered	Percent
Totals	35	35	100.00
Total Bits	300	300	100.00
Total Bits 0->1	150	150	100.00
Total Bits 1->0	150	150	100.00

Ports	35	35	100.00
Port Bits	300	300	100.00
Port Bits 0->1	150	150	100.00
Port Bits 1->0	150	150	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T30,T36,T42	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T2,T127,T11	Yes	T2,T127,T11	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T2,T127,T11	Yes	T2,T127,T11	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T95,*T96,*T97	Yes	T95,T96,T97	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19:17]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T88,*T98,*T35	Yes	T88,T98,T35	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T35,T99,T100	Yes	T35,T99,T100	INPUT
tl_i.a_valid	Yes	Yes	T2,T75,T127	Yes	T2,T75,T127	INPUT
tl_o.a_ready	Yes	Yes	T2,T75,T127	Yes	T2,T75,T127	OUTPUT
tl_o.d_error	Yes	Yes	T95,T96,T101	Yes	T95,T101,T163	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T2,T127,T11	Yes	T2,T127,T11	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T2,T127,T11	Yes	T2,T75,T127	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T2,T127,T11	Yes	T2,T75,T127	OUTPUT
tl_o.d_sink	Yes	Yes	T95,T96,T101	Yes	T95,T96,T101	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T163,*T188,*T189	Yes	T95,T96,T162	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T95,T96,T101	Yes	T95,T96,T101	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T2,*T127,*T11	Yes	T2,T127,T11	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T2,T75,T127	Yes	T2,T75,T127	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T75,T102,T103	Yes	T75,T102,T103	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T75,T102,T103	Yes	T75,T102,T103	OUTPUT
cio_pda0_tx_o	Yes	Yes	T2,T11,T136	Yes	T2,T11,T136	OUTPUT
cio_pcl0_tx_o	Yes	Yes	T2,T11,T136	Yes	T2,T11,T136	OUTPUT
cio_pda1_tx_o	Yes	Yes	T11,T136,T129	Yes	T11,T136,T129	OUTPUT
cio_pcl1_tx_o	Yes	Yes	T11,T136,T129	Yes	T11,T136,T129	OUTPUT
cio_pda0_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_pcl0_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_pda1_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_pcl1_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_done_ch0_o	Yes	Yes	T2,T127,T136	Yes	T2,T127,T136	OUTPUT
intr_done_ch1_o	Yes	Yes	T127,T136,T190	Yes	T127,T136,T190	OUTPUT

*Tests covering at least one bit in the range