Line Coverage for Module :
rv_core_ibex
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 85 | 82 | 96.47 |
| CONT_ASSIGN | 202 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 203 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 216 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 217 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 218 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 225 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 263 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 265 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 268 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 342 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 348 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 363 | 1 | 1 | 100.00 |
| ALWAYS | 492 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 512 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 513 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 514 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 515 | 1 | 1 | 100.00 |
| ALWAYS | 518 | 8 | 8 | 100.00 |
| CONT_ASSIGN | 702 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 702 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 703 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 703 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 704 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 704 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 708 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 708 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 709 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 709 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 710 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 710 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 717 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 718 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 719 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 722 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 724 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 726 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 728 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 735 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 737 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 739 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 741 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 751 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 752 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 753 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 754 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 757 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 760 | 1 | 1 | 100.00 |
| ALWAYS | 792 | 11 | 11 | 100.00 |
| ALWAYS | 808 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 819 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 838 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 839 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 840 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 843 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 847 | 0 | 0 | |
| CONT_ASSIGN | 886 | 1 | 1 | 100.00 |
| ALWAYS | 945 | 0 | 0 | |
| CONT_ASSIGN | 986 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 988 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 990 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 992 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 994 | 1 | 1 | 100.00 |
201 logic addr_trans_rst_ni;
202 1/1 assign ibex_top_clk_i = clk_i;
Tests: T1 T2 T3
203 1/1 assign addr_trans_rst_ni = rst_ni;
Tests: T1 T2 T3
204
205 // errors and core alert events
206 logic ibus_intg_err, dbus_intg_err;
207 logic alert_minor, alert_major_internal, alert_major_bus;
208 logic double_fault;
209 logic fatal_intg_err, fatal_core_err, recov_core_err;
210
211 // alert events to peripheral module
212 logic fatal_intg_event;
213 logic fatal_core_event;
214 logic recov_core_event;
215 // SEC_CM: BUS.INTEGRITY
216 1/1 assign fatal_intg_event = ibus_intg_err | dbus_intg_err | alert_major_bus;
Tests: T1 T2 T3
217 1/1 assign fatal_core_event = alert_major_internal | double_fault;
Tests: T1 T2 T3
218 1/1 assign recov_core_event = alert_minor;
Tests: T2 T3 T4
219
220 // configurations for address translation
221 region_cfg_t [NumRegions-1:0] ibus_region_cfg;
222 region_cfg_t [NumRegions-1:0] dbus_region_cfg;
223
224 // Reset feedback to clkmgr
225 1/1 assign rst_cpu_n_o = rst_ni;
Tests: T1 T2 T3
226
227 // Escalation receiver that converts differential
228 // protocol into single ended signal.
229 logic esc_irq_nm;
230 prim_esc_receiver #(
231 .N_ESC_SEV (alert_handler_reg_pkg::N_ESC_SEV),
232 .PING_CNT_DW (alert_handler_reg_pkg::PING_CNT_DW)
233 ) u_prim_esc_receiver (
234 .clk_i ( clk_esc_i ),
235 .rst_ni ( rst_esc_ni ),
236 .esc_req_o ( esc_irq_nm ),
237 .esc_rx_o,
238 .esc_tx_i
239 );
240
241 // Synchronize to fast Ibex clock domain.
242 logic alert_irq_nm;
243 prim_flop_2sync #(
244 .Width(1)
245 ) u_alert_nmi_sync (
246 .clk_i,
247 .rst_ni,
248 .d_i(esc_irq_nm),
249 .q_o(alert_irq_nm)
250 );
251
252 logic wdog_irq_nm;
253 prim_flop_2sync #(
254 .Width(1)
255 ) u_wdog_nmi_sync (
256 .clk_i,
257 .rst_ni,
258 .d_i(nmi_wdog_i),
259 .q_o(wdog_irq_nm)
260 );
261
262 assign hw2reg.nmi_state.alert.d = 1'b1;
263 1/1 assign hw2reg.nmi_state.alert.de = alert_irq_nm;
Tests: T42 T82 T84
264 assign hw2reg.nmi_state.wdog.d = 1'b1;
265 1/1 assign hw2reg.nmi_state.wdog.de = wdog_irq_nm;
Tests: T5 T258 T259
266
267 logic irq_nm;
268 1/1 assign irq_nm = |(reg2hw.nmi_state & reg2hw.nmi_enable);
Tests: T5 T42 T82
269
270 lc_ctrl_pkg::lc_tx_t [0:0] lc_cpu_en;
271 prim_lc_sync u_lc_sync (
272 .clk_i,
273 .rst_ni,
274 .lc_en_i(lc_cpu_en_i),
275 .lc_en_o(lc_cpu_en)
276 );
277
278 lc_ctrl_pkg::lc_tx_t [0:0] pwrmgr_cpu_en;
279 prim_lc_sync u_pwrmgr_sync (
280 .clk_i,
281 .rst_ni,
282 .lc_en_i(pwrmgr_cpu_en_i),
283 .lc_en_o(pwrmgr_cpu_en)
284 );
285
286 // timer interrupts do not come from
287 // rv_plic and may not be synchronous to the ibex core
288 logic irq_timer_sync;
289 prim_flop_2sync #(
290 .Width(1)
291 ) u_intr_timer_sync (
292 .clk_i,
293 .rst_ni,
294 .d_i(irq_timer_i),
295 .q_o(irq_timer_sync)
296 );
297
298
299 logic irq_software;
300 logic irq_timer;
301 logic irq_external;
302
303 prim_sec_anchor_buf #(
304 .Width(3)
305 ) u_prim_buf_irq (
306 .in_i({irq_software_i,
307 irq_timer_sync,
308 irq_external_i}),
309 .out_o({irq_software,
310 irq_timer,
311 irq_external})
312 );
313
314
315 logic key_req, key_ack;
316 logic [ibex_pkg::SCRAMBLE_KEY_W-1:0] key;
317 logic [ibex_pkg::SCRAMBLE_NONCE_W-1:0] nonce;
318 logic unused_seed_valid;
319 localparam int PayLoadW = ibex_pkg::SCRAMBLE_KEY_W + ibex_pkg::SCRAMBLE_NONCE_W + 1;
320 prim_sync_reqack_data #(
321 .Width(PayLoadW),
322 .DataSrc2Dst(1'b0)
323 ) u_prim_sync_reqack_data (
324 .clk_src_i ( clk_i ),
325 .rst_src_ni ( rst_ni ),
326 .clk_dst_i ( clk_otp_i ),
327 .rst_dst_ni ( rst_otp_ni ),
328 .req_chk_i ( 1'b1 ),
329 .src_req_i ( key_req ),
330 .src_ack_o ( key_ack ),
331 .dst_req_o ( icache_otp_key_o.req ),
332 .dst_ack_i ( icache_otp_key_i.ack ),
333 .data_i ( {icache_otp_key_i.key,
334 icache_otp_key_i.nonce[ibex_pkg::SCRAMBLE_NONCE_W-1:0],
335 icache_otp_key_i.seed_valid} ),
336 .data_o ( {key,
337 nonce,
338 unused_seed_valid} )
339 );
340
341 logic unused_nonce;
342 1/1 assign unused_nonce = |icache_otp_key_i.nonce;
Tests: T2 T3 T4
343
344 // Local fetch enable control.
345 // Whenever a fatal core error is seen disable local fetch enable.
346 lc_ctrl_pkg::lc_tx_t local_fetch_enable_d, local_fetch_enable_q;
347
348 1/1 assign local_fetch_enable_d = fatal_core_err ? lc_ctrl_pkg::Off : local_fetch_enable_q;
Tests: T1 T2 T3
349
350 prim_lc_sender #(
351 .AsyncOn(1), // this instantiates a register
352 .ResetValueIsOn(1)
353 ) u_prim_lc_sender (
354 .clk_i,
355 .rst_ni,
356 .lc_en_i(local_fetch_enable_d),
357 .lc_en_o(local_fetch_enable_q)
358 );
359
360 // Multibit AND computation for fetch enable. Fetch is only enabled when local fetch enable,
361 // lifecycle CPU enable and power manager CPU enable are all enabled.
362 lc_ctrl_pkg::lc_tx_t fetch_enable;
363 1/1 assign fetch_enable = lc_ctrl_pkg::lc_tx_and_hi(local_fetch_enable_q,
Tests: T1 T2 T3
364 lc_ctrl_pkg::lc_tx_and_hi(lc_cpu_en[0],
365 pwrmgr_cpu_en[0]));
366
367 ibex_pkg::crash_dump_t crash_dump;
368 ibex_top #(
369 .PMPEnable ( PMPEnable ),
370 .PMPGranularity ( PMPGranularity ),
371 .PMPNumRegions ( PMPNumRegions ),
372 .MHPMCounterNum ( MHPMCounterNum ),
373 .MHPMCounterWidth ( MHPMCounterWidth ),
374 .RV32E ( RV32E ),
375 .RV32M ( RV32M ),
376 .RV32B ( RV32B ),
377 .RegFile ( RegFile ),
378 .BranchTargetALU ( BranchTargetALU ),
379 .WritebackStage ( WritebackStage ),
380 .ICache ( ICache ),
381 // Our automatic SEC_CM label check doesn't look at vendored code so the SEC_CM labels need
382 // to be mentioned here. The real locations can be found by grepping the vendored code.
383 // TODO(#10071): this should be fixed.
384 // SEC_CM: ICACHE.MEM.INTEGRITY
385 .ICacheECC ( ICacheECC ),
386 // SEC_CM: ICACHE.MEM.SCRAMBLE, SCRAMBLE.KEY.SIDELOAD
387 .ICacheScramble ( ICacheScramble ),
388 // Reduce the number of PRINCE half rounds to 2 (5 effective rounds) to ease timing. This is
389 // acceptable for the instruction cache, whereas 3 half rounds (7 effective rounds) are used
390 // elsewhere in the design.
391 .ICacheScrNumPrinceRoundsHalf( 2 ),
392 .BranchPredictor ( BranchPredictor ),
393 .DbgTriggerEn ( DbgTriggerEn ),
394 .DbgHwBreakNum ( DbgHwBreakNum ),
395 // SEC_CM: LOGIC.SHADOW
396 // SEC_CM: PC.CTRL_FLOW.CONSISTENCY, CTRL_FLOW.UNPREDICTABLE, CORE.DATA_REG_SW.SCA
397 // SEC_CM: EXCEPTION.CTRL_FLOW.GLOBAL_ESC, EXCEPTION.CTRL_FLOW.LOCAL_ESC
398 // SEC_CM: DATA_REG_SW.INTEGRITY, DATA_REG_SW.GLITCH_DETECT
399 .SecureIbex ( SecureIbex ),
400 .RndCnstLfsrSeed ( RndCnstLfsrSeed ),
401 .RndCnstLfsrPerm ( RndCnstLfsrPerm ),
402 .RndCnstIbexKey ( RndCnstIbexKeyDefault ),
403 .RndCnstIbexNonce ( RndCnstIbexNonceDefault ),
404 .DmHaltAddr ( DmHaltAddr ),
405 .DmExceptionAddr ( DmExceptionAddr )
406 ) u_core (
407 .clk_i (ibex_top_clk_i),
408 .rst_ni,
409
410
411 .test_en_i (prim_mubi_pkg::mubi4_test_true_strict(scanmode_i)),
412 .scan_rst_ni,
413
414 .ram_cfg_i,
415
416 .hart_id_i,
417 .boot_addr_i,
418
419 .instr_req_o ( instr_req ),
420 .instr_gnt_i ( instr_gnt ),
421 .instr_rvalid_i ( instr_rvalid ),
422 .instr_addr_o ( instr_addr ),
423 .instr_rdata_i ( instr_rdata ),
424 .instr_rdata_intg_i ( instr_rdata_intg ),
425 .instr_err_i ( instr_err ),
426
427 .data_req_o ( data_req ),
428 .data_gnt_i ( data_gnt ),
429 .data_rvalid_i ( data_rvalid ),
430 .data_we_o ( data_we ),
431 .data_be_o ( data_be ),
432 .data_addr_o ( data_addr ),
433 .data_wdata_o ( data_wdata ),
434 .data_wdata_intg_o ( data_wdata_intg ),
435 .data_rdata_i ( data_rdata ),
436 .data_rdata_intg_i ( data_rdata_intg ),
437 .data_err_i ( data_err ),
438
439 .irq_software_i ( irq_software ),
440 .irq_timer_i ( irq_timer ),
441 .irq_external_i ( irq_external ),
442 .irq_fast_i ( '0 ),
443 .irq_nm_i ( irq_nm ),
444
445 .debug_req_i,
446 .crash_dump_o ( crash_dump ),
447
448 // icache scramble interface
449 .scramble_key_valid_i (key_ack),
450 .scramble_key_i (key),
451 .scramble_nonce_i (nonce),
452 .scramble_req_o (key_req),
453
454 // double fault
455 .double_fault_seen_o (double_fault),
456
457 `ifdef RVFI
458 .rvfi_valid,
459 .rvfi_order,
460 .rvfi_insn,
461 .rvfi_trap,
462 .rvfi_halt,
463 .rvfi_intr,
464 .rvfi_mode,
465 .rvfi_ixl,
466 .rvfi_rs1_addr,
467 .rvfi_rs2_addr,
468 .rvfi_rs3_addr,
469 .rvfi_rs1_rdata,
470 .rvfi_rs2_rdata,
471 .rvfi_rs3_rdata,
472 .rvfi_rd_addr,
473 .rvfi_rd_wdata,
474 .rvfi_pc_rdata,
475 .rvfi_pc_wdata,
476 .rvfi_mem_addr,
477 .rvfi_mem_rmask,
478 .rvfi_mem_wmask,
479 .rvfi_mem_rdata,
480 .rvfi_mem_wdata,
481 `endif
482 // SEC_CM: FETCH.CTRL.LC_GATED
483 .fetch_enable_i (fetch_enable),
484 .alert_minor_o (alert_minor),
485 .alert_major_internal_o (alert_major_internal),
486 .alert_major_bus_o (alert_major_bus),
487 .core_sleep_o (core_sleep)
488 );
489
490 logic core_sleep_q;
491 always_ff @(posedge clk_i or negedge rst_ni) begin
492 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
493 1/1 core_sleep_q <= '0;
Tests: T1 T2 T3
494 end else begin
495 1/1 core_sleep_q <= core_sleep;
Tests: T1 T2 T3
496 end
497 end
498
499 prim_buf #(
500 .Width(1)
501 ) u_core_sleeping_buf (
502 .in_i(core_sleep_q),
503 .out_o(pwrmgr_o.core_sleeping)
504 );
505
506
507
508 logic prev_valid;
509 logic [31:0] prev_exception_pc;
510 logic [31:0] prev_exception_addr;
511
512 1/1 assign crash_dump_o.current = crash_dump;
Tests: T1 T2 T3
513 1/1 assign crash_dump_o.prev_valid = prev_valid;
Tests: T260 T261 T262
514 1/1 assign crash_dump_o.prev_exception_pc = prev_exception_pc;
Tests: T260 T261 T262
515 1/1 assign crash_dump_o.prev_exception_addr = prev_exception_addr;
Tests: T260 T261 T262
516
517 always_ff @(posedge clk_i or negedge rst_ni) begin
518 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
519 1/1 prev_valid <= '0;
Tests: T1 T2 T3
520 1/1 prev_exception_pc <= '0;
Tests: T1 T2 T3
521 1/1 prev_exception_addr <= '0;
Tests: T1 T2 T3
522 1/1 end else if (double_fault) begin
Tests: T1 T2 T3
523 1/1 prev_valid <= 1'b1;
Tests: T260 T261 T262
524 1/1 prev_exception_pc <= crash_dump.exception_pc;
Tests: T260 T261 T262
525 1/1 prev_exception_addr <= crash_dump.exception_addr;
Tests: T260 T261 T262
526 end
MISSING_ELSE
527 end
528
529
530 //
531 // Convert ibex data/instruction bus to TL-UL
532 //
533 logic [31:0] instr_addr_trans;
534 rv_core_addr_trans #(
535 .AddrWidth(32),
536 .NumRegions(NumRegions)
537 ) u_ibus_trans (
538 .clk_i,
539 .rst_ni(addr_trans_rst_ni),
540 .region_cfg_i(ibus_region_cfg),
541 .addr_i(instr_addr),
542 .addr_o(instr_addr_trans)
543 );
544
545 logic [6:0] instr_wdata_intg;
546 logic [top_pkg::TL_DW-1:0] unused_data;
547 // tl_adapter_host_i_ibex only reads instruction. a_data is always 0
548 assign {instr_wdata_intg, unused_data} = prim_secded_pkg::prim_secded_inv_39_32_enc('0);
549 // SEC_CM: BUS.INTEGRITY
550 tlul_adapter_host #(
551 .MAX_REQS(NumOutstandingReqs),
552 // if secure ibex is not set, data integrity is not generated
553 // from ibex, therefore generate it in the gasket instead.
554 .EnableDataIntgGen(~SecureIbex)
555 ) tl_adapter_host_i_ibex (
556 .clk_i,
557 .rst_ni,
558 .req_i (instr_req),
559 .instr_type_i (prim_mubi_pkg::MuBi4True),
560 .gnt_o (instr_gnt),
561 .addr_i (instr_addr_trans),
562 .we_i (1'b0),
563 .wdata_i (32'b0),
564 .wdata_intg_i (instr_wdata_intg),
565 .be_i (4'hF),
566 .valid_o (instr_rvalid),
567 .rdata_o (instr_rdata),
568 .rdata_intg_o (instr_rdata_intg),
569 .err_o (instr_err),
570 .intg_err_o (ibus_intg_err),
571 .tl_o (tl_i_ibex2fifo),
572 .tl_i (tl_i_fifo2ibex)
573 );
574
575 tlul_fifo_sync #(
576 .ReqPass(FifoPass),
577 .RspPass(FifoPass),
578 .ReqDepth(FifoDepth),
579 .RspDepth(FifoDepth)
580 ) fifo_i (
581 .clk_i,
582 .rst_ni,
583 .tl_h_i (tl_i_ibex2fifo),
584 .tl_h_o (tl_i_fifo2ibex),
585 .tl_d_o (corei_tl_h_o),
586 .tl_d_i (corei_tl_h_i),
587 .spare_req_i (1'b0),
588 .spare_req_o (),
589 .spare_rsp_i (1'b0),
590 .spare_rsp_o ());
591
592 logic [31:0] data_addr_trans;
593 rv_core_addr_trans #(
594 .AddrWidth(32),
595 .NumRegions(NumRegions)
596 ) u_dbus_trans (
597 .clk_i,
598 .rst_ni(addr_trans_rst_ni),
599 .region_cfg_i(dbus_region_cfg),
600 .addr_i(data_addr),
601 .addr_o(data_addr_trans)
602 );
603
604 // SEC_CM: BUS.INTEGRITY
605 tlul_adapter_host #(
606 .MAX_REQS(2),
607 .EnableDataIntgGen(~SecureIbex)
608 ) tl_adapter_host_d_ibex (
609 .clk_i,
610 .rst_ni,
611 .req_i (data_req),
612 .instr_type_i (prim_mubi_pkg::MuBi4False),
613 .gnt_o (data_gnt),
614 .addr_i (data_addr_trans),
615 .we_i (data_we),
616 .wdata_i (data_wdata),
617 .wdata_intg_i (data_wdata_intg),
618 .be_i (data_be),
619 .valid_o (data_rvalid),
620 .rdata_o (data_rdata),
621 .rdata_intg_o (data_rdata_intg),
622 .err_o (data_err),
623 .intg_err_o (dbus_intg_err),
624 .tl_o (tl_d_ibex2fifo),
625 .tl_i (tl_d_fifo2ibex)
626 );
627
628 tlul_fifo_sync #(
629 .ReqPass(FifoPass),
630 .RspPass(FifoPass),
631 .ReqDepth(FifoDepth),
632 .RspDepth(FifoDepth)
633 ) fifo_d (
634 .clk_i,
635 .rst_ni,
636 .tl_h_i (tl_d_ibex2fifo),
637 .tl_h_o (tl_d_fifo2ibex),
638 .tl_d_o (cored_tl_h_o),
639 .tl_d_i (cored_tl_h_i),
640 .spare_req_i (1'b0),
641 .spare_req_o (),
642 .spare_rsp_i (1'b0),
643 .spare_rsp_o ());
644
645 `ifdef RVFI
646 ibex_tracer ibex_tracer_i (
647 .clk_i,
648 .rst_ni,
649
650 .hart_id_i,
651
652 .rvfi_valid,
653 .rvfi_order,
654 .rvfi_insn,
655 .rvfi_trap,
656 .rvfi_halt,
657 .rvfi_intr,
658 .rvfi_mode,
659 .rvfi_ixl,
660 .rvfi_rs1_addr,
661 .rvfi_rs2_addr,
662 .rvfi_rs3_addr,
663 .rvfi_rs1_rdata,
664 .rvfi_rs2_rdata,
665 .rvfi_rs3_rdata,
666 .rvfi_rd_addr,
667 .rvfi_rd_wdata,
668 .rvfi_pc_rdata,
669 .rvfi_pc_wdata,
670 .rvfi_mem_addr,
671 .rvfi_mem_rmask,
672 .rvfi_mem_wmask,
673 .rvfi_mem_rdata,
674 .rvfi_mem_wdata
675 );
676 `endif
677
678 //////////////////////////////////
679 // Peripheral functions
680 //////////////////////////////////
681
682 logic intg_err;
683 tlul_pkg::tl_h2d_t tl_win_h2d;
684 tlul_pkg::tl_d2h_t tl_win_d2h;
685 rv_core_ibex_cfg_reg_top u_reg_cfg (
686 .clk_i,
687 .rst_ni,
688 .tl_i(cfg_tl_d_i),
689 .tl_o(cfg_tl_d_o),
690 .reg2hw,
691 .hw2reg,
692 .intg_err_o (intg_err),
693 .tl_win_o(tl_win_h2d),
694 .tl_win_i(tl_win_d2h)
695 );
696
697 ///////////////////////
698 // Region assignments
699 ///////////////////////
700
701 for(genvar i = 0; i < NumRegions; i++) begin : gen_ibus_region_cfgs
702 2/2 assign ibus_region_cfg[i].en = reg2hw.ibus_addr_en[i];
Tests: T214 T215 T263 | T214 T215 T263
703 2/2 assign ibus_region_cfg[i].matching_region = reg2hw.ibus_addr_matching[i];
Tests: T214 T215 T263 | T214 T215 T263
704 2/2 assign ibus_region_cfg[i].remap_addr = reg2hw.ibus_remap_addr[i];
Tests: T214 T215 T263 | T214 T215 T263
705 end
706
707 for(genvar i = 0; i < NumRegions; i++) begin : gen_dbus_region_cfgs
708 2/2 assign dbus_region_cfg[i].en = reg2hw.dbus_addr_en[i];
Tests: T214 T215 T263 | T214 T215 T263
709 2/2 assign dbus_region_cfg[i].matching_region = reg2hw.dbus_addr_matching[i];
Tests: T214 T215 T263 | T214 T215 T263
710 2/2 assign dbus_region_cfg[i].remap_addr = reg2hw.dbus_remap_addr[i];
Tests: T214 T215 T263 | T214 T215 T263
711 end
712
713 ///////////////////////
714 // Error assignment
715 ///////////////////////
716
717 1/1 assign fatal_intg_err = fatal_intg_event;
Tests: T1 T2 T3
718 1/1 assign fatal_core_err = fatal_core_event;
Tests: T1 T2 T3
719 1/1 assign recov_core_err = recov_core_event;
Tests: T2 T3 T4
720
721 assign hw2reg.err_status.reg_intg_err.d = 1'b1;
722 1/1 assign hw2reg.err_status.reg_intg_err.de = intg_err;
Tests: T1 T2 T3
723 assign hw2reg.err_status.fatal_intg_err.d = 1'b1;
724 1/1 assign hw2reg.err_status.fatal_intg_err.de = fatal_intg_err;
Tests: T1 T2 T3
725 assign hw2reg.err_status.fatal_core_err.d = 1'b1;
726 1/1 assign hw2reg.err_status.fatal_core_err.de = fatal_core_err;
Tests: T1 T2 T3
727 assign hw2reg.err_status.recov_core_err.d = 1'b1;
728 1/1 assign hw2reg.err_status.recov_core_err.de = recov_core_err;
Tests: T2 T3 T4
729
730 ///////////////////////
731 // Alert generation
732 ///////////////////////
733
734 logic [NumAlerts-1:0] alert_test;
735 1/1 assign alert_test[0] = reg2hw.alert_test.fatal_sw_err.q &
Tests: T1 T2 T3
736 reg2hw.alert_test.fatal_sw_err.qe;
737 1/1 assign alert_test[1] = reg2hw.alert_test.recov_sw_err.q &
Tests: T1 T2 T3
738 reg2hw.alert_test.recov_sw_err.qe;
739 1/1 assign alert_test[2] = reg2hw.alert_test.fatal_hw_err.q &
Tests: T1 T2 T3
740 reg2hw.alert_test.fatal_hw_err.qe;
741 1/1 assign alert_test[3] = reg2hw.alert_test.recov_hw_err.q &
Tests: T1 T2 T3
742 reg2hw.alert_test.recov_hw_err.qe;
743
744 localparam bit [NumAlerts-1:0] AlertFatal = '{1'b0, 1'b1, 1'b0, 1'b1};
745
746 logic [NumAlerts-1:0] alert_events;
747 logic [NumAlerts-1:0] alert_acks;
748
749 import prim_mubi_pkg::mubi4_test_true_loose;
750 import prim_mubi_pkg::mubi4_t;
751 1/1 assign alert_events[0] = mubi4_test_true_loose(mubi4_t'(reg2hw.sw_fatal_err.q));
Tests: T264 T265 T266
752 1/1 assign alert_events[1] = mubi4_test_true_loose(mubi4_t'(reg2hw.sw_recov_err.q));
Tests: T68
753 1/1 assign alert_events[2] = intg_err | fatal_intg_err | fatal_core_err;
Tests: T1 T2 T3
754 1/1 assign alert_events[3] = recov_core_err;
Tests: T2 T3 T4
755
756 logic unused_alert_acks;
757 1/1 assign unused_alert_acks = |alert_acks;
Tests: T82 T216 T260
758
759 // recoverable alerts are sent once and silenced until activated again.
760 1/1 assign hw2reg.sw_recov_err.de = alert_acks[1];
Tests: T68
761 assign hw2reg.sw_recov_err.d = prim_mubi_pkg::MuBi4False;
762
763 for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_senders
764 prim_alert_sender #(
765 .AsyncOn(AlertAsyncOn[0]),
766 .IsFatal(AlertFatal[i])
767 ) u_alert_sender (
768 .clk_i,
769 .rst_ni,
770 .alert_test_i(alert_test[i]),
771 .alert_req_i(alert_events[i]),
772 .alert_ack_o(alert_acks[i]),
773 .alert_state_o(),
774 .alert_rx_i(alert_rx_i[i]),
775 .alert_tx_o(alert_tx_o[i])
776 );
777 end
778
779 //////////////
780 // RND Data //
781 //////////////
782
783 logic [31:0] rnd_data_q, rnd_data_d;
784 logic rnd_valid_q, rnd_valid_d;
785 logic rnd_fips_q, rnd_fips_d;
786 logic edn_req;
787 logic [31:0] edn_data;
788 logic edn_ack;
789 logic edn_fips;
790
791 always_comb begin
792 1/1 rnd_valid_d = rnd_valid_q;
Tests: T2 T3 T4
793 1/1 rnd_data_d = rnd_data_q;
Tests: T2 T3 T4
794 1/1 rnd_fips_d = rnd_fips_q;
Tests: T2 T3 T4
795
796 1/1 if (reg2hw.rnd_data.re) begin
Tests: T2 T3 T4
797 1/1 rnd_valid_d = '0;
Tests: T2 T4 T5
798 1/1 rnd_data_d = '0;
Tests: T2 T4 T5
799 1/1 rnd_fips_d = '0;
Tests: T2 T4 T5
800 1/1 end else if (edn_req && edn_ack) begin
Tests: T2 T3 T4
801 1/1 rnd_valid_d = 1'b1;
Tests: T2 T3 T4
802 1/1 rnd_data_d = edn_data;
Tests: T2 T3 T4
803 1/1 rnd_fips_d = edn_fips;
Tests: T2 T3 T4
804 end
MISSING_ELSE
805 end
806
807 always_ff @(posedge clk_i or negedge rst_ni) begin
808 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
809 1/1 rnd_valid_q <= '0;
Tests: T1 T2 T3
810 1/1 rnd_data_q <= '0;
Tests: T1 T2 T3
811 1/1 rnd_fips_q <= '0;
Tests: T1 T2 T3
812 end else begin
813 1/1 rnd_valid_q <= rnd_valid_d;
Tests: T1 T2 T3
814 1/1 rnd_data_q <= rnd_data_d;
Tests: T1 T2 T3
815 1/1 rnd_fips_q <= rnd_fips_d;
Tests: T1 T2 T3
816 end
817 end
818
819 1/1 assign edn_req = ~rnd_valid_q;
Tests: T2 T3 T4
820
821 prim_edn_req #(
822 .OutWidth(32)
823 ) u_edn_if (
824 .clk_i,
825 .rst_ni,
826 .req_chk_i(1'b1),
827 .req_i(edn_req),
828 .ack_o(edn_ack),
829 .data_o(edn_data),
830 .fips_o(edn_fips),
831 .err_o(),
832 .clk_edn_i,
833 .rst_edn_ni,
834 .edn_o,
835 .edn_i
836 );
837
838 1/1 assign hw2reg.rnd_data.d = rnd_data_q;
Tests: T2 T3 T4
839 1/1 assign hw2reg.rnd_status.rnd_data_valid.d = rnd_valid_q;
Tests: T2 T3 T4
840 1/1 assign hw2reg.rnd_status.rnd_data_fips.d = rnd_fips_q;
Tests: T157 T267 T145
841
842 logic unused_reg2hw;
843 0/1 ==> assign unused_reg2hw = |reg2hw.rnd_data.q;
844
845
846 // fpga build info hook-up
847 unreachable assign hw2reg.fpga_info.d = fpga_info_i;
848
849 /////////////////////////////////////
850 // The carved out space is for DV emulation purposes only
851 /////////////////////////////////////
852
853 import tlul_pkg::tl_h2d_t;
854 import tlul_pkg::tl_d2h_t;
855 localparam int TlH2DWidth = $bits(tl_h2d_t);
856 localparam int TlD2HWidth = $bits(tl_d2h_t);
857
858 logic [TlH2DWidth-1:0] tl_win_h2d_int;
859 logic [TlD2HWidth-1:0] tl_win_d2h_int;
860 tl_d2h_t tl_win_d2h_err_rsp;
861
862 prim_buf #(
863 .Width(TlH2DWidth)
864 ) u_tlul_req_buf (
865 .in_i(tl_win_h2d),
866 .out_o(tl_win_h2d_int)
867 );
868
869 prim_buf #(
870 .Width(TlD2HWidth)
871 ) u_tlul_rsp_buf (
872 .in_i(tl_win_d2h_err_rsp),
873 .out_o(tl_win_d2h_int)
874 );
875
876 // Interception point for connecting simulation SRAM by disconnecting the tl_d output. The
877 // disconnection is done only if `SYNTHESIS is NOT defined AND `RV_CORE_IBEX_SIM_SRAM is
878 // defined.
879 // This define is used only for verilator as verilator does not support forces.
880 `ifdef RV_CORE_IBEX_SIM_SRAM
881 `ifdef SYNTHESIS
882 // Induce a compilation error by instantiating a non-existent module.
883 illegal_preprocessor_branch_taken u_illegal_preprocessor_branch_taken();
884 `endif
885 `else
886 1/1 assign tl_win_d2h = tl_d2h_t'(tl_win_d2h_int);
Tests: T1 T2 T3
887 `endif
888
889 tlul_err_resp u_sim_win_rsp (
890 .clk_i,
891 .rst_ni,
892 .tl_h_i(tl_h2d_t'(tl_win_h2d_int)),
893 .tl_h_o(tl_win_d2h_err_rsp)
894 );
895
896 // Assertions for CPU enable
897 // Allow 2 or 3 cycles for input to enable due to synchronizers
898 `ASSERT(FpvSecCmIbexFetchEnable0_A,
899 fatal_core_err
900 |=>
901 lc_ctrl_pkg::lc_tx_test_false_loose(fetch_enable))
902 `ASSERT(FpvSecCmIbexFetchEnable1_A,
903 lc_ctrl_pkg::lc_tx_test_false_loose(lc_cpu_en_i)
904 |->
905 ##[2:3] lc_ctrl_pkg::lc_tx_test_false_loose(fetch_enable))
906 `ASSERT(FpvSecCmIbexFetchEnable2_A,
907 lc_ctrl_pkg::lc_tx_test_false_loose(pwrmgr_cpu_en_i)
908 |->
909 ##[2:3] lc_ctrl_pkg::lc_tx_test_false_loose(fetch_enable))
910 `ASSERT(FpvSecCmIbexFetchEnable3_A,
911 lc_ctrl_pkg::lc_tx_test_true_strict(lc_cpu_en_i) &&
912 lc_ctrl_pkg::lc_tx_test_true_strict(pwrmgr_cpu_en_i) ##1
913 lc_ctrl_pkg::lc_tx_test_true_strict(local_fetch_enable_q) &&
914 !fatal_core_err
915 |=>
916 ##[0:1] lc_ctrl_pkg::lc_tx_test_true_strict(fetch_enable))
917 `ASSERT(FpvSecCmIbexFetchEnable3Rev_A,
918 ##2 lc_ctrl_pkg::lc_tx_test_true_strict(fetch_enable)
919 |->
920 ($past(lc_ctrl_pkg::lc_tx_test_true_strict(lc_cpu_en_i), 2) ||
921 $past(lc_ctrl_pkg::lc_tx_test_true_strict(lc_cpu_en_i), 3)) &&
922 ($past(lc_ctrl_pkg::lc_tx_test_true_strict(pwrmgr_cpu_en_i), 2) ||
923 $past(lc_ctrl_pkg::lc_tx_test_true_strict(pwrmgr_cpu_en_i), 3)) &&
924 $past(!fatal_core_err))
925
926 // Alert assertions for reg_we onehot check
927 `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegWeOnehotCheck_A, u_reg_cfg, alert_tx_o[2])
928 `ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ALERT(RvCoreRegWeOnehotCheck_A,
929 u_core.gen_regfile_ff.register_file_i.gen_wren_check.u_prim_onehot_check, alert_tx_o[2])
930 `ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ALERT(RvCoreRegWeOnehotCheckRAddrA_A,
931 u_core.gen_regfile_ff.register_file_i.gen_rdata_mux_check.u_prim_onehot_check_raddr_a,
932 alert_tx_o[2])
933 `ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ALERT(RvCoreRegWeOnehotCheckRAddrB_A,
934 u_core.gen_regfile_ff.register_file_i.gen_rdata_mux_check.u_prim_onehot_check_raddr_b,
935 alert_tx_o[2])
936
937 `ifdef INC_ASSERT
938 if (ICache && ICacheScramble) begin : gen_icache_scramble_asserts
939
940 // Sample icache scramble key for use in assertions below.
941 // pragma coverage off
942 //VCS coverage off
943 logic [otp_ctrl_pkg::FlashKeyWidth-1:0] icache_otp_key_q;
944 always_ff @(posedge clk_i, negedge rst_ni) begin
945 unreachable if (!rst_ni) begin
946 unreachable icache_otp_key_q <= '0;
947 unreachable end else if (icache_otp_key_i.ack) begin
948 unreachable icache_otp_key_q <= icache_otp_key_i.key;
949 end
==> MISSING_ELSE
950 end
951 //VCS coverage on
952 // pragma coverage on
953
954 // Ensure that when a scramble key is received, it is correctly forwarded to the core. The core
955 // will then internally ensure that the key is correctly applied to the icache scrambled
956 // memory primitives.
957 `ASSERT(IbexIcacheScrambleKeyForwardedToCore_A,
958 icache_otp_key_i.ack
959 |-> ##[0:10] // upper bound is not exact, but it should not take more than 10 cycles
960 u_core.scramble_key_valid_i && (u_core.scramble_key_i == icache_otp_key_q)
961 )
962
963 // Ensure that when a FENCE.I is executed, a new icache scramble key is requested.
964 `ASSERT(IbexIcacheScrambleKeyRequestAfterFenceI_A,
965 u_core.u_ibex_core.id_stage_i.instr_valid_i
966 && u_core.u_ibex_core.id_stage_i.decoder_i.opcode == ibex_pkg::OPCODE_MISC_MEM
967 && u_core.u_ibex_core.id_stage_i.decoder_i.instr[14:12] == 3'b001 // FENCE.I
968 |-> ##[0:14] // upper bound is not exact, but it should not take more than a few cycles
969 icache_otp_key_o.req
970 )
971
972 end
973
974 `define ASSERT_IBEX_CORE_ERROR_TRIGGER_ALERT(__assert_name, __alert_name, _hier, __error_name) \
975 if (1) begin : g_``__error_name``_assert_signals \
976 logic __error_name; \
977 assign __error_name = u_core._hier``.__error_name; \
978 \
979 logic unused_assert_connected; \
980 `ASSERT_INIT_NET(AssertConnected_A, unused_assert_connected === 1'b1) \
981 end \
982 `ASSERT_ERROR_TRIGGER_ALERT(__assert_name, g_``__error_name``_assert_signals, __alert_name, 0, \
983 30, // MAX_CYCLES_, use a large value as ibex clock is 4x faster than clk in alert_handler \
984 __error_name)
985
986 0/1 ==> `ASSERT_IBEX_CORE_ERROR_TRIGGER_ALERT(IbexPcMismatchCheck_A, alert_tx_o[2],
ASSERT_IBEX_CORE_ERROR_TRIGGER_ALERT(IbexPcMism:
986.1 if (1) begin : g_pc_mismatch_alert_o_assert_signals
986.2 logic pc_mismatch_alert_o;
986.3 0/1 ==> assign pc_mismatch_alert_o = u_core.u_ibex_core.if_stage_i.pc_mismatch_alert_o;
986.4
986.5 logic unused_assert_connected;
986.6 initial begin
986.7
986.8
986.9
986.10 #1ps;
986.11 AssertConnected_A: assert (unused_assert_connected === 1'b1)
986.12 else begin
986.13 `ifdef UVM
986.14 uvm_pkg::uvm_report_error("ASSERT FAILED", "AssertConnected_A", uvm_pkg::UVM_NONE,
986.15 "../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv", 986, "", 1);
986.16 `else
986.17 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
986.18 `PRIM_STRINGIFY(AssertConnected_A));
986.19 `endif
986.20 end
986.21 end
986.22
986.23 end
986.24 FpvSecCmIbexPcMismatchCheck_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) ($rose(g_pc_mismatch_alert_o_assert_signals.pc_mismatch_alert_o) && !(0) |-> ##[0:30] ((alert_tx_o[2].alert_p))))
986.25 else begin
986.26 `ifdef UVM
986.27 uvm_pkg::uvm_report_error("ASSERT FAILED", "FpvSecCmIbexPcMismatchCheck_A", uvm_pkg::UVM_NONE,
986.28 "../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv", 986, "", 1);
986.29 `else
986.30 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
986.31 `PRIM_STRINGIFY(FpvSecCmIbexPcMismatchCheck_A));
986.32 `endif
986.33 end
986.34 `ifdef INC_ASSERT
986.35 assign g_pc_mismatch_alert_o_assert_signals.unused_assert_connected = 1'b1;
986.36 `endif
986.37 `ifdef FPV_ON
986.38 `ASSUME(IbexPcMismatchCheck_ATriggerAfterAlertInit_S, $stable(rst_ni) == 0 |-> g_pc_mismatch_alert_o_assert_signals.pc_mismatch_alert_o == 0 [*10], `ASSERT_DEFAULT_CLK, `ASSERT_DEFAULT_RST)
986.39 `endif987 u_ibex_core.if_stage_i, pc_mismatch_alert_o)
988 0/1 ==> `ASSERT_IBEX_CORE_ERROR_TRIGGER_ALERT(IbexRfEccErrCheck_A, alert_tx_o[2], u_ibex_core,
ASSERT_IBEX_CORE_ER:
988.1 if (1) begin : g_rf_ecc_err_comb_assert_signals
988.2 logic rf_ecc_err_comb;
988.3 0/1 ==> assign rf_ecc_err_comb = u_core.u_ibex_core.rf_ecc_err_comb;
988.4
988.5 logic unused_assert_connected;
988.6 initial begin
988.7
988.8
988.9
988.10 #1ps;
988.11 AssertConnected_A: assert (unused_assert_connected === 1'b1)
988.12 else begin
988.13 `ifdef UVM
988.14 uvm_pkg::uvm_report_error("ASSERT FAILED", "AssertConnected_A", uvm_pkg::UVM_NONE,
988.15 "../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv", 988, "", 1);
988.16 `else
988.17 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
988.18 `PRIM_STRINGIFY(AssertConnected_A));
988.19 `endif
988.20 end
988.21 end
988.22
988.23 end
988.24 FpvSecCmIbexRfEccErrCheck_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) ($rose(g_rf_ecc_err_comb_assert_signals.rf_ecc_err_comb) && !(0) |-> ##[0:30] ((alert_tx_o[2].alert_p))))
988.25 else begin
988.26 `ifdef UVM
988.27 uvm_pkg::uvm_report_error("ASSERT FAILED", "FpvSecCmIbexRfEccErrCheck_A", uvm_pkg::UVM_NONE,
988.28 "../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv", 988, "", 1);
988.29 `else
988.30 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
988.31 `PRIM_STRINGIFY(FpvSecCmIbexRfEccErrCheck_A));
988.32 `endif
988.33 end
988.34 `ifdef INC_ASSERT
988.35 assign g_rf_ecc_err_comb_assert_signals.unused_assert_connected = 1'b1;
988.36 `endif
988.37 `ifdef FPV_ON
988.38 `ASSUME(IbexRfEccErrCheck_ATriggerAfterAlertInit_S, $stable(rst_ni) == 0 |-> g_rf_ecc_err_comb_assert_signals.rf_ecc_err_comb == 0 [*10], `ASSERT_DEFAULT_CLK, `ASSERT_DEFAULT_RST)
988.39 `endif989 rf_ecc_err_comb)
990 1/1 `ASSERT_IBEX_CORE_ERROR_TRIGGER_ALERT(IbexLoadRespIntgErrCheck_A, alert_tx_o[2], u_ibex_core,
Tests: T1 T2 T3
ASSERT_IBEX_CORE_ERROR_TRI:
990.1 if (1) begin : g_lsu_load_resp_intg_err_assert_signals
990.2 logic lsu_load_resp_intg_err;
990.3 1/1 assign lsu_load_resp_intg_err = u_core.u_ibex_core.lsu_load_resp_intg_err;
Tests: T1 T2 T3
990.4
990.5 logic unused_assert_connected;
990.6 initial begin
990.7
990.8
990.9
990.10 #1ps;
990.11 AssertConnected_A: assert (unused_assert_connected === 1'b1)
990.12 else begin
990.13 `ifdef UVM
990.14 uvm_pkg::uvm_report_error("ASSERT FAILED", "AssertConnected_A", uvm_pkg::UVM_NONE,
990.15 "../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv", 990, "", 1);
990.16 `else
990.17 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
990.18 `PRIM_STRINGIFY(AssertConnected_A));
990.19 `endif
990.20 end
990.21 end
990.22
990.23 end
990.24 FpvSecCmIbexLoadRespIntgErrCheck_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) ($rose(g_lsu_load_resp_intg_err_assert_signals.lsu_load_resp_intg_err) && !(0) |-> ##[0:30] ((alert_tx_o[2].alert_p))))
990.25 else begin
990.26 `ifdef UVM
990.27 uvm_pkg::uvm_report_error("ASSERT FAILED", "FpvSecCmIbexLoadRespIntgErrCheck_A", uvm_pkg::UVM_NONE,
990.28 "../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv", 990, "", 1);
990.29 `else
990.30 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
990.31 `PRIM_STRINGIFY(FpvSecCmIbexLoadRespIntgErrCheck_A));
990.32 `endif
990.33 end
990.34 `ifdef INC_ASSERT
990.35 assign g_lsu_load_resp_intg_err_assert_signals.unused_assert_connected = 1'b1;
990.36 `endif
990.37 `ifdef FPV_ON
990.38 `ASSUME(IbexLoadRespIntgErrCheck_ATriggerAfterAlertInit_S, $stable(rst_ni) == 0 |-> g_lsu_load_resp_intg_err_assert_signals.lsu_load_resp_intg_err == 0 [*10], `ASSERT_DEFAULT_CLK, `ASSERT_DEFAULT_RST)
990.39 `endif991 lsu_load_resp_intg_err)
992 1/1 `ASSERT_IBEX_CORE_ERROR_TRIGGER_ALERT(IbexStoreRespIntgErrCheck_A, alert_tx_o[2], u_ibex_core,
Tests: T1 T2 T3
ASSERT_IBEX_CORE_ERROR_TRIG:
992.1 if (1) begin : g_lsu_store_resp_intg_err_assert_signals
992.2 logic lsu_store_resp_intg_err;
992.3 1/1 assign lsu_store_resp_intg_err = u_core.u_ibex_core.lsu_store_resp_intg_err;
Tests: T1 T2 T3
992.4
992.5 logic unused_assert_connected;
992.6 initial begin
992.7
992.8
992.9
992.10 #1ps;
992.11 AssertConnected_A: assert (unused_assert_connected === 1'b1)
992.12 else begin
992.13 `ifdef UVM
992.14 uvm_pkg::uvm_report_error("ASSERT FAILED", "AssertConnected_A", uvm_pkg::UVM_NONE,
992.15 "../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv", 992, "", 1);
992.16 `else
992.17 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
992.18 `PRIM_STRINGIFY(AssertConnected_A));
992.19 `endif
992.20 end
992.21 end
992.22
992.23 end
992.24 FpvSecCmIbexStoreRespIntgErrCheck_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) ($rose(g_lsu_store_resp_intg_err_assert_signals.lsu_store_resp_intg_err) && !(0) |-> ##[0:30] ((alert_tx_o[2].alert_p))))
992.25 else begin
992.26 `ifdef UVM
992.27 uvm_pkg::uvm_report_error("ASSERT FAILED", "FpvSecCmIbexStoreRespIntgErrCheck_A", uvm_pkg::UVM_NONE,
992.28 "../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv", 992, "", 1);
992.29 `else
992.30 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
992.31 `PRIM_STRINGIFY(FpvSecCmIbexStoreRespIntgErrCheck_A));
992.32 `endif
992.33 end
992.34 `ifdef INC_ASSERT
992.35 assign g_lsu_store_resp_intg_err_assert_signals.unused_assert_connected = 1'b1;
992.36 `endif
992.37 `ifdef FPV_ON
992.38 `ASSUME(IbexStoreRespIntgErrCheck_ATriggerAfterAlertInit_S, $stable(rst_ni) == 0 |-> g_lsu_store_resp_intg_err_assert_signals.lsu_store_resp_intg_err == 0 [*10], `ASSERT_DEFAULT_CLK, `ASSERT_DEFAULT_RST)
992.39 `endif993 lsu_store_resp_intg_err)
994 1/1 `ASSERT_IBEX_CORE_ERROR_TRIGGER_ALERT(IbexInstrIntgErrCheck_A, alert_tx_o[2], u_ibex_core,
Tests: T1 T2 T3
ASSERT_IBEX_CORE_E:
994.1 if (1) begin : g_instr_intg_err_assert_signals
994.2 logic instr_intg_err;
994.3 1/1 assign instr_intg_err = u_core.u_ibex_core.instr_intg_err;
Tests: T1 T2 T3
994.4
994.5 logic unused_assert_connected;
994.6 initial begin
994.7
994.8
994.9
994.10 #1ps;
994.11 AssertConnected_A: assert (unused_assert_connected === 1'b1)
994.12 else begin
994.13 `ifdef UVM
994.14 uvm_pkg::uvm_report_error("ASSERT FAILED", "AssertConnected_A", uvm_pkg::UVM_NONE,
994.15 "../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv", 994, "", 1);
994.16 `else
994.17 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
994.18 `PRIM_STRINGIFY(AssertConnected_A));
994.19 `endif
994.20 end
994.21 end
994.22
994.23 end
994.24 FpvSecCmIbexInstrIntgErrCheck_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) ($rose(g_instr_intg_err_assert_signals.instr_intg_err) && !(0) |-> ##[0:30] ((alert_tx_o[2].alert_p))))
994.25 else begin
994.26 `ifdef UVM
994.27 uvm_pkg::uvm_report_error("ASSERT FAILED", "FpvSecCmIbexInstrIntgErrCheck_A", uvm_pkg::UVM_NONE,
994.28 "../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv", 994, "", 1);
994.29 `else
994.30 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
994.31 `PRIM_STRINGIFY(FpvSecCmIbexInstrIntgErrCheck_A));
994.32 `endif
994.33 end
994.34 `ifdef INC_ASSERT
994.35 assign g_instr_intg_err_assert_signals.unused_assert_connected = 1'b1;
994.36 `endif
994.37 `ifdef FPV_ON
994.38 `ASSUME(IbexInstrIntgErrCheck_ATriggerAfterAlertInit_S, $stable(rst_ni) == 0 |-> g_instr_intg_err_assert_signals.instr_intg_err == 0 [*10], `ASSERT_DEFAULT_CLK, `ASSERT_DEFAULT_RST)
994.39 `endif
Cond Coverage for Module :
rv_core_ibex
| Total | Covered | Percent |
|---|
| Conditions | 28 | 25 | 89.29 |
| Logical | 28 | 25 | 89.29 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 216
EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
------1------ ------2------ -------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T82,T216,T209 |
| 0 | 1 | 0 | Not Covered | |
| 1 | 0 | 0 | Not Covered | |
LINE 217
EXPRESSION (alert_major_internal | double_fault)
----------1--------- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T260,T261,T262 |
| 1 | 0 | Covered | T164,T268,T226 |
LINE 348
EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T164,T260,T268 |
LINE 735
EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
----------------1--------------- ----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T75,T226,T192 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T75,T76,T77 |
LINE 737
EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
----------------1--------------- ----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T75,T76,T77 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T75,T226,T192 |
LINE 739
EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
----------------1--------------- ----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T75,T226,T192 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T75,T76,T77 |
LINE 741
EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
----------------1--------------- ----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T75,T226,T192 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T75,T76,T77 |
LINE 753
EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
----1--- -------2------ -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T164,T260,T268 |
| 0 | 1 | 0 | Covered | T82,T216,T209 |
| 1 | 0 | 0 | Covered | T269,T115,T270 |
LINE 800
EXPRESSION (edn_req && edn_ack)
---1--- ---2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T2,T4,T5 |
| 1 | 1 | Covered | T2,T3,T4 |
Toggle Coverage for Module :
rv_core_ibex
| Total | Covered | Percent |
| Totals |
123 |
117 |
95.12 |
| Total Bits |
1628 |
1604 |
98.53 |
| Total Bits 0->1 |
814 |
802 |
98.53 |
| Total Bits 1->0 |
814 |
802 |
98.53 |
| | | |
| Ports |
123 |
117 |
95.12 |
| Port Bits |
1628 |
1604 |
98.53 |
| Port Bits 0->1 |
814 |
802 |
98.53 |
| Port Bits 1->0 |
814 |
802 |
98.53 |
Port Details
| Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
| clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| rst_ni |
Yes |
Yes |
T30,T36,T42 |
Yes |
T1,T2,T3 |
INPUT |
| clk_edn_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| rst_edn_ni |
Yes |
Yes |
T30,T36,T42 |
Yes |
T1,T2,T3 |
INPUT |
| clk_esc_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| rst_esc_ni |
Yes |
Yes |
T30,T36,T42 |
Yes |
T1,T2,T3 |
INPUT |
| rst_cpu_n_o |
Yes |
Yes |
T30,T36,T42 |
Yes |
T1,T2,T3 |
OUTPUT |
| ram_cfg_i.rf_cfg.cfg[3:0] |
No |
No |
|
No |
|
INPUT |
| ram_cfg_i.rf_cfg.cfg_en |
No |
No |
|
No |
|
INPUT |
| ram_cfg_i.rf_cfg.test |
No |
No |
|
No |
|
INPUT |
| ram_cfg_i.ram_cfg.cfg[3:0] |
No |
No |
|
No |
|
INPUT |
| ram_cfg_i.ram_cfg.cfg_en |
No |
No |
|
No |
|
INPUT |
| ram_cfg_i.ram_cfg.test |
No |
No |
|
No |
|
INPUT |
| hart_id_i[31:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
| boot_addr_i[31:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
| corei_tl_h_o.d_ready |
Yes |
Yes |
T162,T271,T272 |
Yes |
T95,T96,T97 |
OUTPUT |
| corei_tl_h_o.a_user.data_intg[6:0] |
Yes |
Yes |
T95,T96,T97 |
Yes |
T95,T96,T97 |
OUTPUT |
| corei_tl_h_o.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| corei_tl_h_o.a_user.instr_type[3:0] |
Yes |
Yes |
T96,T162,T163 |
Yes |
T96,T101,T162 |
OUTPUT |
| corei_tl_h_o.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
| corei_tl_h_o.a_data[31:0] |
Yes |
Yes |
T95,T96,T97 |
Yes |
T95,T96,T97 |
OUTPUT |
| corei_tl_h_o.a_mask[3:0] |
Yes |
Yes |
T95,T96,T97 |
Yes |
T95,T96,T97 |
OUTPUT |
| corei_tl_h_o.a_address[31:0] |
Yes |
Yes |
T95,T96,T97 |
Yes |
T95,T96,T97 |
OUTPUT |
| corei_tl_h_o.a_source[5:0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| corei_tl_h_o.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
| corei_tl_h_o.a_size[1:0] |
Yes |
Yes |
T95,T96,T97 |
Yes |
T95,T96,T97 |
OUTPUT |
| corei_tl_h_o.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
| corei_tl_h_o.a_opcode[2:0] |
Yes |
Yes |
T95,T96,T97 |
Yes |
T95,T96,T97 |
OUTPUT |
| corei_tl_h_o.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| corei_tl_h_i.a_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| corei_tl_h_i.d_error |
Yes |
Yes |
T42,T212,T98 |
Yes |
T42,T212,T98 |
INPUT |
| corei_tl_h_i.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| corei_tl_h_i.d_user.rsp_intg[6:0] |
Yes |
Yes |
T42,T82,T212 |
Yes |
T42,T82,T212 |
INPUT |
| corei_tl_h_i.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| corei_tl_h_i.d_sink |
Yes |
Yes |
T95,T96,T97 |
Yes |
T95,T96,T97 |
INPUT |
| corei_tl_h_i.d_source[5:0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
| corei_tl_h_i.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
| corei_tl_h_i.d_size[1:0] |
Yes |
Yes |
T95,T96,T97 |
Yes |
T95,T96,T97 |
INPUT |
| corei_tl_h_i.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
| corei_tl_h_i.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
| corei_tl_h_i.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
| corei_tl_h_i.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| cored_tl_h_o.d_ready |
Yes |
Yes |
T35,T99,T100 |
Yes |
T35,T99,T100 |
OUTPUT |
| cored_tl_h_o.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| cored_tl_h_o.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| cored_tl_h_o.a_user.instr_type[3:0] |
Yes |
Yes |
T35,T68,T95 |
Yes |
T35,T68,T95 |
OUTPUT |
| cored_tl_h_o.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
| cored_tl_h_o.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| cored_tl_h_o.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| cored_tl_h_o.a_address[31:0] |
Yes |
Yes |
T35,T68,T95 |
Yes |
T35,T68,T95 |
OUTPUT |
| cored_tl_h_o.a_source[5:0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| cored_tl_h_o.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
| cored_tl_h_o.a_size[1:0] |
Yes |
Yes |
T35,T68,T95 |
Yes |
T35,T68,T95 |
OUTPUT |
| cored_tl_h_o.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
| cored_tl_h_o.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| cored_tl_h_o.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| cored_tl_h_i.a_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| cored_tl_h_i.d_error |
Yes |
Yes |
T42,T82,T208 |
Yes |
T42,T82,T208 |
INPUT |
| cored_tl_h_i.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| cored_tl_h_i.d_user.rsp_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| cored_tl_h_i.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| cored_tl_h_i.d_sink |
Yes |
Yes |
T95,T96,T97 |
Yes |
T95,T96,T97 |
INPUT |
| cored_tl_h_i.d_source[5:0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
| cored_tl_h_i.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
| cored_tl_h_i.d_size[1:0] |
Yes |
Yes |
T95,T96,T97 |
Yes |
T95,T96,T97 |
INPUT |
| cored_tl_h_i.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
| cored_tl_h_i.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
| cored_tl_h_i.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
| cored_tl_h_i.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| irq_software_i |
Yes |
Yes |
T273,T274,T275 |
Yes |
T273,T274,T275 |
INPUT |
| irq_timer_i |
Yes |
Yes |
T126,T127,T128 |
Yes |
T126,T127,T128 |
INPUT |
| irq_external_i |
Yes |
Yes |
T2,T4,T5 |
Yes |
T2,T4,T5 |
INPUT |
| esc_tx_i.esc_n |
Yes |
Yes |
T42,T82,T84 |
Yes |
T42,T82,T84 |
INPUT |
| esc_tx_i.esc_p |
Yes |
Yes |
T42,T82,T84 |
Yes |
T42,T82,T84 |
INPUT |
| esc_rx_o.resp_n |
Yes |
Yes |
T42,T82,T84 |
Yes |
T42,T82,T84 |
OUTPUT |
| esc_rx_o.resp_p |
Yes |
Yes |
T42,T82,T84 |
Yes |
T42,T82,T84 |
OUTPUT |
| nmi_wdog_i |
Yes |
Yes |
T5,T258,T259 |
Yes |
T5,T258,T259 |
INPUT |
| debug_req_i |
Yes |
Yes |
T98,T54,T55 |
Yes |
T98,T54,T55 |
INPUT |
| crash_dump_o.current.exception_addr[31:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
| crash_dump_o.current.exception_pc[31:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
| crash_dump_o.current.last_data_addr[31:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
| crash_dump_o.current.next_pc[31:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
| crash_dump_o.current.current_pc[31:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
| crash_dump_o.prev_exception_addr[31:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
| crash_dump_o.prev_exception_pc[31:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
| crash_dump_o.prev_valid |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
| lc_cpu_en_i[3:0] |
Yes |
Yes |
T42,T37,T43 |
Yes |
T1,T2,T3 |
INPUT |
| pwrmgr_cpu_en_i[3:0] |
Yes |
Yes |
T4,T5,T26 |
Yes |
T1,T2,T3 |
INPUT |
| pwrmgr_o.core_sleeping |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| scan_rst_ni |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
| scanmode_i[3:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
| cfg_tl_d_i.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| cfg_tl_d_i.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| cfg_tl_d_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| cfg_tl_d_i.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| cfg_tl_d_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
| cfg_tl_d_i.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| cfg_tl_d_i.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| cfg_tl_d_i.a_address[7:0] |
Yes |
Yes |
*T96,*T97,*T101 |
Yes |
T96,T97,T101 |
INPUT |
| cfg_tl_d_i.a_address[15:8] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
| cfg_tl_d_i.a_address[20:16] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| cfg_tl_d_i.a_address[23:21] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
| cfg_tl_d_i.a_address[24] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
| cfg_tl_d_i.a_address[29:25] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
| cfg_tl_d_i.a_address[30] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
| cfg_tl_d_i.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
| cfg_tl_d_i.a_source[5:0] |
Yes |
Yes |
*T54,*T68,*T95 |
Yes |
T54,T68,T95 |
INPUT |
| cfg_tl_d_i.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
| cfg_tl_d_i.a_size[1:0] |
Yes |
Yes |
T95,T96,T97 |
Yes |
T95,T96,T97 |
INPUT |
| cfg_tl_d_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
| cfg_tl_d_i.a_opcode[2:0] |
Yes |
Yes |
T95,T96,T97 |
Yes |
T95,T96,T97 |
INPUT |
| cfg_tl_d_i.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| cfg_tl_d_o.a_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| cfg_tl_d_o.d_error |
Yes |
Yes |
T68,T95,T97 |
Yes |
T68,T95,T97 |
OUTPUT |
| cfg_tl_d_o.d_user.data_intg[6:0] |
Yes |
Yes |
T2,T4,T5 |
Yes |
T2,T4,T5 |
OUTPUT |
| cfg_tl_d_o.d_user.rsp_intg[6:0] |
Yes |
Yes |
T2,T3,T4 |
Yes |
T1,T2,T3 |
OUTPUT |
| cfg_tl_d_o.d_data[31:0] |
Yes |
Yes |
T2,T4,T5 |
Yes |
T2,T4,T5 |
OUTPUT |
| cfg_tl_d_o.d_sink |
Yes |
Yes |
T95,T96,T97 |
Yes |
T95,T97,T101 |
OUTPUT |
| cfg_tl_d_o.d_source[5:0] |
Yes |
Yes |
*T68,*T97,*T162 |
Yes |
T54,T68,T95 |
OUTPUT |
| cfg_tl_d_o.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
| cfg_tl_d_o.d_size[1:0] |
Yes |
Yes |
T95,T96,T97 |
Yes |
T96,T97,T101 |
OUTPUT |
| cfg_tl_d_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
| cfg_tl_d_o.d_opcode[0] |
Yes |
Yes |
*T2,*T3,*T4 |
Yes |
T2,T3,T4 |
OUTPUT |
| cfg_tl_d_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
| cfg_tl_d_o.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| edn_o.edn_req |
Yes |
Yes |
T2,T3,T4 |
Yes |
T1,T2,T3 |
OUTPUT |
| edn_i.edn_bus[31:0] |
Yes |
Yes |
T121,T12,T42 |
Yes |
T2,T4,T5 |
INPUT |
| edn_i.edn_fips |
Yes |
Yes |
T157,T276,T277 |
Yes |
T157,T267,T145 |
INPUT |
| edn_i.edn_ack |
Yes |
Yes |
T2,T3,T4 |
Yes |
T2,T3,T4 |
INPUT |
| clk_otp_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| rst_otp_ni |
Yes |
Yes |
T30,T36,T42 |
Yes |
T1,T2,T3 |
INPUT |
| icache_otp_key_o.req |
Yes |
Yes |
T212,T213,T214 |
Yes |
T212,T213,T214 |
OUTPUT |
| icache_otp_key_i.seed_valid |
Yes |
Yes |
T42,T37,T43 |
Yes |
T2,T3,T4 |
INPUT |
| icache_otp_key_i.nonce[127:0] |
Yes |
Yes |
T4,T105,T6 |
Yes |
T4,T105,T6 |
INPUT |
| icache_otp_key_i.key[127:0] |
Yes |
Yes |
T2,T3,T4 |
Yes |
T105,T6,T32 |
INPUT |
| icache_otp_key_i.ack |
Yes |
Yes |
T213,T214,T215 |
Yes |
T213,T214,T215 |
INPUT |
| fpga_info_i[31:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
| alert_rx_i[0].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| alert_rx_i[0].ack_p |
Yes |
Yes |
T75,T102,T103 |
Yes |
T75,T102,T103 |
INPUT |
| alert_rx_i[0].ping_n |
Yes |
Yes |
T102,T103,T104 |
Yes |
T103,T104,T193 |
INPUT |
| alert_rx_i[0].ping_p |
Yes |
Yes |
T103,T104,T193 |
Yes |
T102,T103,T104 |
INPUT |
| alert_rx_i[1].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| alert_rx_i[1].ack_p |
Yes |
Yes |
T75,T102,T226 |
Yes |
T75,T102,T226 |
INPUT |
| alert_rx_i[1].ping_n |
Yes |
Yes |
T102,T103,T104 |
Yes |
T102,T103,T104 |
INPUT |
| alert_rx_i[1].ping_p |
Yes |
Yes |
T102,T103,T104 |
Yes |
T102,T103,T104 |
INPUT |
| alert_rx_i[2].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| alert_rx_i[2].ack_p |
Yes |
Yes |
T82,T216,T260 |
Yes |
T82,T216,T260 |
INPUT |
| alert_rx_i[2].ping_n |
Yes |
Yes |
T102,T103,T104 |
Yes |
T102,T103,T104 |
INPUT |
| alert_rx_i[2].ping_p |
Yes |
Yes |
T102,T103,T104 |
Yes |
T102,T103,T104 |
INPUT |
| alert_rx_i[3].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| alert_rx_i[3].ack_p |
Yes |
Yes |
T75,T102,T103 |
Yes |
T75,T102,T103 |
INPUT |
| alert_rx_i[3].ping_n |
Yes |
Yes |
T102,T103,T104 |
Yes |
T102,T103,T104 |
INPUT |
| alert_rx_i[3].ping_p |
Yes |
Yes |
T102,T103,T104 |
Yes |
T102,T103,T104 |
INPUT |
| alert_tx_o[0].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| alert_tx_o[0].alert_p |
Yes |
Yes |
T75,T102,T103 |
Yes |
T75,T102,T103 |
OUTPUT |
| alert_tx_o[1].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| alert_tx_o[1].alert_p |
Yes |
Yes |
T75,T102,T226 |
Yes |
T75,T102,T226 |
OUTPUT |
| alert_tx_o[2].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| alert_tx_o[2].alert_p |
Yes |
Yes |
T82,T216,T260 |
Yes |
T82,T216,T260 |
OUTPUT |
| alert_tx_o[3].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| alert_tx_o[3].alert_p |
Yes |
Yes |
T75,T102,T103 |
Yes |
T75,T102,T103 |
OUTPUT |
*Tests covering at least one bit in the range
Branch Coverage for Module :
rv_core_ibex
| Line No. | Total | Covered | Percent |
| Branches |
|
12 |
12 |
100.00 |
| TERNARY |
348 |
2 |
2 |
100.00 |
| IF |
492 |
2 |
2 |
100.00 |
| IF |
518 |
3 |
3 |
100.00 |
| IF |
796 |
3 |
3 |
100.00 |
| IF |
808 |
2 |
2 |
100.00 |
348 assign local_fetch_enable_d = fatal_core_err ? lc_ctrl_pkg::Off : local_fetch_enable_q;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T164,T260,T268 |
| 0 |
Covered |
T1,T2,T3 |
492 if (!rst_ni) begin
-1-
493 core_sleep_q <= '0;
==>
494 end else begin
495 core_sleep_q <= core_sleep;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
518 if (!rst_ni) begin
-1-
519 prev_valid <= '0;
==>
520 prev_exception_pc <= '0;
521 prev_exception_addr <= '0;
522 end else if (double_fault) begin
-2-
523 prev_valid <= 1'b1;
==>
524 prev_exception_pc <= crash_dump.exception_pc;
525 prev_exception_addr <= crash_dump.exception_addr;
526 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T260,T261,T262 |
| 0 |
0 |
Covered |
T1,T2,T3 |
796 if (reg2hw.rnd_data.re) begin
-1-
797 rnd_valid_d = '0;
==>
798 rnd_data_d = '0;
799 rnd_fips_d = '0;
800 end else if (edn_req && edn_ack) begin
-2-
801 rnd_valid_d = 1'b1;
==>
802 rnd_data_d = edn_data;
803 rnd_fips_d = edn_fips;
804 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T2,T4,T5 |
| 0 |
1 |
Covered |
T2,T3,T4 |
| 0 |
0 |
Covered |
T2,T3,T4 |
808 if (!rst_ni) begin
-1-
809 rnd_valid_q <= '0;
==>
810 rnd_data_q <= '0;
811 rnd_fips_q <= '0;
812 end else begin
813 rnd_valid_q <= rnd_valid_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
rv_core_ibex
Assertion Details
FpvSecCmIbexFetchEnable0_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
516490638 |
10 |
0 |
0 |
| T66 |
272702 |
0 |
0 |
0 |
| T75 |
92338 |
0 |
0 |
0 |
| T140 |
153467 |
0 |
0 |
0 |
| T196 |
419025 |
0 |
0 |
0 |
| T201 |
463797 |
0 |
0 |
0 |
| T259 |
212403 |
0 |
0 |
0 |
| T260 |
300457 |
1 |
0 |
0 |
| T261 |
0 |
1 |
0 |
0 |
| T262 |
0 |
1 |
0 |
0 |
| T268 |
219251 |
0 |
0 |
0 |
| T278 |
0 |
1 |
0 |
0 |
| T279 |
0 |
1 |
0 |
0 |
| T280 |
0 |
1 |
0 |
0 |
| T281 |
0 |
1 |
0 |
0 |
| T282 |
0 |
1 |
0 |
0 |
| T283 |
0 |
1 |
0 |
0 |
| T284 |
0 |
1 |
0 |
0 |
| T285 |
218340 |
0 |
0 |
0 |
| T286 |
176294 |
0 |
0 |
0 |
FpvSecCmIbexFetchEnable1_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
516490638 |
25340130 |
0 |
92 |
| T1 |
42248 |
9923 |
0 |
0 |
| T2 |
84649 |
9919 |
0 |
0 |
| T3 |
76631 |
9927 |
0 |
0 |
| T4 |
104153 |
9919 |
0 |
0 |
| T5 |
127764 |
9931 |
0 |
0 |
| T6 |
79367 |
9931 |
0 |
0 |
| T26 |
87872 |
9919 |
0 |
0 |
| T30 |
0 |
0 |
0 |
2 |
| T31 |
0 |
0 |
0 |
2 |
| T34 |
36418 |
36354 |
0 |
2 |
| T35 |
0 |
0 |
0 |
2 |
| T36 |
0 |
0 |
0 |
2 |
| T37 |
0 |
0 |
0 |
2 |
| T83 |
0 |
0 |
0 |
2 |
| T99 |
0 |
0 |
0 |
2 |
| T105 |
61525 |
9923 |
0 |
0 |
| T106 |
94103 |
9923 |
0 |
0 |
| T287 |
0 |
0 |
0 |
2 |
| T288 |
0 |
0 |
0 |
2 |
FpvSecCmIbexFetchEnable2_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
516490638 |
66664375 |
0 |
82 |
| T1 |
42248 |
34775 |
0 |
0 |
| T2 |
84649 |
34775 |
0 |
0 |
| T3 |
76631 |
34775 |
0 |
0 |
| T4 |
104153 |
36292 |
0 |
0 |
| T5 |
127764 |
34791 |
0 |
0 |
| T6 |
79367 |
34775 |
0 |
0 |
| T7 |
0 |
0 |
0 |
2 |
| T26 |
87872 |
38300 |
0 |
0 |
| T30 |
0 |
0 |
0 |
2 |
| T34 |
36418 |
34775 |
0 |
0 |
| T35 |
0 |
0 |
0 |
2 |
| T36 |
0 |
0 |
0 |
2 |
| T37 |
0 |
0 |
0 |
2 |
| T53 |
0 |
0 |
0 |
2 |
| T99 |
0 |
0 |
0 |
2 |
| T105 |
61525 |
34775 |
0 |
0 |
| T106 |
94103 |
34775 |
0 |
0 |
| T287 |
0 |
0 |
0 |
2 |
| T289 |
0 |
0 |
0 |
2 |
| T290 |
0 |
0 |
0 |
2 |
FpvSecCmIbexFetchEnable3Rev_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
516490638 |
444797408 |
0 |
2026 |
| T1 |
42248 |
7415 |
0 |
2 |
| T2 |
84649 |
49820 |
0 |
2 |
| T3 |
76631 |
41791 |
0 |
2 |
| T4 |
104153 |
67802 |
0 |
2 |
| T5 |
127764 |
92912 |
0 |
2 |
| T6 |
79367 |
44527 |
0 |
2 |
| T26 |
87872 |
49513 |
0 |
2 |
| T34 |
36418 |
0 |
0 |
2 |
| T105 |
61525 |
26692 |
0 |
2 |
| T106 |
94103 |
59274 |
0 |
2 |
| T121 |
0 |
61432 |
0 |
0 |
FpvSecCmIbexFetchEnable3_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
516490638 |
444799324 |
0 |
1922 |
| T1 |
42248 |
7416 |
0 |
2 |
| T2 |
84649 |
49821 |
0 |
2 |
| T3 |
76631 |
41792 |
0 |
2 |
| T4 |
104153 |
67804 |
0 |
2 |
| T5 |
127764 |
92913 |
0 |
2 |
| T6 |
79367 |
44528 |
0 |
2 |
| T26 |
87872 |
49515 |
0 |
2 |
| T34 |
36418 |
0 |
0 |
0 |
| T105 |
61525 |
26693 |
0 |
2 |
| T106 |
94103 |
59275 |
0 |
2 |
| T121 |
0 |
61433 |
0 |
2 |
FpvSecCmIbexInstrIntgErrCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
516490638 |
307 |
0 |
0 |
| T10 |
408746 |
0 |
0 |
0 |
| T59 |
289057 |
0 |
0 |
0 |
| T63 |
243025 |
0 |
0 |
0 |
| T82 |
253757 |
77 |
0 |
0 |
| T84 |
242849 |
0 |
0 |
0 |
| T131 |
231889 |
0 |
0 |
0 |
| T148 |
214752 |
0 |
0 |
0 |
| T218 |
164084 |
0 |
0 |
0 |
| T238 |
249256 |
0 |
0 |
0 |
| T291 |
0 |
77 |
0 |
0 |
| T292 |
0 |
76 |
0 |
0 |
| T293 |
0 |
77 |
0 |
0 |
| T294 |
213144 |
0 |
0 |
0 |
FpvSecCmIbexLoadRespIntgErrCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
516490638 |
587 |
0 |
0 |
| T66 |
272702 |
0 |
0 |
0 |
| T75 |
92338 |
0 |
0 |
0 |
| T151 |
0 |
31 |
0 |
0 |
| T196 |
419025 |
0 |
0 |
0 |
| T201 |
463797 |
0 |
0 |
0 |
| T209 |
0 |
32 |
0 |
0 |
| T210 |
0 |
32 |
0 |
0 |
| T216 |
153072 |
100 |
0 |
0 |
| T259 |
212403 |
0 |
0 |
0 |
| T260 |
300457 |
0 |
0 |
0 |
| T268 |
219251 |
0 |
0 |
0 |
| T285 |
218340 |
0 |
0 |
0 |
| T286 |
176294 |
0 |
0 |
0 |
| T295 |
0 |
100 |
0 |
0 |
| T296 |
0 |
31 |
0 |
0 |
| T297 |
0 |
32 |
0 |
0 |
| T298 |
0 |
31 |
0 |
0 |
| T299 |
0 |
99 |
0 |
0 |
| T300 |
0 |
32 |
0 |
0 |
FpvSecCmIbexLockstepResetCountAlertCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
516490638 |
0 |
0 |
0 |
FpvSecCmIbexPcMismatchCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
516490638 |
0 |
0 |
0 |
FpvSecCmIbexRfEccErrCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
516490638 |
0 |
0 |
0 |
FpvSecCmIbexStoreRespIntgErrCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
516490638 |
0 |
0 |
0 |
FpvSecCmRegWeOnehotCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
516490638 |
7 |
0 |
0 |
| T115 |
0 |
1 |
0 |
0 |
| T173 |
392483 |
0 |
0 |
0 |
| T269 |
129596 |
1 |
0 |
0 |
| T270 |
0 |
1 |
0 |
0 |
| T278 |
226813 |
0 |
0 |
0 |
| T301 |
0 |
1 |
0 |
0 |
| T302 |
0 |
1 |
0 |
0 |
| T303 |
0 |
1 |
0 |
0 |
| T304 |
0 |
1 |
0 |
0 |
| T305 |
290216 |
0 |
0 |
0 |
| T306 |
422109 |
0 |
0 |
0 |
| T307 |
206069 |
0 |
0 |
0 |
| T308 |
186882 |
0 |
0 |
0 |
| T309 |
138013 |
0 |
0 |
0 |
| T310 |
400822 |
0 |
0 |
0 |
| T311 |
449254 |
0 |
0 |
0 |
FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
516490638 |
0 |
0 |
0 |
FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
516490638 |
0 |
0 |
0 |
FpvSecCmRvCoreRegWeOnehotCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
516490638 |
0 |
0 |
0 |
g_instr_intg_err_assert_signals.AssertConnected_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1025 |
1025 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T26 |
1 |
1 |
0 |
0 |
| T34 |
1 |
1 |
0 |
0 |
| T105 |
1 |
1 |
0 |
0 |
| T106 |
1 |
1 |
0 |
0 |
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1025 |
1025 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T26 |
1 |
1 |
0 |
0 |
| T34 |
1 |
1 |
0 |
0 |
| T105 |
1 |
1 |
0 |
0 |
| T106 |
1 |
1 |
0 |
0 |
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1025 |
1025 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T26 |
1 |
1 |
0 |
0 |
| T34 |
1 |
1 |
0 |
0 |
| T105 |
1 |
1 |
0 |
0 |
| T106 |
1 |
1 |
0 |
0 |
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1025 |
1025 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T26 |
1 |
1 |
0 |
0 |
| T34 |
1 |
1 |
0 |
0 |
| T105 |
1 |
1 |
0 |
0 |
| T106 |
1 |
1 |
0 |
0 |
g_rf_ecc_err_comb_assert_signals.AssertConnected_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1025 |
1025 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T26 |
1 |
1 |
0 |
0 |
| T34 |
1 |
1 |
0 |
0 |
| T105 |
1 |
1 |
0 |
0 |
| T106 |
1 |
1 |
0 |
0 |
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
516490638 |
230 |
0 |
0 |
| T91 |
211864 |
0 |
0 |
0 |
| T123 |
166559 |
0 |
0 |
0 |
| T167 |
182279 |
0 |
0 |
0 |
| T213 |
81443 |
45 |
0 |
0 |
| T214 |
105437 |
32 |
0 |
0 |
| T215 |
0 |
33 |
0 |
0 |
| T236 |
650384 |
0 |
0 |
0 |
| T263 |
0 |
34 |
0 |
0 |
| T276 |
637696 |
0 |
0 |
0 |
| T312 |
0 |
37 |
0 |
0 |
| T313 |
0 |
49 |
0 |
0 |
| T314 |
85784 |
0 |
0 |
0 |
| T315 |
596324 |
0 |
0 |
0 |
| T316 |
118205 |
0 |
0 |
0 |
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
516490638 |
206 |
0 |
0 |
| T88 |
119156 |
0 |
0 |
0 |
| T153 |
184117 |
0 |
0 |
0 |
| T154 |
211020 |
0 |
0 |
0 |
| T183 |
430847 |
0 |
0 |
0 |
| T212 |
385747 |
16 |
0 |
0 |
| T213 |
0 |
11 |
0 |
0 |
| T214 |
0 |
42 |
0 |
0 |
| T215 |
0 |
42 |
0 |
0 |
| T219 |
327753 |
0 |
0 |
0 |
| T263 |
0 |
42 |
0 |
0 |
| T312 |
0 |
9 |
0 |
0 |
| T313 |
0 |
12 |
0 |
0 |
| T317 |
0 |
16 |
0 |
0 |
| T318 |
0 |
16 |
0 |
0 |
| T319 |
271490 |
0 |
0 |
0 |
| T320 |
407978 |
0 |
0 |
0 |
| T321 |
626534 |
0 |
0 |
0 |
| T322 |
126541 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 85 | 82 | 96.47 |
| CONT_ASSIGN | 202 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 203 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 216 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 217 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 218 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 225 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 263 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 265 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 268 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 342 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 348 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 363 | 1 | 1 | 100.00 |
| ALWAYS | 492 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 512 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 513 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 514 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 515 | 1 | 1 | 100.00 |
| ALWAYS | 518 | 8 | 8 | 100.00 |
| CONT_ASSIGN | 702 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 702 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 703 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 703 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 704 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 704 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 708 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 708 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 709 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 709 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 710 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 710 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 717 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 718 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 719 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 722 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 724 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 726 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 728 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 735 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 737 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 739 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 741 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 751 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 752 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 753 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 754 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 757 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 760 | 1 | 1 | 100.00 |
| ALWAYS | 792 | 11 | 11 | 100.00 |
| ALWAYS | 808 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 819 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 838 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 839 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 840 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 843 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 847 | 0 | 0 | |
| CONT_ASSIGN | 886 | 1 | 1 | 100.00 |
| ALWAYS | 945 | 0 | 0 | |
| CONT_ASSIGN | 986 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 988 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 990 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 992 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 994 | 1 | 1 | 100.00 |
201 logic addr_trans_rst_ni;
202 1/1 assign ibex_top_clk_i = clk_i;
Tests: T1 T2 T3
203 1/1 assign addr_trans_rst_ni = rst_ni;
Tests: T1 T2 T3
204
205 // errors and core alert events
206 logic ibus_intg_err, dbus_intg_err;
207 logic alert_minor, alert_major_internal, alert_major_bus;
208 logic double_fault;
209 logic fatal_intg_err, fatal_core_err, recov_core_err;
210
211 // alert events to peripheral module
212 logic fatal_intg_event;
213 logic fatal_core_event;
214 logic recov_core_event;
215 // SEC_CM: BUS.INTEGRITY
216 1/1 assign fatal_intg_event = ibus_intg_err | dbus_intg_err | alert_major_bus;
Tests: T1 T2 T3
217 1/1 assign fatal_core_event = alert_major_internal | double_fault;
Tests: T1 T2 T3
218 1/1 assign recov_core_event = alert_minor;
Tests: T2 T3 T4
219
220 // configurations for address translation
221 region_cfg_t [NumRegions-1:0] ibus_region_cfg;
222 region_cfg_t [NumRegions-1:0] dbus_region_cfg;
223
224 // Reset feedback to clkmgr
225 1/1 assign rst_cpu_n_o = rst_ni;
Tests: T1 T2 T3
226
227 // Escalation receiver that converts differential
228 // protocol into single ended signal.
229 logic esc_irq_nm;
230 prim_esc_receiver #(
231 .N_ESC_SEV (alert_handler_reg_pkg::N_ESC_SEV),
232 .PING_CNT_DW (alert_handler_reg_pkg::PING_CNT_DW)
233 ) u_prim_esc_receiver (
234 .clk_i ( clk_esc_i ),
235 .rst_ni ( rst_esc_ni ),
236 .esc_req_o ( esc_irq_nm ),
237 .esc_rx_o,
238 .esc_tx_i
239 );
240
241 // Synchronize to fast Ibex clock domain.
242 logic alert_irq_nm;
243 prim_flop_2sync #(
244 .Width(1)
245 ) u_alert_nmi_sync (
246 .clk_i,
247 .rst_ni,
248 .d_i(esc_irq_nm),
249 .q_o(alert_irq_nm)
250 );
251
252 logic wdog_irq_nm;
253 prim_flop_2sync #(
254 .Width(1)
255 ) u_wdog_nmi_sync (
256 .clk_i,
257 .rst_ni,
258 .d_i(nmi_wdog_i),
259 .q_o(wdog_irq_nm)
260 );
261
262 assign hw2reg.nmi_state.alert.d = 1'b1;
263 1/1 assign hw2reg.nmi_state.alert.de = alert_irq_nm;
Tests: T42 T82 T84
264 assign hw2reg.nmi_state.wdog.d = 1'b1;
265 1/1 assign hw2reg.nmi_state.wdog.de = wdog_irq_nm;
Tests: T5 T258 T259
266
267 logic irq_nm;
268 1/1 assign irq_nm = |(reg2hw.nmi_state & reg2hw.nmi_enable);
Tests: T5 T42 T82
269
270 lc_ctrl_pkg::lc_tx_t [0:0] lc_cpu_en;
271 prim_lc_sync u_lc_sync (
272 .clk_i,
273 .rst_ni,
274 .lc_en_i(lc_cpu_en_i),
275 .lc_en_o(lc_cpu_en)
276 );
277
278 lc_ctrl_pkg::lc_tx_t [0:0] pwrmgr_cpu_en;
279 prim_lc_sync u_pwrmgr_sync (
280 .clk_i,
281 .rst_ni,
282 .lc_en_i(pwrmgr_cpu_en_i),
283 .lc_en_o(pwrmgr_cpu_en)
284 );
285
286 // timer interrupts do not come from
287 // rv_plic and may not be synchronous to the ibex core
288 logic irq_timer_sync;
289 prim_flop_2sync #(
290 .Width(1)
291 ) u_intr_timer_sync (
292 .clk_i,
293 .rst_ni,
294 .d_i(irq_timer_i),
295 .q_o(irq_timer_sync)
296 );
297
298
299 logic irq_software;
300 logic irq_timer;
301 logic irq_external;
302
303 prim_sec_anchor_buf #(
304 .Width(3)
305 ) u_prim_buf_irq (
306 .in_i({irq_software_i,
307 irq_timer_sync,
308 irq_external_i}),
309 .out_o({irq_software,
310 irq_timer,
311 irq_external})
312 );
313
314
315 logic key_req, key_ack;
316 logic [ibex_pkg::SCRAMBLE_KEY_W-1:0] key;
317 logic [ibex_pkg::SCRAMBLE_NONCE_W-1:0] nonce;
318 logic unused_seed_valid;
319 localparam int PayLoadW = ibex_pkg::SCRAMBLE_KEY_W + ibex_pkg::SCRAMBLE_NONCE_W + 1;
320 prim_sync_reqack_data #(
321 .Width(PayLoadW),
322 .DataSrc2Dst(1'b0)
323 ) u_prim_sync_reqack_data (
324 .clk_src_i ( clk_i ),
325 .rst_src_ni ( rst_ni ),
326 .clk_dst_i ( clk_otp_i ),
327 .rst_dst_ni ( rst_otp_ni ),
328 .req_chk_i ( 1'b1 ),
329 .src_req_i ( key_req ),
330 .src_ack_o ( key_ack ),
331 .dst_req_o ( icache_otp_key_o.req ),
332 .dst_ack_i ( icache_otp_key_i.ack ),
333 .data_i ( {icache_otp_key_i.key,
334 icache_otp_key_i.nonce[ibex_pkg::SCRAMBLE_NONCE_W-1:0],
335 icache_otp_key_i.seed_valid} ),
336 .data_o ( {key,
337 nonce,
338 unused_seed_valid} )
339 );
340
341 logic unused_nonce;
342 1/1 assign unused_nonce = |icache_otp_key_i.nonce;
Tests: T2 T3 T4
343
344 // Local fetch enable control.
345 // Whenever a fatal core error is seen disable local fetch enable.
346 lc_ctrl_pkg::lc_tx_t local_fetch_enable_d, local_fetch_enable_q;
347
348 1/1 assign local_fetch_enable_d = fatal_core_err ? lc_ctrl_pkg::Off : local_fetch_enable_q;
Tests: T1 T2 T3
349
350 prim_lc_sender #(
351 .AsyncOn(1), // this instantiates a register
352 .ResetValueIsOn(1)
353 ) u_prim_lc_sender (
354 .clk_i,
355 .rst_ni,
356 .lc_en_i(local_fetch_enable_d),
357 .lc_en_o(local_fetch_enable_q)
358 );
359
360 // Multibit AND computation for fetch enable. Fetch is only enabled when local fetch enable,
361 // lifecycle CPU enable and power manager CPU enable are all enabled.
362 lc_ctrl_pkg::lc_tx_t fetch_enable;
363 1/1 assign fetch_enable = lc_ctrl_pkg::lc_tx_and_hi(local_fetch_enable_q,
Tests: T1 T2 T3
364 lc_ctrl_pkg::lc_tx_and_hi(lc_cpu_en[0],
365 pwrmgr_cpu_en[0]));
366
367 ibex_pkg::crash_dump_t crash_dump;
368 ibex_top #(
369 .PMPEnable ( PMPEnable ),
370 .PMPGranularity ( PMPGranularity ),
371 .PMPNumRegions ( PMPNumRegions ),
372 .MHPMCounterNum ( MHPMCounterNum ),
373 .MHPMCounterWidth ( MHPMCounterWidth ),
374 .RV32E ( RV32E ),
375 .RV32M ( RV32M ),
376 .RV32B ( RV32B ),
377 .RegFile ( RegFile ),
378 .BranchTargetALU ( BranchTargetALU ),
379 .WritebackStage ( WritebackStage ),
380 .ICache ( ICache ),
381 // Our automatic SEC_CM label check doesn't look at vendored code so the SEC_CM labels need
382 // to be mentioned here. The real locations can be found by grepping the vendored code.
383 // TODO(#10071): this should be fixed.
384 // SEC_CM: ICACHE.MEM.INTEGRITY
385 .ICacheECC ( ICacheECC ),
386 // SEC_CM: ICACHE.MEM.SCRAMBLE, SCRAMBLE.KEY.SIDELOAD
387 .ICacheScramble ( ICacheScramble ),
388 // Reduce the number of PRINCE half rounds to 2 (5 effective rounds) to ease timing. This is
389 // acceptable for the instruction cache, whereas 3 half rounds (7 effective rounds) are used
390 // elsewhere in the design.
391 .ICacheScrNumPrinceRoundsHalf( 2 ),
392 .BranchPredictor ( BranchPredictor ),
393 .DbgTriggerEn ( DbgTriggerEn ),
394 .DbgHwBreakNum ( DbgHwBreakNum ),
395 // SEC_CM: LOGIC.SHADOW
396 // SEC_CM: PC.CTRL_FLOW.CONSISTENCY, CTRL_FLOW.UNPREDICTABLE, CORE.DATA_REG_SW.SCA
397 // SEC_CM: EXCEPTION.CTRL_FLOW.GLOBAL_ESC, EXCEPTION.CTRL_FLOW.LOCAL_ESC
398 // SEC_CM: DATA_REG_SW.INTEGRITY, DATA_REG_SW.GLITCH_DETECT
399 .SecureIbex ( SecureIbex ),
400 .RndCnstLfsrSeed ( RndCnstLfsrSeed ),
401 .RndCnstLfsrPerm ( RndCnstLfsrPerm ),
402 .RndCnstIbexKey ( RndCnstIbexKeyDefault ),
403 .RndCnstIbexNonce ( RndCnstIbexNonceDefault ),
404 .DmHaltAddr ( DmHaltAddr ),
405 .DmExceptionAddr ( DmExceptionAddr )
406 ) u_core (
407 .clk_i (ibex_top_clk_i),
408 .rst_ni,
409
410
411 .test_en_i (prim_mubi_pkg::mubi4_test_true_strict(scanmode_i)),
412 .scan_rst_ni,
413
414 .ram_cfg_i,
415
416 .hart_id_i,
417 .boot_addr_i,
418
419 .instr_req_o ( instr_req ),
420 .instr_gnt_i ( instr_gnt ),
421 .instr_rvalid_i ( instr_rvalid ),
422 .instr_addr_o ( instr_addr ),
423 .instr_rdata_i ( instr_rdata ),
424 .instr_rdata_intg_i ( instr_rdata_intg ),
425 .instr_err_i ( instr_err ),
426
427 .data_req_o ( data_req ),
428 .data_gnt_i ( data_gnt ),
429 .data_rvalid_i ( data_rvalid ),
430 .data_we_o ( data_we ),
431 .data_be_o ( data_be ),
432 .data_addr_o ( data_addr ),
433 .data_wdata_o ( data_wdata ),
434 .data_wdata_intg_o ( data_wdata_intg ),
435 .data_rdata_i ( data_rdata ),
436 .data_rdata_intg_i ( data_rdata_intg ),
437 .data_err_i ( data_err ),
438
439 .irq_software_i ( irq_software ),
440 .irq_timer_i ( irq_timer ),
441 .irq_external_i ( irq_external ),
442 .irq_fast_i ( '0 ),
443 .irq_nm_i ( irq_nm ),
444
445 .debug_req_i,
446 .crash_dump_o ( crash_dump ),
447
448 // icache scramble interface
449 .scramble_key_valid_i (key_ack),
450 .scramble_key_i (key),
451 .scramble_nonce_i (nonce),
452 .scramble_req_o (key_req),
453
454 // double fault
455 .double_fault_seen_o (double_fault),
456
457 `ifdef RVFI
458 .rvfi_valid,
459 .rvfi_order,
460 .rvfi_insn,
461 .rvfi_trap,
462 .rvfi_halt,
463 .rvfi_intr,
464 .rvfi_mode,
465 .rvfi_ixl,
466 .rvfi_rs1_addr,
467 .rvfi_rs2_addr,
468 .rvfi_rs3_addr,
469 .rvfi_rs1_rdata,
470 .rvfi_rs2_rdata,
471 .rvfi_rs3_rdata,
472 .rvfi_rd_addr,
473 .rvfi_rd_wdata,
474 .rvfi_pc_rdata,
475 .rvfi_pc_wdata,
476 .rvfi_mem_addr,
477 .rvfi_mem_rmask,
478 .rvfi_mem_wmask,
479 .rvfi_mem_rdata,
480 .rvfi_mem_wdata,
481 `endif
482 // SEC_CM: FETCH.CTRL.LC_GATED
483 .fetch_enable_i (fetch_enable),
484 .alert_minor_o (alert_minor),
485 .alert_major_internal_o (alert_major_internal),
486 .alert_major_bus_o (alert_major_bus),
487 .core_sleep_o (core_sleep)
488 );
489
490 logic core_sleep_q;
491 always_ff @(posedge clk_i or negedge rst_ni) begin
492 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
493 1/1 core_sleep_q <= '0;
Tests: T1 T2 T3
494 end else begin
495 1/1 core_sleep_q <= core_sleep;
Tests: T1 T2 T3
496 end
497 end
498
499 prim_buf #(
500 .Width(1)
501 ) u_core_sleeping_buf (
502 .in_i(core_sleep_q),
503 .out_o(pwrmgr_o.core_sleeping)
504 );
505
506
507
508 logic prev_valid;
509 logic [31:0] prev_exception_pc;
510 logic [31:0] prev_exception_addr;
511
512 1/1 assign crash_dump_o.current = crash_dump;
Tests: T1 T2 T3
513 1/1 assign crash_dump_o.prev_valid = prev_valid;
Tests: T260 T261 T262
514 1/1 assign crash_dump_o.prev_exception_pc = prev_exception_pc;
Tests: T260 T261 T262
515 1/1 assign crash_dump_o.prev_exception_addr = prev_exception_addr;
Tests: T260 T261 T262
516
517 always_ff @(posedge clk_i or negedge rst_ni) begin
518 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
519 1/1 prev_valid <= '0;
Tests: T1 T2 T3
520 1/1 prev_exception_pc <= '0;
Tests: T1 T2 T3
521 1/1 prev_exception_addr <= '0;
Tests: T1 T2 T3
522 1/1 end else if (double_fault) begin
Tests: T1 T2 T3
523 1/1 prev_valid <= 1'b1;
Tests: T260 T261 T262
524 1/1 prev_exception_pc <= crash_dump.exception_pc;
Tests: T260 T261 T262
525 1/1 prev_exception_addr <= crash_dump.exception_addr;
Tests: T260 T261 T262
526 end
MISSING_ELSE
527 end
528
529
530 //
531 // Convert ibex data/instruction bus to TL-UL
532 //
533 logic [31:0] instr_addr_trans;
534 rv_core_addr_trans #(
535 .AddrWidth(32),
536 .NumRegions(NumRegions)
537 ) u_ibus_trans (
538 .clk_i,
539 .rst_ni(addr_trans_rst_ni),
540 .region_cfg_i(ibus_region_cfg),
541 .addr_i(instr_addr),
542 .addr_o(instr_addr_trans)
543 );
544
545 logic [6:0] instr_wdata_intg;
546 logic [top_pkg::TL_DW-1:0] unused_data;
547 // tl_adapter_host_i_ibex only reads instruction. a_data is always 0
548 assign {instr_wdata_intg, unused_data} = prim_secded_pkg::prim_secded_inv_39_32_enc('0);
549 // SEC_CM: BUS.INTEGRITY
550 tlul_adapter_host #(
551 .MAX_REQS(NumOutstandingReqs),
552 // if secure ibex is not set, data integrity is not generated
553 // from ibex, therefore generate it in the gasket instead.
554 .EnableDataIntgGen(~SecureIbex)
555 ) tl_adapter_host_i_ibex (
556 .clk_i,
557 .rst_ni,
558 .req_i (instr_req),
559 .instr_type_i (prim_mubi_pkg::MuBi4True),
560 .gnt_o (instr_gnt),
561 .addr_i (instr_addr_trans),
562 .we_i (1'b0),
563 .wdata_i (32'b0),
564 .wdata_intg_i (instr_wdata_intg),
565 .be_i (4'hF),
566 .valid_o (instr_rvalid),
567 .rdata_o (instr_rdata),
568 .rdata_intg_o (instr_rdata_intg),
569 .err_o (instr_err),
570 .intg_err_o (ibus_intg_err),
571 .tl_o (tl_i_ibex2fifo),
572 .tl_i (tl_i_fifo2ibex)
573 );
574
575 tlul_fifo_sync #(
576 .ReqPass(FifoPass),
577 .RspPass(FifoPass),
578 .ReqDepth(FifoDepth),
579 .RspDepth(FifoDepth)
580 ) fifo_i (
581 .clk_i,
582 .rst_ni,
583 .tl_h_i (tl_i_ibex2fifo),
584 .tl_h_o (tl_i_fifo2ibex),
585 .tl_d_o (corei_tl_h_o),
586 .tl_d_i (corei_tl_h_i),
587 .spare_req_i (1'b0),
588 .spare_req_o (),
589 .spare_rsp_i (1'b0),
590 .spare_rsp_o ());
591
592 logic [31:0] data_addr_trans;
593 rv_core_addr_trans #(
594 .AddrWidth(32),
595 .NumRegions(NumRegions)
596 ) u_dbus_trans (
597 .clk_i,
598 .rst_ni(addr_trans_rst_ni),
599 .region_cfg_i(dbus_region_cfg),
600 .addr_i(data_addr),
601 .addr_o(data_addr_trans)
602 );
603
604 // SEC_CM: BUS.INTEGRITY
605 tlul_adapter_host #(
606 .MAX_REQS(2),
607 .EnableDataIntgGen(~SecureIbex)
608 ) tl_adapter_host_d_ibex (
609 .clk_i,
610 .rst_ni,
611 .req_i (data_req),
612 .instr_type_i (prim_mubi_pkg::MuBi4False),
613 .gnt_o (data_gnt),
614 .addr_i (data_addr_trans),
615 .we_i (data_we),
616 .wdata_i (data_wdata),
617 .wdata_intg_i (data_wdata_intg),
618 .be_i (data_be),
619 .valid_o (data_rvalid),
620 .rdata_o (data_rdata),
621 .rdata_intg_o (data_rdata_intg),
622 .err_o (data_err),
623 .intg_err_o (dbus_intg_err),
624 .tl_o (tl_d_ibex2fifo),
625 .tl_i (tl_d_fifo2ibex)
626 );
627
628 tlul_fifo_sync #(
629 .ReqPass(FifoPass),
630 .RspPass(FifoPass),
631 .ReqDepth(FifoDepth),
632 .RspDepth(FifoDepth)
633 ) fifo_d (
634 .clk_i,
635 .rst_ni,
636 .tl_h_i (tl_d_ibex2fifo),
637 .tl_h_o (tl_d_fifo2ibex),
638 .tl_d_o (cored_tl_h_o),
639 .tl_d_i (cored_tl_h_i),
640 .spare_req_i (1'b0),
641 .spare_req_o (),
642 .spare_rsp_i (1'b0),
643 .spare_rsp_o ());
644
645 `ifdef RVFI
646 ibex_tracer ibex_tracer_i (
647 .clk_i,
648 .rst_ni,
649
650 .hart_id_i,
651
652 .rvfi_valid,
653 .rvfi_order,
654 .rvfi_insn,
655 .rvfi_trap,
656 .rvfi_halt,
657 .rvfi_intr,
658 .rvfi_mode,
659 .rvfi_ixl,
660 .rvfi_rs1_addr,
661 .rvfi_rs2_addr,
662 .rvfi_rs3_addr,
663 .rvfi_rs1_rdata,
664 .rvfi_rs2_rdata,
665 .rvfi_rs3_rdata,
666 .rvfi_rd_addr,
667 .rvfi_rd_wdata,
668 .rvfi_pc_rdata,
669 .rvfi_pc_wdata,
670 .rvfi_mem_addr,
671 .rvfi_mem_rmask,
672 .rvfi_mem_wmask,
673 .rvfi_mem_rdata,
674 .rvfi_mem_wdata
675 );
676 `endif
677
678 //////////////////////////////////
679 // Peripheral functions
680 //////////////////////////////////
681
682 logic intg_err;
683 tlul_pkg::tl_h2d_t tl_win_h2d;
684 tlul_pkg::tl_d2h_t tl_win_d2h;
685 rv_core_ibex_cfg_reg_top u_reg_cfg (
686 .clk_i,
687 .rst_ni,
688 .tl_i(cfg_tl_d_i),
689 .tl_o(cfg_tl_d_o),
690 .reg2hw,
691 .hw2reg,
692 .intg_err_o (intg_err),
693 .tl_win_o(tl_win_h2d),
694 .tl_win_i(tl_win_d2h)
695 );
696
697 ///////////////////////
698 // Region assignments
699 ///////////////////////
700
701 for(genvar i = 0; i < NumRegions; i++) begin : gen_ibus_region_cfgs
702 2/2 assign ibus_region_cfg[i].en = reg2hw.ibus_addr_en[i];
Tests: T214 T215 T263 | T214 T215 T263
703 2/2 assign ibus_region_cfg[i].matching_region = reg2hw.ibus_addr_matching[i];
Tests: T214 T215 T263 | T214 T215 T263
704 2/2 assign ibus_region_cfg[i].remap_addr = reg2hw.ibus_remap_addr[i];
Tests: T214 T215 T263 | T214 T215 T263
705 end
706
707 for(genvar i = 0; i < NumRegions; i++) begin : gen_dbus_region_cfgs
708 2/2 assign dbus_region_cfg[i].en = reg2hw.dbus_addr_en[i];
Tests: T214 T215 T263 | T214 T215 T263
709 2/2 assign dbus_region_cfg[i].matching_region = reg2hw.dbus_addr_matching[i];
Tests: T214 T215 T263 | T214 T215 T263
710 2/2 assign dbus_region_cfg[i].remap_addr = reg2hw.dbus_remap_addr[i];
Tests: T214 T215 T263 | T214 T215 T263
711 end
712
713 ///////////////////////
714 // Error assignment
715 ///////////////////////
716
717 1/1 assign fatal_intg_err = fatal_intg_event;
Tests: T1 T2 T3
718 1/1 assign fatal_core_err = fatal_core_event;
Tests: T1 T2 T3
719 1/1 assign recov_core_err = recov_core_event;
Tests: T2 T3 T4
720
721 assign hw2reg.err_status.reg_intg_err.d = 1'b1;
722 1/1 assign hw2reg.err_status.reg_intg_err.de = intg_err;
Tests: T1 T2 T3
723 assign hw2reg.err_status.fatal_intg_err.d = 1'b1;
724 1/1 assign hw2reg.err_status.fatal_intg_err.de = fatal_intg_err;
Tests: T1 T2 T3
725 assign hw2reg.err_status.fatal_core_err.d = 1'b1;
726 1/1 assign hw2reg.err_status.fatal_core_err.de = fatal_core_err;
Tests: T1 T2 T3
727 assign hw2reg.err_status.recov_core_err.d = 1'b1;
728 1/1 assign hw2reg.err_status.recov_core_err.de = recov_core_err;
Tests: T2 T3 T4
729
730 ///////////////////////
731 // Alert generation
732 ///////////////////////
733
734 logic [NumAlerts-1:0] alert_test;
735 1/1 assign alert_test[0] = reg2hw.alert_test.fatal_sw_err.q &
Tests: T1 T2 T3
736 reg2hw.alert_test.fatal_sw_err.qe;
737 1/1 assign alert_test[1] = reg2hw.alert_test.recov_sw_err.q &
Tests: T1 T2 T3
738 reg2hw.alert_test.recov_sw_err.qe;
739 1/1 assign alert_test[2] = reg2hw.alert_test.fatal_hw_err.q &
Tests: T1 T2 T3
740 reg2hw.alert_test.fatal_hw_err.qe;
741 1/1 assign alert_test[3] = reg2hw.alert_test.recov_hw_err.q &
Tests: T1 T2 T3
742 reg2hw.alert_test.recov_hw_err.qe;
743
744 localparam bit [NumAlerts-1:0] AlertFatal = '{1'b0, 1'b1, 1'b0, 1'b1};
745
746 logic [NumAlerts-1:0] alert_events;
747 logic [NumAlerts-1:0] alert_acks;
748
749 import prim_mubi_pkg::mubi4_test_true_loose;
750 import prim_mubi_pkg::mubi4_t;
751 1/1 assign alert_events[0] = mubi4_test_true_loose(mubi4_t'(reg2hw.sw_fatal_err.q));
Tests: T264 T265 T266
752 1/1 assign alert_events[1] = mubi4_test_true_loose(mubi4_t'(reg2hw.sw_recov_err.q));
Tests: T68
753 1/1 assign alert_events[2] = intg_err | fatal_intg_err | fatal_core_err;
Tests: T1 T2 T3
754 1/1 assign alert_events[3] = recov_core_err;
Tests: T2 T3 T4
755
756 logic unused_alert_acks;
757 1/1 assign unused_alert_acks = |alert_acks;
Tests: T82 T216 T260
758
759 // recoverable alerts are sent once and silenced until activated again.
760 1/1 assign hw2reg.sw_recov_err.de = alert_acks[1];
Tests: T68
761 assign hw2reg.sw_recov_err.d = prim_mubi_pkg::MuBi4False;
762
763 for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_senders
764 prim_alert_sender #(
765 .AsyncOn(AlertAsyncOn[0]),
766 .IsFatal(AlertFatal[i])
767 ) u_alert_sender (
768 .clk_i,
769 .rst_ni,
770 .alert_test_i(alert_test[i]),
771 .alert_req_i(alert_events[i]),
772 .alert_ack_o(alert_acks[i]),
773 .alert_state_o(),
774 .alert_rx_i(alert_rx_i[i]),
775 .alert_tx_o(alert_tx_o[i])
776 );
777 end
778
779 //////////////
780 // RND Data //
781 //////////////
782
783 logic [31:0] rnd_data_q, rnd_data_d;
784 logic rnd_valid_q, rnd_valid_d;
785 logic rnd_fips_q, rnd_fips_d;
786 logic edn_req;
787 logic [31:0] edn_data;
788 logic edn_ack;
789 logic edn_fips;
790
791 always_comb begin
792 1/1 rnd_valid_d = rnd_valid_q;
Tests: T2 T3 T4
793 1/1 rnd_data_d = rnd_data_q;
Tests: T2 T3 T4
794 1/1 rnd_fips_d = rnd_fips_q;
Tests: T2 T3 T4
795
796 1/1 if (reg2hw.rnd_data.re) begin
Tests: T2 T3 T4
797 1/1 rnd_valid_d = '0;
Tests: T2 T4 T5
798 1/1 rnd_data_d = '0;
Tests: T2 T4 T5
799 1/1 rnd_fips_d = '0;
Tests: T2 T4 T5
800 1/1 end else if (edn_req && edn_ack) begin
Tests: T2 T3 T4
801 1/1 rnd_valid_d = 1'b1;
Tests: T2 T3 T4
802 1/1 rnd_data_d = edn_data;
Tests: T2 T3 T4
803 1/1 rnd_fips_d = edn_fips;
Tests: T2 T3 T4
804 end
MISSING_ELSE
805 end
806
807 always_ff @(posedge clk_i or negedge rst_ni) begin
808 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
809 1/1 rnd_valid_q <= '0;
Tests: T1 T2 T3
810 1/1 rnd_data_q <= '0;
Tests: T1 T2 T3
811 1/1 rnd_fips_q <= '0;
Tests: T1 T2 T3
812 end else begin
813 1/1 rnd_valid_q <= rnd_valid_d;
Tests: T1 T2 T3
814 1/1 rnd_data_q <= rnd_data_d;
Tests: T1 T2 T3
815 1/1 rnd_fips_q <= rnd_fips_d;
Tests: T1 T2 T3
816 end
817 end
818
819 1/1 assign edn_req = ~rnd_valid_q;
Tests: T2 T3 T4
820
821 prim_edn_req #(
822 .OutWidth(32)
823 ) u_edn_if (
824 .clk_i,
825 .rst_ni,
826 .req_chk_i(1'b1),
827 .req_i(edn_req),
828 .ack_o(edn_ack),
829 .data_o(edn_data),
830 .fips_o(edn_fips),
831 .err_o(),
832 .clk_edn_i,
833 .rst_edn_ni,
834 .edn_o,
835 .edn_i
836 );
837
838 1/1 assign hw2reg.rnd_data.d = rnd_data_q;
Tests: T2 T3 T4
839 1/1 assign hw2reg.rnd_status.rnd_data_valid.d = rnd_valid_q;
Tests: T2 T3 T4
840 1/1 assign hw2reg.rnd_status.rnd_data_fips.d = rnd_fips_q;
Tests: T157 T267 T145
841
842 logic unused_reg2hw;
843 0/1 ==> assign unused_reg2hw = |reg2hw.rnd_data.q;
844
845
846 // fpga build info hook-up
847 unreachable assign hw2reg.fpga_info.d = fpga_info_i;
848
849 /////////////////////////////////////
850 // The carved out space is for DV emulation purposes only
851 /////////////////////////////////////
852
853 import tlul_pkg::tl_h2d_t;
854 import tlul_pkg::tl_d2h_t;
855 localparam int TlH2DWidth = $bits(tl_h2d_t);
856 localparam int TlD2HWidth = $bits(tl_d2h_t);
857
858 logic [TlH2DWidth-1:0] tl_win_h2d_int;
859 logic [TlD2HWidth-1:0] tl_win_d2h_int;
860 tl_d2h_t tl_win_d2h_err_rsp;
861
862 prim_buf #(
863 .Width(TlH2DWidth)
864 ) u_tlul_req_buf (
865 .in_i(tl_win_h2d),
866 .out_o(tl_win_h2d_int)
867 );
868
869 prim_buf #(
870 .Width(TlD2HWidth)
871 ) u_tlul_rsp_buf (
872 .in_i(tl_win_d2h_err_rsp),
873 .out_o(tl_win_d2h_int)
874 );
875
876 // Interception point for connecting simulation SRAM by disconnecting the tl_d output. The
877 // disconnection is done only if `SYNTHESIS is NOT defined AND `RV_CORE_IBEX_SIM_SRAM is
878 // defined.
879 // This define is used only for verilator as verilator does not support forces.
880 `ifdef RV_CORE_IBEX_SIM_SRAM
881 `ifdef SYNTHESIS
882 // Induce a compilation error by instantiating a non-existent module.
883 illegal_preprocessor_branch_taken u_illegal_preprocessor_branch_taken();
884 `endif
885 `else
886 1/1 assign tl_win_d2h = tl_d2h_t'(tl_win_d2h_int);
Tests: T1 T2 T3
887 `endif
888
889 tlul_err_resp u_sim_win_rsp (
890 .clk_i,
891 .rst_ni,
892 .tl_h_i(tl_h2d_t'(tl_win_h2d_int)),
893 .tl_h_o(tl_win_d2h_err_rsp)
894 );
895
896 // Assertions for CPU enable
897 // Allow 2 or 3 cycles for input to enable due to synchronizers
898 `ASSERT(FpvSecCmIbexFetchEnable0_A,
899 fatal_core_err
900 |=>
901 lc_ctrl_pkg::lc_tx_test_false_loose(fetch_enable))
902 `ASSERT(FpvSecCmIbexFetchEnable1_A,
903 lc_ctrl_pkg::lc_tx_test_false_loose(lc_cpu_en_i)
904 |->
905 ##[2:3] lc_ctrl_pkg::lc_tx_test_false_loose(fetch_enable))
906 `ASSERT(FpvSecCmIbexFetchEnable2_A,
907 lc_ctrl_pkg::lc_tx_test_false_loose(pwrmgr_cpu_en_i)
908 |->
909 ##[2:3] lc_ctrl_pkg::lc_tx_test_false_loose(fetch_enable))
910 `ASSERT(FpvSecCmIbexFetchEnable3_A,
911 lc_ctrl_pkg::lc_tx_test_true_strict(lc_cpu_en_i) &&
912 lc_ctrl_pkg::lc_tx_test_true_strict(pwrmgr_cpu_en_i) ##1
913 lc_ctrl_pkg::lc_tx_test_true_strict(local_fetch_enable_q) &&
914 !fatal_core_err
915 |=>
916 ##[0:1] lc_ctrl_pkg::lc_tx_test_true_strict(fetch_enable))
917 `ASSERT(FpvSecCmIbexFetchEnable3Rev_A,
918 ##2 lc_ctrl_pkg::lc_tx_test_true_strict(fetch_enable)
919 |->
920 ($past(lc_ctrl_pkg::lc_tx_test_true_strict(lc_cpu_en_i), 2) ||
921 $past(lc_ctrl_pkg::lc_tx_test_true_strict(lc_cpu_en_i), 3)) &&
922 ($past(lc_ctrl_pkg::lc_tx_test_true_strict(pwrmgr_cpu_en_i), 2) ||
923 $past(lc_ctrl_pkg::lc_tx_test_true_strict(pwrmgr_cpu_en_i), 3)) &&
924 $past(!fatal_core_err))
925
926 // Alert assertions for reg_we onehot check
927 `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegWeOnehotCheck_A, u_reg_cfg, alert_tx_o[2])
928 `ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ALERT(RvCoreRegWeOnehotCheck_A,
929 u_core.gen_regfile_ff.register_file_i.gen_wren_check.u_prim_onehot_check, alert_tx_o[2])
930 `ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ALERT(RvCoreRegWeOnehotCheckRAddrA_A,
931 u_core.gen_regfile_ff.register_file_i.gen_rdata_mux_check.u_prim_onehot_check_raddr_a,
932 alert_tx_o[2])
933 `ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ALERT(RvCoreRegWeOnehotCheckRAddrB_A,
934 u_core.gen_regfile_ff.register_file_i.gen_rdata_mux_check.u_prim_onehot_check_raddr_b,
935 alert_tx_o[2])
936
937 `ifdef INC_ASSERT
938 if (ICache && ICacheScramble) begin : gen_icache_scramble_asserts
939
940 // Sample icache scramble key for use in assertions below.
941 // pragma coverage off
942 //VCS coverage off
943 logic [otp_ctrl_pkg::FlashKeyWidth-1:0] icache_otp_key_q;
944 always_ff @(posedge clk_i, negedge rst_ni) begin
945 unreachable if (!rst_ni) begin
946 unreachable icache_otp_key_q <= '0;
947 unreachable end else if (icache_otp_key_i.ack) begin
948 unreachable icache_otp_key_q <= icache_otp_key_i.key;
949 end
==> MISSING_ELSE
950 end
951 //VCS coverage on
952 // pragma coverage on
953
954 // Ensure that when a scramble key is received, it is correctly forwarded to the core. The core
955 // will then internally ensure that the key is correctly applied to the icache scrambled
956 // memory primitives.
957 `ASSERT(IbexIcacheScrambleKeyForwardedToCore_A,
958 icache_otp_key_i.ack
959 |-> ##[0:10] // upper bound is not exact, but it should not take more than 10 cycles
960 u_core.scramble_key_valid_i && (u_core.scramble_key_i == icache_otp_key_q)
961 )
962
963 // Ensure that when a FENCE.I is executed, a new icache scramble key is requested.
964 `ASSERT(IbexIcacheScrambleKeyRequestAfterFenceI_A,
965 u_core.u_ibex_core.id_stage_i.instr_valid_i
966 && u_core.u_ibex_core.id_stage_i.decoder_i.opcode == ibex_pkg::OPCODE_MISC_MEM
967 && u_core.u_ibex_core.id_stage_i.decoder_i.instr[14:12] == 3'b001 // FENCE.I
968 |-> ##[0:14] // upper bound is not exact, but it should not take more than a few cycles
969 icache_otp_key_o.req
970 )
971
972 end
973
974 `define ASSERT_IBEX_CORE_ERROR_TRIGGER_ALERT(__assert_name, __alert_name, _hier, __error_name) \
975 if (1) begin : g_``__error_name``_assert_signals \
976 logic __error_name; \
977 assign __error_name = u_core._hier``.__error_name; \
978 \
979 logic unused_assert_connected; \
980 `ASSERT_INIT_NET(AssertConnected_A, unused_assert_connected === 1'b1) \
981 end \
982 `ASSERT_ERROR_TRIGGER_ALERT(__assert_name, g_``__error_name``_assert_signals, __alert_name, 0, \
983 30, // MAX_CYCLES_, use a large value as ibex clock is 4x faster than clk in alert_handler \
984 __error_name)
985
986 0/1 ==> `ASSERT_IBEX_CORE_ERROR_TRIGGER_ALERT(IbexPcMismatchCheck_A, alert_tx_o[2],
ASSERT_IBEX_CORE_ERROR_TRIGGER_ALERT(IbexPcMism:
986.1 if (1) begin : g_pc_mismatch_alert_o_assert_signals
986.2 logic pc_mismatch_alert_o;
986.3 0/1 ==> assign pc_mismatch_alert_o = u_core.u_ibex_core.if_stage_i.pc_mismatch_alert_o;
986.4
986.5 logic unused_assert_connected;
986.6 initial begin
986.7
986.8
986.9
986.10 #1ps;
986.11 AssertConnected_A: assert (unused_assert_connected === 1'b1)
986.12 else begin
986.13 `ifdef UVM
986.14 uvm_pkg::uvm_report_error("ASSERT FAILED", "AssertConnected_A", uvm_pkg::UVM_NONE,
986.15 "../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv", 986, "", 1);
986.16 `else
986.17 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
986.18 `PRIM_STRINGIFY(AssertConnected_A));
986.19 `endif
986.20 end
986.21 end
986.22
986.23 end
986.24 FpvSecCmIbexPcMismatchCheck_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) ($rose(g_pc_mismatch_alert_o_assert_signals.pc_mismatch_alert_o) && !(0) |-> ##[0:30] ((alert_tx_o[2].alert_p))))
986.25 else begin
986.26 `ifdef UVM
986.27 uvm_pkg::uvm_report_error("ASSERT FAILED", "FpvSecCmIbexPcMismatchCheck_A", uvm_pkg::UVM_NONE,
986.28 "../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv", 986, "", 1);
986.29 `else
986.30 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
986.31 `PRIM_STRINGIFY(FpvSecCmIbexPcMismatchCheck_A));
986.32 `endif
986.33 end
986.34 `ifdef INC_ASSERT
986.35 assign g_pc_mismatch_alert_o_assert_signals.unused_assert_connected = 1'b1;
986.36 `endif
986.37 `ifdef FPV_ON
986.38 `ASSUME(IbexPcMismatchCheck_ATriggerAfterAlertInit_S, $stable(rst_ni) == 0 |-> g_pc_mismatch_alert_o_assert_signals.pc_mismatch_alert_o == 0 [*10], `ASSERT_DEFAULT_CLK, `ASSERT_DEFAULT_RST)
986.39 `endif987 u_ibex_core.if_stage_i, pc_mismatch_alert_o)
988 0/1 ==> `ASSERT_IBEX_CORE_ERROR_TRIGGER_ALERT(IbexRfEccErrCheck_A, alert_tx_o[2], u_ibex_core,
ASSERT_IBEX_CORE_ER:
988.1 if (1) begin : g_rf_ecc_err_comb_assert_signals
988.2 logic rf_ecc_err_comb;
988.3 0/1 ==> assign rf_ecc_err_comb = u_core.u_ibex_core.rf_ecc_err_comb;
988.4
988.5 logic unused_assert_connected;
988.6 initial begin
988.7
988.8
988.9
988.10 #1ps;
988.11 AssertConnected_A: assert (unused_assert_connected === 1'b1)
988.12 else begin
988.13 `ifdef UVM
988.14 uvm_pkg::uvm_report_error("ASSERT FAILED", "AssertConnected_A", uvm_pkg::UVM_NONE,
988.15 "../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv", 988, "", 1);
988.16 `else
988.17 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
988.18 `PRIM_STRINGIFY(AssertConnected_A));
988.19 `endif
988.20 end
988.21 end
988.22
988.23 end
988.24 FpvSecCmIbexRfEccErrCheck_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) ($rose(g_rf_ecc_err_comb_assert_signals.rf_ecc_err_comb) && !(0) |-> ##[0:30] ((alert_tx_o[2].alert_p))))
988.25 else begin
988.26 `ifdef UVM
988.27 uvm_pkg::uvm_report_error("ASSERT FAILED", "FpvSecCmIbexRfEccErrCheck_A", uvm_pkg::UVM_NONE,
988.28 "../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv", 988, "", 1);
988.29 `else
988.30 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
988.31 `PRIM_STRINGIFY(FpvSecCmIbexRfEccErrCheck_A));
988.32 `endif
988.33 end
988.34 `ifdef INC_ASSERT
988.35 assign g_rf_ecc_err_comb_assert_signals.unused_assert_connected = 1'b1;
988.36 `endif
988.37 `ifdef FPV_ON
988.38 `ASSUME(IbexRfEccErrCheck_ATriggerAfterAlertInit_S, $stable(rst_ni) == 0 |-> g_rf_ecc_err_comb_assert_signals.rf_ecc_err_comb == 0 [*10], `ASSERT_DEFAULT_CLK, `ASSERT_DEFAULT_RST)
988.39 `endif989 rf_ecc_err_comb)
990 1/1 `ASSERT_IBEX_CORE_ERROR_TRIGGER_ALERT(IbexLoadRespIntgErrCheck_A, alert_tx_o[2], u_ibex_core,
Tests: T1 T2 T3
ASSERT_IBEX_CORE_ERROR_TRI:
990.1 if (1) begin : g_lsu_load_resp_intg_err_assert_signals
990.2 logic lsu_load_resp_intg_err;
990.3 1/1 assign lsu_load_resp_intg_err = u_core.u_ibex_core.lsu_load_resp_intg_err;
Tests: T1 T2 T3
990.4
990.5 logic unused_assert_connected;
990.6 initial begin
990.7
990.8
990.9
990.10 #1ps;
990.11 AssertConnected_A: assert (unused_assert_connected === 1'b1)
990.12 else begin
990.13 `ifdef UVM
990.14 uvm_pkg::uvm_report_error("ASSERT FAILED", "AssertConnected_A", uvm_pkg::UVM_NONE,
990.15 "../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv", 990, "", 1);
990.16 `else
990.17 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
990.18 `PRIM_STRINGIFY(AssertConnected_A));
990.19 `endif
990.20 end
990.21 end
990.22
990.23 end
990.24 FpvSecCmIbexLoadRespIntgErrCheck_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) ($rose(g_lsu_load_resp_intg_err_assert_signals.lsu_load_resp_intg_err) && !(0) |-> ##[0:30] ((alert_tx_o[2].alert_p))))
990.25 else begin
990.26 `ifdef UVM
990.27 uvm_pkg::uvm_report_error("ASSERT FAILED", "FpvSecCmIbexLoadRespIntgErrCheck_A", uvm_pkg::UVM_NONE,
990.28 "../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv", 990, "", 1);
990.29 `else
990.30 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
990.31 `PRIM_STRINGIFY(FpvSecCmIbexLoadRespIntgErrCheck_A));
990.32 `endif
990.33 end
990.34 `ifdef INC_ASSERT
990.35 assign g_lsu_load_resp_intg_err_assert_signals.unused_assert_connected = 1'b1;
990.36 `endif
990.37 `ifdef FPV_ON
990.38 `ASSUME(IbexLoadRespIntgErrCheck_ATriggerAfterAlertInit_S, $stable(rst_ni) == 0 |-> g_lsu_load_resp_intg_err_assert_signals.lsu_load_resp_intg_err == 0 [*10], `ASSERT_DEFAULT_CLK, `ASSERT_DEFAULT_RST)
990.39 `endif991 lsu_load_resp_intg_err)
992 1/1 `ASSERT_IBEX_CORE_ERROR_TRIGGER_ALERT(IbexStoreRespIntgErrCheck_A, alert_tx_o[2], u_ibex_core,
Tests: T1 T2 T3
ASSERT_IBEX_CORE_ERROR_TRIG:
992.1 if (1) begin : g_lsu_store_resp_intg_err_assert_signals
992.2 logic lsu_store_resp_intg_err;
992.3 1/1 assign lsu_store_resp_intg_err = u_core.u_ibex_core.lsu_store_resp_intg_err;
Tests: T1 T2 T3
992.4
992.5 logic unused_assert_connected;
992.6 initial begin
992.7
992.8
992.9
992.10 #1ps;
992.11 AssertConnected_A: assert (unused_assert_connected === 1'b1)
992.12 else begin
992.13 `ifdef UVM
992.14 uvm_pkg::uvm_report_error("ASSERT FAILED", "AssertConnected_A", uvm_pkg::UVM_NONE,
992.15 "../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv", 992, "", 1);
992.16 `else
992.17 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
992.18 `PRIM_STRINGIFY(AssertConnected_A));
992.19 `endif
992.20 end
992.21 end
992.22
992.23 end
992.24 FpvSecCmIbexStoreRespIntgErrCheck_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) ($rose(g_lsu_store_resp_intg_err_assert_signals.lsu_store_resp_intg_err) && !(0) |-> ##[0:30] ((alert_tx_o[2].alert_p))))
992.25 else begin
992.26 `ifdef UVM
992.27 uvm_pkg::uvm_report_error("ASSERT FAILED", "FpvSecCmIbexStoreRespIntgErrCheck_A", uvm_pkg::UVM_NONE,
992.28 "../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv", 992, "", 1);
992.29 `else
992.30 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
992.31 `PRIM_STRINGIFY(FpvSecCmIbexStoreRespIntgErrCheck_A));
992.32 `endif
992.33 end
992.34 `ifdef INC_ASSERT
992.35 assign g_lsu_store_resp_intg_err_assert_signals.unused_assert_connected = 1'b1;
992.36 `endif
992.37 `ifdef FPV_ON
992.38 `ASSUME(IbexStoreRespIntgErrCheck_ATriggerAfterAlertInit_S, $stable(rst_ni) == 0 |-> g_lsu_store_resp_intg_err_assert_signals.lsu_store_resp_intg_err == 0 [*10], `ASSERT_DEFAULT_CLK, `ASSERT_DEFAULT_RST)
992.39 `endif993 lsu_store_resp_intg_err)
994 1/1 `ASSERT_IBEX_CORE_ERROR_TRIGGER_ALERT(IbexInstrIntgErrCheck_A, alert_tx_o[2], u_ibex_core,
Tests: T1 T2 T3
ASSERT_IBEX_CORE_E:
994.1 if (1) begin : g_instr_intg_err_assert_signals
994.2 logic instr_intg_err;
994.3 1/1 assign instr_intg_err = u_core.u_ibex_core.instr_intg_err;
Tests: T1 T2 T3
994.4
994.5 logic unused_assert_connected;
994.6 initial begin
994.7
994.8
994.9
994.10 #1ps;
994.11 AssertConnected_A: assert (unused_assert_connected === 1'b1)
994.12 else begin
994.13 `ifdef UVM
994.14 uvm_pkg::uvm_report_error("ASSERT FAILED", "AssertConnected_A", uvm_pkg::UVM_NONE,
994.15 "../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv", 994, "", 1);
994.16 `else
994.17 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
994.18 `PRIM_STRINGIFY(AssertConnected_A));
994.19 `endif
994.20 end
994.21 end
994.22
994.23 end
994.24 FpvSecCmIbexInstrIntgErrCheck_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) ($rose(g_instr_intg_err_assert_signals.instr_intg_err) && !(0) |-> ##[0:30] ((alert_tx_o[2].alert_p))))
994.25 else begin
994.26 `ifdef UVM
994.27 uvm_pkg::uvm_report_error("ASSERT FAILED", "FpvSecCmIbexInstrIntgErrCheck_A", uvm_pkg::UVM_NONE,
994.28 "../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv", 994, "", 1);
994.29 `else
994.30 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
994.31 `PRIM_STRINGIFY(FpvSecCmIbexInstrIntgErrCheck_A));
994.32 `endif
994.33 end
994.34 `ifdef INC_ASSERT
994.35 assign g_instr_intg_err_assert_signals.unused_assert_connected = 1'b1;
994.36 `endif
994.37 `ifdef FPV_ON
994.38 `ASSUME(IbexInstrIntgErrCheck_ATriggerAfterAlertInit_S, $stable(rst_ni) == 0 |-> g_instr_intg_err_assert_signals.instr_intg_err == 0 [*10], `ASSERT_DEFAULT_CLK, `ASSERT_DEFAULT_RST)
994.39 `endif
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex
| Total | Covered | Percent |
|---|
| Conditions | 28 | 25 | 89.29 |
| Logical | 28 | 25 | 89.29 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 216
EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
------1------ ------2------ -------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T82,T216,T209 |
| 0 | 1 | 0 | Not Covered | |
| 1 | 0 | 0 | Not Covered | |
LINE 217
EXPRESSION (alert_major_internal | double_fault)
----------1--------- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T260,T261,T262 |
| 1 | 0 | Covered | T164,T268,T226 |
LINE 348
EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T164,T260,T268 |
LINE 735
EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
----------------1--------------- ----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T75,T226,T192 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T75,T76,T77 |
LINE 737
EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
----------------1--------------- ----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T75,T76,T77 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T75,T226,T192 |
LINE 739
EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
----------------1--------------- ----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T75,T226,T192 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T75,T76,T77 |
LINE 741
EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
----------------1--------------- ----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T75,T226,T192 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T75,T76,T77 |
LINE 753
EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
----1--- -------2------ -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T164,T260,T268 |
| 0 | 1 | 0 | Covered | T82,T216,T209 |
| 1 | 0 | 0 | Covered | T269,T115,T270 |
LINE 800
EXPRESSION (edn_req && edn_ack)
---1--- ---2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T2,T4,T5 |
| 1 | 1 | Covered | T2,T3,T4 |
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex
| Total | Covered | Percent |
| Totals |
119 |
117 |
98.32 |
| Total Bits |
1608 |
1604 |
99.75 |
| Total Bits 0->1 |
804 |
802 |
99.75 |
| Total Bits 1->0 |
804 |
802 |
99.75 |
| | | |
| Ports |
119 |
117 |
98.32 |
| Port Bits |
1608 |
1604 |
99.75 |
| Port Bits 0->1 |
804 |
802 |
99.75 |
| Port Bits 1->0 |
804 |
802 |
99.75 |
Port Details
| Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction | Exclude Annotation |
| clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
| rst_ni |
Yes |
Yes |
T30,T36,T42 |
Yes |
T1,T2,T3 |
INPUT |
|
| clk_edn_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
| rst_edn_ni |
Yes |
Yes |
T30,T36,T42 |
Yes |
T1,T2,T3 |
INPUT |
|
| clk_esc_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
| rst_esc_ni |
Yes |
Yes |
T30,T36,T42 |
Yes |
T1,T2,T3 |
INPUT |
|
| rst_cpu_n_o |
Yes |
Yes |
T30,T36,T42 |
Yes |
T1,T2,T3 |
OUTPUT |
|
| ram_cfg_i.rf_cfg.cfg[3:0] |
Excluded |
Excluded |
|
Excluded |
|
INPUT |
[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv |
| ram_cfg_i.rf_cfg.cfg_en[0:0] |
Excluded |
Excluded |
|
Excluded |
|
INPUT |
[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv |
| ram_cfg_i.rf_cfg.test |
No |
No |
|
No |
|
INPUT |
|
| ram_cfg_i.ram_cfg.cfg[3:0] |
Excluded |
Excluded |
|
Excluded |
|
INPUT |
[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv |
| ram_cfg_i.ram_cfg.cfg_en[0:0] |
Excluded |
Excluded |
|
Excluded |
|
INPUT |
[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv |
| ram_cfg_i.ram_cfg.test |
No |
No |
|
No |
|
INPUT |
|
| hart_id_i[31:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
|
| boot_addr_i[31:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
|
| corei_tl_h_o.d_ready |
Yes |
Yes |
T162,T271,T272 |
Yes |
T95,T96,T97 |
OUTPUT |
|
| corei_tl_h_o.a_user.data_intg[6:0] |
Yes |
Yes |
T95,T96,T97 |
Yes |
T95,T96,T97 |
OUTPUT |
|
| corei_tl_h_o.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
|
| corei_tl_h_o.a_user.instr_type[3:0] |
Yes |
Yes |
T96,T162,T163 |
Yes |
T96,T101,T162 |
OUTPUT |
|
| corei_tl_h_o.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
|
| corei_tl_h_o.a_data[31:0] |
Yes |
Yes |
T95,T96,T97 |
Yes |
T95,T96,T97 |
OUTPUT |
|
| corei_tl_h_o.a_mask[3:0] |
Yes |
Yes |
T95,T96,T97 |
Yes |
T95,T96,T97 |
OUTPUT |
|
| corei_tl_h_o.a_address[31:0] |
Yes |
Yes |
T95,T96,T97 |
Yes |
T95,T96,T97 |
OUTPUT |
|
| corei_tl_h_o.a_source[5:0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
|
| corei_tl_h_o.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
|
| corei_tl_h_o.a_size[1:0] |
Yes |
Yes |
T95,T96,T97 |
Yes |
T95,T96,T97 |
OUTPUT |
|
| corei_tl_h_o.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
|
| corei_tl_h_o.a_opcode[2:0] |
Yes |
Yes |
T95,T96,T97 |
Yes |
T95,T96,T97 |
OUTPUT |
|
| corei_tl_h_o.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
|
| corei_tl_h_i.a_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
| corei_tl_h_i.d_error |
Yes |
Yes |
T42,T212,T98 |
Yes |
T42,T212,T98 |
INPUT |
|
| corei_tl_h_i.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
| corei_tl_h_i.d_user.rsp_intg[6:0] |
Yes |
Yes |
T42,T82,T212 |
Yes |
T42,T82,T212 |
INPUT |
|
| corei_tl_h_i.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
| corei_tl_h_i.d_sink |
Yes |
Yes |
T95,T96,T97 |
Yes |
T95,T96,T97 |
INPUT |
|
| corei_tl_h_i.d_source[5:0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
|
| corei_tl_h_i.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
|
| corei_tl_h_i.d_size[1:0] |
Yes |
Yes |
T95,T96,T97 |
Yes |
T95,T96,T97 |
INPUT |
|
| corei_tl_h_i.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
|
| corei_tl_h_i.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
|
| corei_tl_h_i.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
|
| corei_tl_h_i.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
| cored_tl_h_o.d_ready |
Yes |
Yes |
T35,T99,T100 |
Yes |
T35,T99,T100 |
OUTPUT |
|
| cored_tl_h_o.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
|
| cored_tl_h_o.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
|
| cored_tl_h_o.a_user.instr_type[3:0] |
Yes |
Yes |
T35,T68,T95 |
Yes |
T35,T68,T95 |
OUTPUT |
|
| cored_tl_h_o.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
|
| cored_tl_h_o.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
|
| cored_tl_h_o.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
|
| cored_tl_h_o.a_address[31:0] |
Yes |
Yes |
T35,T68,T95 |
Yes |
T35,T68,T95 |
OUTPUT |
|
| cored_tl_h_o.a_source[5:0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
|
| cored_tl_h_o.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
|
| cored_tl_h_o.a_size[1:0] |
Yes |
Yes |
T35,T68,T95 |
Yes |
T35,T68,T95 |
OUTPUT |
|
| cored_tl_h_o.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
|
| cored_tl_h_o.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
|
| cored_tl_h_o.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
|
| cored_tl_h_i.a_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
| cored_tl_h_i.d_error |
Yes |
Yes |
T42,T82,T208 |
Yes |
T42,T82,T208 |
INPUT |
|
| cored_tl_h_i.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
| cored_tl_h_i.d_user.rsp_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
| cored_tl_h_i.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
| cored_tl_h_i.d_sink |
Yes |
Yes |
T95,T96,T97 |
Yes |
T95,T96,T97 |
INPUT |
|
| cored_tl_h_i.d_source[5:0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
|
| cored_tl_h_i.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
|
| cored_tl_h_i.d_size[1:0] |
Yes |
Yes |
T95,T96,T97 |
Yes |
T95,T96,T97 |
INPUT |
|
| cored_tl_h_i.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
|
| cored_tl_h_i.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
|
| cored_tl_h_i.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
|
| cored_tl_h_i.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
| irq_software_i |
Yes |
Yes |
T273,T274,T275 |
Yes |
T273,T274,T275 |
INPUT |
|
| irq_timer_i |
Yes |
Yes |
T126,T127,T128 |
Yes |
T126,T127,T128 |
INPUT |
|
| irq_external_i |
Yes |
Yes |
T2,T4,T5 |
Yes |
T2,T4,T5 |
INPUT |
|
| esc_tx_i.esc_n |
Yes |
Yes |
T42,T82,T84 |
Yes |
T42,T82,T84 |
INPUT |
|
| esc_tx_i.esc_p |
Yes |
Yes |
T42,T82,T84 |
Yes |
T42,T82,T84 |
INPUT |
|
| esc_rx_o.resp_n |
Yes |
Yes |
T42,T82,T84 |
Yes |
T42,T82,T84 |
OUTPUT |
|
| esc_rx_o.resp_p |
Yes |
Yes |
T42,T82,T84 |
Yes |
T42,T82,T84 |
OUTPUT |
|
| nmi_wdog_i |
Yes |
Yes |
T5,T258,T259 |
Yes |
T5,T258,T259 |
INPUT |
|
| debug_req_i |
Yes |
Yes |
T98,T54,T55 |
Yes |
T98,T54,T55 |
INPUT |
|
| crash_dump_o.current.exception_addr[31:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
|
| crash_dump_o.current.exception_pc[31:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
|
| crash_dump_o.current.last_data_addr[31:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
|
| crash_dump_o.current.next_pc[31:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
|
| crash_dump_o.current.current_pc[31:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
|
| crash_dump_o.prev_exception_addr[31:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
|
| crash_dump_o.prev_exception_pc[31:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
|
| crash_dump_o.prev_valid |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
|
| lc_cpu_en_i[3:0] |
Yes |
Yes |
T42,T37,T43 |
Yes |
T1,T2,T3 |
INPUT |
|
| pwrmgr_cpu_en_i[3:0] |
Yes |
Yes |
T4,T5,T26 |
Yes |
T1,T2,T3 |
INPUT |
|
| pwrmgr_o.core_sleeping |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
|
| scan_rst_ni |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
|
| scanmode_i[3:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
|
| cfg_tl_d_i.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
| cfg_tl_d_i.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
| cfg_tl_d_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
| cfg_tl_d_i.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
| cfg_tl_d_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
|
| cfg_tl_d_i.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
| cfg_tl_d_i.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
| cfg_tl_d_i.a_address[7:0] |
Yes |
Yes |
*T96,*T97,*T101 |
Yes |
T96,T97,T101 |
INPUT |
|
| cfg_tl_d_i.a_address[15:8] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
|
| cfg_tl_d_i.a_address[20:16] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
| cfg_tl_d_i.a_address[23:21] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
|
| cfg_tl_d_i.a_address[24] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
|
| cfg_tl_d_i.a_address[29:25] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
|
| cfg_tl_d_i.a_address[30] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
|
| cfg_tl_d_i.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
|
| cfg_tl_d_i.a_source[5:0] |
Yes |
Yes |
*T54,*T68,*T95 |
Yes |
T54,T68,T95 |
INPUT |
|
| cfg_tl_d_i.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
|
| cfg_tl_d_i.a_size[1:0] |
Yes |
Yes |
T95,T96,T97 |
Yes |
T95,T96,T97 |
INPUT |
|
| cfg_tl_d_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
|
| cfg_tl_d_i.a_opcode[2:0] |
Yes |
Yes |
T95,T96,T97 |
Yes |
T95,T96,T97 |
INPUT |
|
| cfg_tl_d_i.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
| cfg_tl_d_o.a_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
|
| cfg_tl_d_o.d_error |
Yes |
Yes |
T68,T95,T97 |
Yes |
T68,T95,T97 |
OUTPUT |
|
| cfg_tl_d_o.d_user.data_intg[6:0] |
Yes |
Yes |
T2,T4,T5 |
Yes |
T2,T4,T5 |
OUTPUT |
|
| cfg_tl_d_o.d_user.rsp_intg[6:0] |
Yes |
Yes |
T2,T3,T4 |
Yes |
T1,T2,T3 |
OUTPUT |
|
| cfg_tl_d_o.d_data[31:0] |
Yes |
Yes |
T2,T4,T5 |
Yes |
T2,T4,T5 |
OUTPUT |
|
| cfg_tl_d_o.d_sink |
Yes |
Yes |
T95,T96,T97 |
Yes |
T95,T97,T101 |
OUTPUT |
|
| cfg_tl_d_o.d_source[5:0] |
Yes |
Yes |
*T68,*T97,*T162 |
Yes |
T54,T68,T95 |
OUTPUT |
|
| cfg_tl_d_o.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
|
| cfg_tl_d_o.d_size[1:0] |
Yes |
Yes |
T95,T96,T97 |
Yes |
T96,T97,T101 |
OUTPUT |
|
| cfg_tl_d_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
|
| cfg_tl_d_o.d_opcode[0] |
Yes |
Yes |
*T2,*T3,*T4 |
Yes |
T2,T3,T4 |
OUTPUT |
|
| cfg_tl_d_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
|
| cfg_tl_d_o.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
|
| edn_o.edn_req |
Yes |
Yes |
T2,T3,T4 |
Yes |
T1,T2,T3 |
OUTPUT |
|
| edn_i.edn_bus[31:0] |
Yes |
Yes |
T121,T12,T42 |
Yes |
T2,T4,T5 |
INPUT |
|
| edn_i.edn_fips |
Yes |
Yes |
T157,T276,T277 |
Yes |
T157,T267,T145 |
INPUT |
|
| edn_i.edn_ack |
Yes |
Yes |
T2,T3,T4 |
Yes |
T2,T3,T4 |
INPUT |
|
| clk_otp_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
| rst_otp_ni |
Yes |
Yes |
T30,T36,T42 |
Yes |
T1,T2,T3 |
INPUT |
|
| icache_otp_key_o.req |
Yes |
Yes |
T212,T213,T214 |
Yes |
T212,T213,T214 |
OUTPUT |
|
| icache_otp_key_i.seed_valid |
Yes |
Yes |
T42,T37,T43 |
Yes |
T2,T3,T4 |
INPUT |
|
| icache_otp_key_i.nonce[127:0] |
Yes |
Yes |
T4,T105,T6 |
Yes |
T4,T105,T6 |
INPUT |
|
| icache_otp_key_i.key[127:0] |
Yes |
Yes |
T2,T3,T4 |
Yes |
T105,T6,T32 |
INPUT |
|
| icache_otp_key_i.ack |
Yes |
Yes |
T213,T214,T215 |
Yes |
T213,T214,T215 |
INPUT |
|
| fpga_info_i[31:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
|
| alert_rx_i[0].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
| alert_rx_i[0].ack_p |
Yes |
Yes |
T75,T102,T103 |
Yes |
T75,T102,T103 |
INPUT |
|
| alert_rx_i[0].ping_n |
Yes |
Yes |
T102,T103,T104 |
Yes |
T103,T104,T193 |
INPUT |
|
| alert_rx_i[0].ping_p |
Yes |
Yes |
T103,T104,T193 |
Yes |
T102,T103,T104 |
INPUT |
|
| alert_rx_i[1].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
| alert_rx_i[1].ack_p |
Yes |
Yes |
T75,T102,T226 |
Yes |
T75,T102,T226 |
INPUT |
|
| alert_rx_i[1].ping_n |
Yes |
Yes |
T102,T103,T104 |
Yes |
T102,T103,T104 |
INPUT |
|
| alert_rx_i[1].ping_p |
Yes |
Yes |
T102,T103,T104 |
Yes |
T102,T103,T104 |
INPUT |
|
| alert_rx_i[2].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
| alert_rx_i[2].ack_p |
Yes |
Yes |
T82,T216,T260 |
Yes |
T82,T216,T260 |
INPUT |
|
| alert_rx_i[2].ping_n |
Yes |
Yes |
T102,T103,T104 |
Yes |
T102,T103,T104 |
INPUT |
|
| alert_rx_i[2].ping_p |
Yes |
Yes |
T102,T103,T104 |
Yes |
T102,T103,T104 |
INPUT |
|
| alert_rx_i[3].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
| alert_rx_i[3].ack_p |
Yes |
Yes |
T75,T102,T103 |
Yes |
T75,T102,T103 |
INPUT |
|
| alert_rx_i[3].ping_n |
Yes |
Yes |
T102,T103,T104 |
Yes |
T102,T103,T104 |
INPUT |
|
| alert_rx_i[3].ping_p |
Yes |
Yes |
T102,T103,T104 |
Yes |
T102,T103,T104 |
INPUT |
|
| alert_tx_o[0].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
|
| alert_tx_o[0].alert_p |
Yes |
Yes |
T75,T102,T103 |
Yes |
T75,T102,T103 |
OUTPUT |
|
| alert_tx_o[1].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
|
| alert_tx_o[1].alert_p |
Yes |
Yes |
T75,T102,T226 |
Yes |
T75,T102,T226 |
OUTPUT |
|
| alert_tx_o[2].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
|
| alert_tx_o[2].alert_p |
Yes |
Yes |
T82,T216,T260 |
Yes |
T82,T216,T260 |
OUTPUT |
|
| alert_tx_o[3].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
|
| alert_tx_o[3].alert_p |
Yes |
Yes |
T75,T102,T103 |
Yes |
T75,T102,T103 |
OUTPUT |
|
*Tests covering at least one bit in the range
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex
| Line No. | Total | Covered | Percent |
| Branches |
|
12 |
12 |
100.00 |
| TERNARY |
348 |
2 |
2 |
100.00 |
| IF |
492 |
2 |
2 |
100.00 |
| IF |
518 |
3 |
3 |
100.00 |
| IF |
796 |
3 |
3 |
100.00 |
| IF |
808 |
2 |
2 |
100.00 |
348 assign local_fetch_enable_d = fatal_core_err ? lc_ctrl_pkg::Off : local_fetch_enable_q;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T164,T260,T268 |
| 0 |
Covered |
T1,T2,T3 |
492 if (!rst_ni) begin
-1-
493 core_sleep_q <= '0;
==>
494 end else begin
495 core_sleep_q <= core_sleep;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
518 if (!rst_ni) begin
-1-
519 prev_valid <= '0;
==>
520 prev_exception_pc <= '0;
521 prev_exception_addr <= '0;
522 end else if (double_fault) begin
-2-
523 prev_valid <= 1'b1;
==>
524 prev_exception_pc <= crash_dump.exception_pc;
525 prev_exception_addr <= crash_dump.exception_addr;
526 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T260,T261,T262 |
| 0 |
0 |
Covered |
T1,T2,T3 |
796 if (reg2hw.rnd_data.re) begin
-1-
797 rnd_valid_d = '0;
==>
798 rnd_data_d = '0;
799 rnd_fips_d = '0;
800 end else if (edn_req && edn_ack) begin
-2-
801 rnd_valid_d = 1'b1;
==>
802 rnd_data_d = edn_data;
803 rnd_fips_d = edn_fips;
804 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T2,T4,T5 |
| 0 |
1 |
Covered |
T2,T3,T4 |
| 0 |
0 |
Covered |
T2,T3,T4 |
808 if (!rst_ni) begin
-1-
809 rnd_valid_q <= '0;
==>
810 rnd_data_q <= '0;
811 rnd_fips_q <= '0;
812 end else begin
813 rnd_valid_q <= rnd_valid_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex
Assertion Details
FpvSecCmIbexFetchEnable0_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
516490638 |
10 |
0 |
0 |
| T66 |
272702 |
0 |
0 |
0 |
| T75 |
92338 |
0 |
0 |
0 |
| T140 |
153467 |
0 |
0 |
0 |
| T196 |
419025 |
0 |
0 |
0 |
| T201 |
463797 |
0 |
0 |
0 |
| T259 |
212403 |
0 |
0 |
0 |
| T260 |
300457 |
1 |
0 |
0 |
| T261 |
0 |
1 |
0 |
0 |
| T262 |
0 |
1 |
0 |
0 |
| T268 |
219251 |
0 |
0 |
0 |
| T278 |
0 |
1 |
0 |
0 |
| T279 |
0 |
1 |
0 |
0 |
| T280 |
0 |
1 |
0 |
0 |
| T281 |
0 |
1 |
0 |
0 |
| T282 |
0 |
1 |
0 |
0 |
| T283 |
0 |
1 |
0 |
0 |
| T284 |
0 |
1 |
0 |
0 |
| T285 |
218340 |
0 |
0 |
0 |
| T286 |
176294 |
0 |
0 |
0 |
FpvSecCmIbexFetchEnable1_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
516490638 |
25340130 |
0 |
92 |
| T1 |
42248 |
9923 |
0 |
0 |
| T2 |
84649 |
9919 |
0 |
0 |
| T3 |
76631 |
9927 |
0 |
0 |
| T4 |
104153 |
9919 |
0 |
0 |
| T5 |
127764 |
9931 |
0 |
0 |
| T6 |
79367 |
9931 |
0 |
0 |
| T26 |
87872 |
9919 |
0 |
0 |
| T30 |
0 |
0 |
0 |
2 |
| T31 |
0 |
0 |
0 |
2 |
| T34 |
36418 |
36354 |
0 |
2 |
| T35 |
0 |
0 |
0 |
2 |
| T36 |
0 |
0 |
0 |
2 |
| T37 |
0 |
0 |
0 |
2 |
| T83 |
0 |
0 |
0 |
2 |
| T99 |
0 |
0 |
0 |
2 |
| T105 |
61525 |
9923 |
0 |
0 |
| T106 |
94103 |
9923 |
0 |
0 |
| T287 |
0 |
0 |
0 |
2 |
| T288 |
0 |
0 |
0 |
2 |
FpvSecCmIbexFetchEnable2_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
516490638 |
66664375 |
0 |
82 |
| T1 |
42248 |
34775 |
0 |
0 |
| T2 |
84649 |
34775 |
0 |
0 |
| T3 |
76631 |
34775 |
0 |
0 |
| T4 |
104153 |
36292 |
0 |
0 |
| T5 |
127764 |
34791 |
0 |
0 |
| T6 |
79367 |
34775 |
0 |
0 |
| T7 |
0 |
0 |
0 |
2 |
| T26 |
87872 |
38300 |
0 |
0 |
| T30 |
0 |
0 |
0 |
2 |
| T34 |
36418 |
34775 |
0 |
0 |
| T35 |
0 |
0 |
0 |
2 |
| T36 |
0 |
0 |
0 |
2 |
| T37 |
0 |
0 |
0 |
2 |
| T53 |
0 |
0 |
0 |
2 |
| T99 |
0 |
0 |
0 |
2 |
| T105 |
61525 |
34775 |
0 |
0 |
| T106 |
94103 |
34775 |
0 |
0 |
| T287 |
0 |
0 |
0 |
2 |
| T289 |
0 |
0 |
0 |
2 |
| T290 |
0 |
0 |
0 |
2 |
FpvSecCmIbexFetchEnable3Rev_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
516490638 |
444797408 |
0 |
2026 |
| T1 |
42248 |
7415 |
0 |
2 |
| T2 |
84649 |
49820 |
0 |
2 |
| T3 |
76631 |
41791 |
0 |
2 |
| T4 |
104153 |
67802 |
0 |
2 |
| T5 |
127764 |
92912 |
0 |
2 |
| T6 |
79367 |
44527 |
0 |
2 |
| T26 |
87872 |
49513 |
0 |
2 |
| T34 |
36418 |
0 |
0 |
2 |
| T105 |
61525 |
26692 |
0 |
2 |
| T106 |
94103 |
59274 |
0 |
2 |
| T121 |
0 |
61432 |
0 |
0 |
FpvSecCmIbexFetchEnable3_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
516490638 |
444799324 |
0 |
1922 |
| T1 |
42248 |
7416 |
0 |
2 |
| T2 |
84649 |
49821 |
0 |
2 |
| T3 |
76631 |
41792 |
0 |
2 |
| T4 |
104153 |
67804 |
0 |
2 |
| T5 |
127764 |
92913 |
0 |
2 |
| T6 |
79367 |
44528 |
0 |
2 |
| T26 |
87872 |
49515 |
0 |
2 |
| T34 |
36418 |
0 |
0 |
0 |
| T105 |
61525 |
26693 |
0 |
2 |
| T106 |
94103 |
59275 |
0 |
2 |
| T121 |
0 |
61433 |
0 |
2 |
FpvSecCmIbexInstrIntgErrCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
516490638 |
307 |
0 |
0 |
| T10 |
408746 |
0 |
0 |
0 |
| T59 |
289057 |
0 |
0 |
0 |
| T63 |
243025 |
0 |
0 |
0 |
| T82 |
253757 |
77 |
0 |
0 |
| T84 |
242849 |
0 |
0 |
0 |
| T131 |
231889 |
0 |
0 |
0 |
| T148 |
214752 |
0 |
0 |
0 |
| T218 |
164084 |
0 |
0 |
0 |
| T238 |
249256 |
0 |
0 |
0 |
| T291 |
0 |
77 |
0 |
0 |
| T292 |
0 |
76 |
0 |
0 |
| T293 |
0 |
77 |
0 |
0 |
| T294 |
213144 |
0 |
0 |
0 |
FpvSecCmIbexLoadRespIntgErrCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
516490638 |
587 |
0 |
0 |
| T66 |
272702 |
0 |
0 |
0 |
| T75 |
92338 |
0 |
0 |
0 |
| T151 |
0 |
31 |
0 |
0 |
| T196 |
419025 |
0 |
0 |
0 |
| T201 |
463797 |
0 |
0 |
0 |
| T209 |
0 |
32 |
0 |
0 |
| T210 |
0 |
32 |
0 |
0 |
| T216 |
153072 |
100 |
0 |
0 |
| T259 |
212403 |
0 |
0 |
0 |
| T260 |
300457 |
0 |
0 |
0 |
| T268 |
219251 |
0 |
0 |
0 |
| T285 |
218340 |
0 |
0 |
0 |
| T286 |
176294 |
0 |
0 |
0 |
| T295 |
0 |
100 |
0 |
0 |
| T296 |
0 |
31 |
0 |
0 |
| T297 |
0 |
32 |
0 |
0 |
| T298 |
0 |
31 |
0 |
0 |
| T299 |
0 |
99 |
0 |
0 |
| T300 |
0 |
32 |
0 |
0 |
FpvSecCmIbexLockstepResetCountAlertCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
516490638 |
0 |
0 |
0 |
FpvSecCmIbexPcMismatchCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
516490638 |
0 |
0 |
0 |
FpvSecCmIbexRfEccErrCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
516490638 |
0 |
0 |
0 |
FpvSecCmIbexStoreRespIntgErrCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
516490638 |
0 |
0 |
0 |
FpvSecCmRegWeOnehotCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
516490638 |
7 |
0 |
0 |
| T115 |
0 |
1 |
0 |
0 |
| T173 |
392483 |
0 |
0 |
0 |
| T269 |
129596 |
1 |
0 |
0 |
| T270 |
0 |
1 |
0 |
0 |
| T278 |
226813 |
0 |
0 |
0 |
| T301 |
0 |
1 |
0 |
0 |
| T302 |
0 |
1 |
0 |
0 |
| T303 |
0 |
1 |
0 |
0 |
| T304 |
0 |
1 |
0 |
0 |
| T305 |
290216 |
0 |
0 |
0 |
| T306 |
422109 |
0 |
0 |
0 |
| T307 |
206069 |
0 |
0 |
0 |
| T308 |
186882 |
0 |
0 |
0 |
| T309 |
138013 |
0 |
0 |
0 |
| T310 |
400822 |
0 |
0 |
0 |
| T311 |
449254 |
0 |
0 |
0 |
FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
516490638 |
0 |
0 |
0 |
FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
516490638 |
0 |
0 |
0 |
FpvSecCmRvCoreRegWeOnehotCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
516490638 |
0 |
0 |
0 |
g_instr_intg_err_assert_signals.AssertConnected_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1025 |
1025 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T26 |
1 |
1 |
0 |
0 |
| T34 |
1 |
1 |
0 |
0 |
| T105 |
1 |
1 |
0 |
0 |
| T106 |
1 |
1 |
0 |
0 |
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1025 |
1025 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T26 |
1 |
1 |
0 |
0 |
| T34 |
1 |
1 |
0 |
0 |
| T105 |
1 |
1 |
0 |
0 |
| T106 |
1 |
1 |
0 |
0 |
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1025 |
1025 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T26 |
1 |
1 |
0 |
0 |
| T34 |
1 |
1 |
0 |
0 |
| T105 |
1 |
1 |
0 |
0 |
| T106 |
1 |
1 |
0 |
0 |
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1025 |
1025 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T26 |
1 |
1 |
0 |
0 |
| T34 |
1 |
1 |
0 |
0 |
| T105 |
1 |
1 |
0 |
0 |
| T106 |
1 |
1 |
0 |
0 |
g_rf_ecc_err_comb_assert_signals.AssertConnected_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1025 |
1025 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T26 |
1 |
1 |
0 |
0 |
| T34 |
1 |
1 |
0 |
0 |
| T105 |
1 |
1 |
0 |
0 |
| T106 |
1 |
1 |
0 |
0 |
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
516490638 |
230 |
0 |
0 |
| T91 |
211864 |
0 |
0 |
0 |
| T123 |
166559 |
0 |
0 |
0 |
| T167 |
182279 |
0 |
0 |
0 |
| T213 |
81443 |
45 |
0 |
0 |
| T214 |
105437 |
32 |
0 |
0 |
| T215 |
0 |
33 |
0 |
0 |
| T236 |
650384 |
0 |
0 |
0 |
| T263 |
0 |
34 |
0 |
0 |
| T276 |
637696 |
0 |
0 |
0 |
| T312 |
0 |
37 |
0 |
0 |
| T313 |
0 |
49 |
0 |
0 |
| T314 |
85784 |
0 |
0 |
0 |
| T315 |
596324 |
0 |
0 |
0 |
| T316 |
118205 |
0 |
0 |
0 |
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
516490638 |
206 |
0 |
0 |
| T88 |
119156 |
0 |
0 |
0 |
| T153 |
184117 |
0 |
0 |
0 |
| T154 |
211020 |
0 |
0 |
0 |
| T183 |
430847 |
0 |
0 |
0 |
| T212 |
385747 |
16 |
0 |
0 |
| T213 |
0 |
11 |
0 |
0 |
| T214 |
0 |
42 |
0 |
0 |
| T215 |
0 |
42 |
0 |
0 |
| T219 |
327753 |
0 |
0 |
0 |
| T263 |
0 |
42 |
0 |
0 |
| T312 |
0 |
9 |
0 |
0 |
| T313 |
0 |
12 |
0 |
0 |
| T317 |
0 |
16 |
0 |
0 |
| T318 |
0 |
16 |
0 |
0 |
| T319 |
271490 |
0 |
0 |
0 |
| T320 |
407978 |
0 |
0 |
0 |
| T321 |
626534 |
0 |
0 |
0 |
| T322 |
126541 |
0 |
0 |
0 |