Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_sim_win_rsp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_data_intg.u_tlul_data_integ_enc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_data_intg.u_tlul_data_integ_enc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_data_intg.u_tlul_data_integ_enc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_data_intg.u_tlul_data_integ_enc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_data_intg.u_tlul_data_integ_enc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_secded_inv_39_32_enc
Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS1399100.00

12 always_comb begin : p_encode 13 1/1 data_o = 39'(data_i); Tests: T1 T2 T3  14 1/1 data_o[32] = ^(data_o & 39'h002606BD25); Tests: T1 T2 T3  15 1/1 data_o[33] = ^(data_o & 39'h00DEBA8050); Tests: T1 T2 T3  16 1/1 data_o[34] = ^(data_o & 39'h00413D89AA); Tests: T1 T2 T3  17 1/1 data_o[35] = ^(data_o & 39'h0031234ED1); Tests: T1 T2 T3  18 1/1 data_o[36] = ^(data_o & 39'h00C2C1323B); Tests: T1 T2 T3  19 1/1 data_o[37] = ^(data_o & 39'h002DCC624C); Tests: T1 T2 T3  20 1/1 data_o[38] = ^(data_o & 39'h0098505586); Tests: T1 T2 T3  21 1/1 data_o ^= 39'h2A00000000; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_sim_win_rsp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen
Line No.TotalCoveredPercent
TOTAL900.00
ALWAYS13900.00

12 always_comb begin : p_encode 13 0/1 ==> data_o = 39'(data_i); 14 0/1 ==> data_o[32] = ^(data_o & 39'h002606BD25); 15 0/1 ==> data_o[33] = ^(data_o & 39'h00DEBA8050); 16 0/1 ==> data_o[34] = ^(data_o & 39'h00413D89AA); 17 0/1 ==> data_o[35] = ^(data_o & 39'h0031234ED1); 18 0/1 ==> data_o[36] = ^(data_o & 39'h00C2C1323B); 19 0/1 ==> data_o[37] = ^(data_o & 39'h002DCC624C); 20 0/1 ==> data_o[38] = ^(data_o & 39'h0098505586); 21 0/1 ==> data_o ^= 39'h2A00000000;
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen
Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS1399100.00

12 always_comb begin : p_encode 13 1/1 data_o = 39'(data_i); Tests: T1 T2 T3  14 1/1 data_o[32] = ^(data_o & 39'h002606BD25); Tests: T1 T2 T3  15 1/1 data_o[33] = ^(data_o & 39'h00DEBA8050); Tests: T1 T2 T3  16 1/1 data_o[34] = ^(data_o & 39'h00413D89AA); Tests: T1 T2 T3  17 1/1 data_o[35] = ^(data_o & 39'h0031234ED1); Tests: T1 T2 T3  18 1/1 data_o[36] = ^(data_o & 39'h00C2C1323B); Tests: T1 T2 T3  19 1/1 data_o[37] = ^(data_o & 39'h002DCC624C); Tests: T1 T2 T3  20 1/1 data_o[38] = ^(data_o & 39'h0098505586); Tests: T1 T2 T3  21 1/1 data_o ^= 39'h2A00000000; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen
Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS1399100.00

12 always_comb begin : p_encode 13 1/1 data_o = 39'(data_i); Tests: T1 T2 T3  14 1/1 data_o[32] = ^(data_o & 39'h002606BD25); Tests: T1 T2 T3  15 1/1 data_o[33] = ^(data_o & 39'h00DEBA8050); Tests: T1 T2 T3  16 1/1 data_o[34] = ^(data_o & 39'h00413D89AA); Tests: T1 T2 T3  17 1/1 data_o[35] = ^(data_o & 39'h0031234ED1); Tests: T1 T2 T3  18 1/1 data_o[36] = ^(data_o & 39'h00C2C1323B); Tests: T1 T2 T3  19 1/1 data_o[37] = ^(data_o & 39'h002DCC624C); Tests: T1 T2 T3  20 1/1 data_o[38] = ^(data_o & 39'h0098505586); Tests: T1 T2 T3  21 1/1 data_o ^= 39'h2A00000000; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen
Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS1399100.00

12 always_comb begin : p_encode 13 1/1 data_o = 39'(data_i); Tests: T2 T4 T5  14 1/1 data_o[32] = ^(data_o & 39'h002606BD25); Tests: T2 T4 T5  15 1/1 data_o[33] = ^(data_o & 39'h00DEBA8050); Tests: T2 T4 T5  16 1/1 data_o[34] = ^(data_o & 39'h00413D89AA); Tests: T2 T4 T5  17 1/1 data_o[35] = ^(data_o & 39'h0031234ED1); Tests: T2 T4 T5  18 1/1 data_o[36] = ^(data_o & 39'h00C2C1323B); Tests: T2 T4 T5  19 1/1 data_o[37] = ^(data_o & 39'h002DCC624C); Tests: T2 T4 T5  20 1/1 data_o[38] = ^(data_o & 39'h0098505586); Tests: T2 T4 T5  21 1/1 data_o ^= 39'h2A00000000; Tests: T2 T4 T5 
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen
Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS1399100.00

12 always_comb begin : p_encode 13 1/1 data_o = 39'(data_i); Tests: T2 T4 T5  14 1/1 data_o[32] = ^(data_o & 39'h002606BD25); Tests: T2 T4 T5  15 1/1 data_o[33] = ^(data_o & 39'h00DEBA8050); Tests: T2 T4 T5  16 1/1 data_o[34] = ^(data_o & 39'h00413D89AA); Tests: T2 T4 T5  17 1/1 data_o[35] = ^(data_o & 39'h0031234ED1); Tests: T2 T4 T5  18 1/1 data_o[36] = ^(data_o & 39'h00C2C1323B); Tests: T2 T4 T5  19 1/1 data_o[37] = ^(data_o & 39'h002DCC624C); Tests: T2 T4 T5  20 1/1 data_o[38] = ^(data_o & 39'h0098505586); Tests: T2 T4 T5  21 1/1 data_o ^= 39'h2A00000000; Tests: T2 T4 T5