Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T30,T36,T42	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T30,T36,T42	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T30,T36,T42	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T30,T36,T42	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T30,T36,T42	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T162,T271,T272	Yes	T95,T96,T97	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T96,T162,T163	Yes	T96,T101,T162	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T42,T212,T98	Yes	T42,T212,T98	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T42,T82,T212	Yes	T42,T82,T212	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T35,T99,T100	Yes	T35,T99,T100	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T35,T68,T95	Yes	T35,T68,T95	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T35,T68,T95	Yes	T35,T68,T95	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T42,T82,T208	Yes	T42,T82,T208	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T42,T37,T43	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T88,T90,T98	Yes	T88,T90,T98	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T42,T37,T43	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T42,T37,T43	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T88,T90,T98	Yes	T88,T90,T98	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T42,T37,T43	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T88,T90,T98	Yes	T88,T90,T98	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T30,T36,T42	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T88,T90,T98	Yes	T88,T90,T98	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T88,T90,T85	Yes	T88,T90,T85	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T88,T90,T98	Yes	T88,T90,T98	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T88,*T90,*T98	Yes	T88,T90,T98	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T88,T90,T98	Yes	T88,T90,T98	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T30,T36,T42	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T68,T95,T96	Yes	T68,T95,T96	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T68,T95,T96	Yes	T68,T95,T96	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T68,T95,T96	Yes	T68,T95,T96	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T68,T95,T96	Yes	T68,T95,T96	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T68,T95,T96	Yes	T68,T95,T96	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T68,T95,T96	Yes	T68,T95,T96	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T95,T96,T101	Yes	T95,T96,T101	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T95,T97,T101	Yes	T95,T97,T101	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T68,T95,T96	Yes	T68,T95,T96	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T68,T162,T271	Yes	T68,T95,T96	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T68,T95,T97	Yes	T68,T95,T96	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T68,T95,T96	Yes	T68,T95,T96	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T68,T95,T96	Yes	T68,T95,T96	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T68,T95,*T97	Yes	T68,T95,T96	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T101	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T68,*T95,*T96	Yes	T68,T95,T96	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T68,T95,T96	Yes	T68,T95,T96	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T30,T36,T42	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T98,T99,T54	Yes	T98,T99,T54	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T98,T99,T54	Yes	T98,T99,T54	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T98,T99,T54	Yes	T98,T99,T54	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T98,T99,T54	Yes	T98,T99,T54	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T98,T99,T54	Yes	T98,T99,T54	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T98,*T54,*T55	Yes	T98,T54,T55	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T98,T99,T54	Yes	T98,T99,T54	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T42,T37,T43	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T98,T54,T55	Yes	T98,T54,T55	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T98,T99,T54	Yes	T98,T99,T54	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T42,T37,T43	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T98,*T54,*T55	Yes	T98,T54,T55	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T42,T37,T43	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T98,T99,T54	Yes	T98,T99,T54	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T1,T205,T90	Yes	T1,T205,T90	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T205,T418,T35	Yes	T205,T418,T35	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T95,*T96,*T97	Yes	T95,T96,T97	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T30,T36,T42	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T75,T419,T289	Yes	T75,T419,T289	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T75,T419,T289	Yes	T75,T419,T289	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T75,T419,T289	Yes	T75,T419,T289	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T68,*T95,*T96	Yes	T68,T95,T96	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T95,T96,T101	Yes	T95,T96,T101	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T75,T419,T289	Yes	T75,T419,T289	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T75,T419,T289	Yes	T75,T419,T289	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T95,T96,T101	Yes	T95,T96,T101	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T419,T289,T420	Yes	T419,T289,T420	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T68,T95,T96	Yes	T75,T76,T77	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T419,T289,T420	Yes	T75,T419,T289	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T95,T96,T97	Yes	T95,T96,T101	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T68,T95,*T101	Yes	T68,T95,T96	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T95,T96,T101	Yes	T95,T96,T101	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T289,*T421,*T422	Yes	T419,T289,T420	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T75,T419,T289	Yes	T75,T419,T289	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T88,*T98,*T35	Yes	T88,T98,T35	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T35,T99,T100	Yes	T35,T99,T100	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T82,T671,T292	Yes	T82,T671,T292	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T88,*T98,*T35	Yes	T88,T98,T35	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T9,T10,T397	Yes	T9,T10,T397	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T9,T10,T397	Yes	T9,T10,T397	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T9,T10,T397	Yes	T9,T10,T397	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T9,T10,T397	Yes	T9,T10,T397	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T9,T10,T397	Yes	T9,T10,T397	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T9,T10,T397	Yes	T9,T10,T397	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T99,*T95,*T96	Yes	T99,T95,T96	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T9,T227,T229	Yes	T9,T227,T229	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T9,T10,T397	Yes	T9,T10,T397	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T9,T10,T397	Yes	T9,T10,T397	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T9,T10,T397	Yes	T9,T10,T397	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T9,T10,T397	Yes	T9,T10,T397	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T9,T10,T397	Yes	T9,T10,T397	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T99,*T95,*T97	Yes	T99,T95,T96	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T95,T96,T101	Yes	T95,T96,T97	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T9,*T10,*T397	Yes	T9,T10,T397	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T9,T10,T397	Yes	T9,T10,T397	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T28,T397,T75	Yes	T28,T397,T75	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T28,T397,T75	Yes	T28,T397,T75	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T28,T397,T75	Yes	T28,T397,T75	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T28,T397,T75	Yes	T28,T397,T75	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T28,T397,T75	Yes	T28,T397,T75	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T28,T397,T75	Yes	T28,T397,T75	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T99,*T95,*T96	Yes	T99,T95,T96	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T96,T97,T101	Yes	T96,T97,T101	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T95,T96,T101	Yes	T95,T96,T101	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T28,T397,T75	Yes	T28,T397,T75	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T28,T397,T75	Yes	T28,T397,T75	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T95,T97,T101	Yes	T95,T97,T101	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T28,T397,T127	Yes	T28,T397,T127	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T28,T397,T127	Yes	T28,T397,T75	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T28,T397,T127	Yes	T28,T397,T127	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T95,T96,T97	Yes	T96,T163,T188	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T99,*T97,*T163	Yes	T99,T95,T96	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T96,T97,T101	Yes	T96,T101,T162	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T28,*T397,*T127	Yes	T28,T397,T127	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T28,T397,T75	Yes	T28,T397,T75	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T6,T32,T8	Yes	T6,T32,T8	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T6,T8,T81	Yes	T6,T8,T81	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T6,T32,T8	Yes	T6,T32,T8	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T6,T32,T8	Yes	T6,T32,T8	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T6,T8,T81	Yes	T6,T8,T81	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T6,T32,T8	Yes	T6,T32,T8	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T99,*T95,*T97	Yes	T99,T95,T97	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T96,T97,T101	Yes	T96,T97,T101	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T6,T32,T8	Yes	T6,T32,T8	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T6,T32,T8	Yes	T6,T32,T8	INPUT
tl_usbdev_i.d_error	Yes	Yes	T95,T101,T162	Yes	T95,T101,T162	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T6,T8,T81	Yes	T6,T32,T8	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T32,T8	Yes	T6,T8,T81	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T6,T32,T8	Yes	T6,T8,T81	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T95,T101,T162	Yes	T95,T101,T163	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T99,*T95,*T97	Yes	T99,T95,T101	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T97,T101,T163	Yes	T101,T163,T188	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T6,*T8,*T81	Yes	T6,T8,T81	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T6,T32,T8	Yes	T6,T32,T8	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T100,*T95,*T96	Yes	T100,T95,T96	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T95,T96,T162	Yes	T95,T96,T162	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T30,T36,T42	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T4,T5,T121	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T95,T96,T101	Yes	T95,T96,T162	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T100,*T95,*T163	Yes	T100,T95,T96	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T95,T96,T101	Yes	T95,T162,T163	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T30,T36,T42	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T100,T95,T96	Yes	T100,T95,T96	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T100,T95,T96	Yes	T100,T95,T96	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T100,T95,T96	Yes	T100,T95,T96	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T100,T95,T96	Yes	T100,T95,T96	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T100,T95,T96	Yes	T100,T95,T96	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T100,T95,*T96	Yes	T100,T95,T96	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T100,T95,T96	Yes	T100,T95,T96	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T100,T162,T271	Yes	T100,T95,T96	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T100,T95,T96	Yes	T100,T95,T96	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T100,T95,T97	Yes	T100,T95,T96	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T100,T95,T96	Yes	T100,T95,T96	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T95,T97,T101	Yes	T95,T97,T101	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T100,T97,T101	Yes	T100,T95,T96	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T97,T101	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T100,*T95,*T96	Yes	T100,T95,T97	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T100,T95,T96	Yes	T100,T95,T96	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T30,T36,T42	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T95,*T96,*T97	Yes	T95,T96,T97	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_hmac_o.d_ready	Yes	Yes	T30,T36,T42	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T75,T660,T326	Yes	T75,T660,T326	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T75,T660,T326	Yes	T75,T660,T326	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T75,T660,T326	Yes	T75,T660,T326	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T75,T660,T326	Yes	T75,T660,T326	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T75,T660,T326	Yes	T75,T660,T326	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T100,*T95,*T96	Yes	T100,T95,T96	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T660,T326,T327	Yes	T660,T326,T327	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T75,T660,T326	Yes	T75,T660,T326	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T75,T660,T326	Yes	T75,T660,T326	INPUT
tl_hmac_i.d_error	Yes	Yes	T95,T101,T162	Yes	T95,T162,T163	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T660,T326,T327	Yes	T660,T326,T327	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T660,T326,T327	Yes	T660,T326,T327	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T75,T660,T326	Yes	T660,T326,T327	INPUT
tl_hmac_i.d_sink	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T100,*T97,*T163	Yes	T100,T95,T96	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T95,T96,T101	Yes	T95,T96,T97	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T75,*T660,*T326	Yes	T660,T326,T327	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T75,T660,T326	Yes	T75,T660,T326	INPUT
tl_kmac_o.d_ready	Yes	Yes	T106,T30,T36	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T106,T75,T450	Yes	T106,T75,T450	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T106,T43,T238	Yes	T106,T43,T238	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T106,T43,T238	Yes	T106,T43,T238	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T106,T75,T450	Yes	T106,T75,T450	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T106,T43,T238	Yes	T106,T43,T238	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T100,*T95,*T96	Yes	T100,T95,T96	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T96,T97,T101	Yes	T96,T97,T101	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T106,T450,T451	Yes	T106,T450,T451	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T106,T43,T238	Yes	T106,T43,T238	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T106,T43,T238	Yes	T106,T43,T238	INPUT
tl_kmac_i.d_error	Yes	Yes	T95,T96,T101	Yes	T95,T96,T101	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T106,T43,T238	Yes	T106,T43,T238	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T106,T43,T238	Yes	T106,T43,T238	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T106,T43,T238	Yes	T106,T43,T200	INPUT
tl_kmac_i.d_sink	Yes	Yes	T95,T96,T101	Yes	T95,T96,T97	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T100,*T95,*T96	Yes	T100,T95,T96	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T106,*T43,*T238	Yes	T106,T43,T200	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T106,T43,T238	Yes	T106,T43,T238	INPUT
tl_aes_o.d_ready	Yes	Yes	T30,T36,T42	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T415,T658,T75	Yes	T415,T658,T75	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T415,T658,T75	Yes	T415,T658,T75	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T415,T658,T75	Yes	T415,T658,T75	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T415,T658,T75	Yes	T415,T658,T75	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T415,T658,T75	Yes	T415,T658,T75	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T95,*T96,*T97	Yes	T95,T96,T97	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T95,T96,T101	Yes	T95,T96,T101	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T95,T96,T101	Yes	T95,T96,T101	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T415,T658,T75	Yes	T415,T658,T75	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T415,T658,T75	Yes	T415,T658,T75	INPUT
tl_aes_i.d_error	Yes	Yes	T95,T96,T97	Yes	T95,T101,T163	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T415,T658,T379	Yes	T415,T658,T379	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T415,T658,T379	Yes	T415,T658,T75	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T415,T658,T379	Yes	T415,T658,T75	INPUT
tl_aes_i.d_sink	Yes	Yes	T95,T96,T97	Yes	T95,T97,T101	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T101,*T163,*T188	Yes	T95,T97,T101	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T95,T101,T163	Yes	T95,T96,T101	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T415,*T658,*T379	Yes	T415,T658,T379	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T415,T658,T75	Yes	T415,T658,T75	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T100,*T95,*T96	Yes	T100,T95,T96	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T95,T97,T101	Yes	T95,T97,T101	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T95,T96,T101	Yes	T95,T96,T101	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T96,T97,T101	Yes	T96,T97,T101	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T160,T161,T157	Yes	T160,T161,T157	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T42,T37,T43	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T42,T37,T43	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T96,T97,T101	Yes	T95,T96,T97	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T100,*T96,*T97	Yes	T100,T95,T96	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T160,*T161,*T157	Yes	T160,T161,T157	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T75,T160,T380	Yes	T75,T160,T380	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T100,*T95,*T96	Yes	T100,T95,T96	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T95,T96,T101	Yes	T95,T96,T101	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T96,T97,T101	Yes	T95,T96,T101	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T160,T380,T626	Yes	T160,T380,T626	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T42,T37,T43	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T42,T37,T43	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T95,T96,T101	Yes	T95,T96,T101	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T100,*T101,*T162	Yes	T100,T95,T96	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T101	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T160,*T380,*T626	Yes	T160,T380,T626	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T75,T160,T380	Yes	T75,T160,T380	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T75,T160,T380	Yes	T75,T160,T380	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T100,*T95,*T96	Yes	T100,T95,T96	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T95,T97,T162	Yes	T95,T97,T162	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T101,T163,T188	Yes	T101,T162,T163	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T160,T380,T157	Yes	T160,T380,T157	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T42,T37,T43	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T42,T37,T43	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T96,T97,T101	Yes	T96,T97,T101	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T100,*T96,*T97	Yes	T100,T95,T101	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T95,T96,T101	Yes	T95,T96,T97	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T160,*T380,*T157	Yes	T160,T380,T157	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T30,T36,T42	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T75,T160,T157	Yes	T75,T160,T157	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T75,T160,T157	Yes	T75,T160,T157	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T75,T160,T157	Yes	T75,T160,T157	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T75,T160,T157	Yes	T75,T160,T157	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T75,T160,T157	Yes	T75,T160,T157	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T100,*T95,*T96	Yes	T100,T95,T96	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T96,T101,T162	Yes	T96,T101,T162	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T75,T160,T157	Yes	T75,T160,T157	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T75,T160,T157	Yes	T75,T160,T157	INPUT
tl_edn1_i.d_error	Yes	Yes	T96,T97,T101	Yes	T96,T97,T101	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T160,T157,T328	Yes	T160,T157,T328	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T157,T328,T267	Yes	T75,T160,T157	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T157,T328,T267	Yes	T75,T160,T157	INPUT
tl_edn1_i.d_sink	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T100,*T96,*T97	Yes	T100,T95,T96	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T160,*T157,*T328	Yes	T160,T157,T328	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T75,T160,T157	Yes	T75,T160,T157	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T99,*T95,*T96	Yes	T99,T95,T96	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T96,T97,T101	Yes	T96,T97,T101	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T2,T4,T26	Yes	T2,T4,T26	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T2,T4,T26	Yes	T2,T4,T5	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T95,T96,T97	Yes	T95,T97,T101	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T99,*T97,*T163	Yes	T99,T95,T96	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
tl_otbn_o.d_ready	Yes	Yes	T30,T36,T42	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T216,T75,T157	Yes	T216,T75,T157	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T216,T75,T157	Yes	T216,T75,T157	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T216,T75,T157	Yes	T216,T75,T157	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T216,T75,T157	Yes	T216,T75,T157	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T216,T75,T157	Yes	T216,T75,T157	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T35,*T231,*T232	Yes	T35,T231,T232	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T95,T101,T162	Yes	T95,T101,T162	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T95,T101,T162	Yes	T95,T101,T162	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T216,T75,T157	Yes	T216,T75,T157	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T216,T75,T157	Yes	T216,T75,T157	INPUT
tl_otbn_i.d_error	Yes	Yes	T101,T162,T163	Yes	T101,T162,T163	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T216,T157,T328	Yes	T216,T157,T328	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T216,T157,T328	Yes	T216,T157,T328	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T216,T75,T157	Yes	T216,T157,T328	INPUT
tl_otbn_i.d_sink	Yes	Yes	T95,T101,T162	Yes	T101,T162,T163	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T35,*T231,*T232	Yes	T35,T231,T232	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T95,T101,T162	Yes	T95,T101,T162	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T216,*T75,*T157	Yes	T216,T157,T328	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T216,T75,T157	Yes	T216,T75,T157	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T30,T36,T42	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T43,T238,T200	Yes	T43,T238,T200	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T43,T238,T200	Yes	T43,T238,T200	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T43,T238,T200	Yes	T43,T238,T200	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T43,T200,T75	Yes	T43,T200,T75	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T43,T238,T200	Yes	T43,T238,T200	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T100,*T95,*T96	Yes	T100,T95,T96	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T95,T97,T101	Yes	T95,T97,T101	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T43,T238,T200	Yes	T43,T238,T200	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T43,T238,T200	Yes	T43,T238,T200	INPUT
tl_keymgr_i.d_error	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T43,T200,T201	Yes	T43,T200,T201	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T43,T200,T201	Yes	T43,T200,T75	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T43,T200,T201	Yes	T43,T200,T75	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T95,T97,T162	Yes	T95,T96,T97	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T100,*T97,*T163	Yes	T100,T95,T96	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T95,T97,T101	Yes	T95,T97,T101	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T43,*T200,*T201	Yes	T43,T238,T200	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T43,T238,T200	Yes	T43,T238,T200	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T54,*T68,*T95	Yes	T54,T68,T95	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T68,T95,T97	Yes	T68,T95,T97	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T95,T96,T97	Yes	T95,T97,T101	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T68,*T97,*T162	Yes	T54,T68,T95	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T96,T97,T101	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T30,T36,T42	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T75,T209,T151	Yes	T75,T209,T151	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T75,T209,T151	Yes	T75,T209,T151	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T75,T209,T151	Yes	T75,T209,T151	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T75,T209,T151	Yes	T75,T209,T151	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T75,T209,T151	Yes	T75,T209,T151	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T99,*T448,*T95	Yes	T99,T448,T95	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T95,T97,T101	Yes	T95,T97,T101	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T95,T97,T101	Yes	T95,T97,T101	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T75,T209,T151	Yes	T75,T209,T151	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T75,T209,T151	Yes	T75,T209,T151	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T95,T96,T163	Yes	T95,T96,T101	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T212,T99,T317	Yes	T212,T99,T317	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T209,T151,T212	Yes	T75,T209,T151	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T209,T151,T212	Yes	T75,T209,T151	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T99,*T95,*T96	Yes	T99,T448,T95	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T95,T97,T101	Yes	T95,T96,T97	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T209,*T151,*T212	Yes	T209,T151,T212	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T75,T209,T151	Yes	T75,T209,T151	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T30,T36,T42	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range