Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_peri_ni	Yes	Yes	T30,T36,T42	Yes	T1,T2,T3	INPUT
tl_main_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T88,*T98,*T35	Yes	T88,T98,T35	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T35,T99,T100	Yes	T35,T99,T100	INPUT
tl_main_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_error	Yes	Yes	T82,T671,T292	Yes	T82,T671,T292	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_sink	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T88,*T98,*T35	Yes	T88,T98,T35	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T131,T132,T226	Yes	T131,T132,T226	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T131,T132,T226	Yes	T131,T132,T226	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T88,*T98,*T35	Yes	T88,T98,T35	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T35,T99,T100	Yes	T35,T99,T100	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T131,T75,T132	Yes	T131,T75,T132	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T131,T75,T132	Yes	T131,T75,T132	INPUT
tl_uart0_i.d_error	Yes	Yes	T95,T162,T163	Yes	T95,T101,T162	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T131,T132,T319	Yes	T131,T132,T319	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T131,T132,T192	Yes	T131,T75,T132	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T131,T132,T192	Yes	T131,T75,T132	INPUT
tl_uart0_i.d_sink	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T99,*T54,*T55	Yes	T99,T54,T55	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T95,T101,T162	Yes	T95,T162,T163	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T131,*T132,*T319	Yes	T131,T132,T319	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T131,T75,T132	Yes	T131,T75,T132	INPUT
tl_uart1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T133,T134,T319	Yes	T133,T134,T319	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T133,T134,T319	Yes	T133,T134,T319	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T88,*T98,*T35	Yes	T88,T98,T35	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T35,T99,T100	Yes	T35,T99,T100	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T133,T134,T75	Yes	T133,T134,T75	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T133,T134,T75	Yes	T133,T134,T75	INPUT
tl_uart1_i.d_error	Yes	Yes	T97,T162,T163	Yes	T95,T96,T97	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T133,T134,T319	Yes	T133,T134,T319	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T133,T134,T192	Yes	T133,T134,T75	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T133,T134,T192	Yes	T133,T134,T75	INPUT
tl_uart1_i.d_sink	Yes	Yes	T95,T96,T101	Yes	T95,T96,T162	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T99,*T97,*T162	Yes	T99,T95,T96	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T96,T97,T101	Yes	T96,T162,T163	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T133,*T134,*T319	Yes	T133,T134,T319	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T133,T134,T75	Yes	T133,T134,T75	INPUT
tl_uart2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T63,T319,T99	Yes	T63,T319,T99	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T63,T319,T99	Yes	T63,T319,T99	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T88,*T98,*T35	Yes	T88,T98,T35	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T35,T99,T100	Yes	T35,T99,T100	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T63,T75,T192	Yes	T63,T75,T192	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T63,T75,T192	Yes	T63,T75,T192	INPUT
tl_uart2_i.d_error	Yes	Yes	T95,T101,T163	Yes	T95,T96,T101	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T63,T319,T99	Yes	T63,T319,T99	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T63,T192,T319	Yes	T63,T75,T192	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T63,T192,T319	Yes	T63,T75,T192	INPUT
tl_uart2_i.d_sink	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T99,*T95,*T163	Yes	T99,T95,T96	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T96,T163,T188	Yes	T95,T96,T163	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T63,*T319,*T99	Yes	T63,T319,T99	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T63,T75,T192	Yes	T63,T75,T192	INPUT
tl_uart3_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T38,T65,T319	Yes	T38,T65,T319	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T38,T65,T319	Yes	T38,T65,T319	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T88,*T98,*T35	Yes	T88,T98,T35	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T35,T99,T100	Yes	T35,T99,T100	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T38,T75,T192	Yes	T38,T75,T192	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T38,T75,T192	Yes	T38,T75,T192	INPUT
tl_uart3_i.d_error	Yes	Yes	T95,T97,T162	Yes	T95,T97,T162	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T38,T65,T319	Yes	T38,T65,T319	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T38,T192,T65	Yes	T38,T75,T192	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T38,T192,T65	Yes	T38,T75,T192	INPUT
tl_uart3_i.d_sink	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T99,*T97,*T163	Yes	T99,T95,T96	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T162	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T38,*T65,*T319	Yes	T38,T65,T319	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T38,T75,T192	Yes	T38,T75,T192	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T57,T58,T397	Yes	T57,T58,T397	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T57,T58,T397	Yes	T57,T58,T397	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T88,*T98,*T35	Yes	T88,T98,T35	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T35,T99,T100	Yes	T35,T99,T100	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T57,T58,T397	Yes	T57,T58,T397	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T57,T58,T397	Yes	T57,T58,T397	INPUT
tl_i2c0_i.d_error	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T57,T58,T331	Yes	T57,T58,T331	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T57,T58,T397	Yes	T57,T58,T397	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T57,T58,T397	Yes	T57,T58,T397	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T100,*T95,*T96	Yes	T100,T95,T96	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T95,T96,T101	Yes	T95,T96,T97	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T57,*T58,*T397	Yes	T57,T58,T397	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T57,T58,T397	Yes	T57,T58,T397	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T59,T397,T331	Yes	T59,T397,T331	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T59,T397,T331	Yes	T59,T397,T331	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T88,*T98,*T35	Yes	T88,T98,T35	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T35,T99,T100	Yes	T35,T99,T100	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T59,T397,T75	Yes	T59,T397,T75	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T59,T397,T75	Yes	T59,T397,T75	INPUT
tl_i2c1_i.d_error	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T59,T331,T11	Yes	T59,T331,T11	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T59,T397,T192	Yes	T59,T397,T75	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T59,T397,T192	Yes	T59,T397,T75	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T95,T97,T101	Yes	T95,T101,T162	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T100,*T95,*T97	Yes	T100,T95,T97	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T95,T97,T162	Yes	T95,T162,T163	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T59,*T397,*T331	Yes	T59,T397,T331	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T59,T397,T75	Yes	T59,T397,T75	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T397,T61,T331	Yes	T397,T61,T331	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T397,T61,T331	Yes	T397,T61,T331	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T88,*T98,*T35	Yes	T88,T98,T35	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T35,T99,T100	Yes	T35,T99,T100	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T397,T61,T75	Yes	T397,T61,T75	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T397,T61,T75	Yes	T397,T61,T75	INPUT
tl_i2c2_i.d_error	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T61,T331,T11	Yes	T61,T331,T11	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T397,T61,T192	Yes	T397,T61,T75	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T397,T61,T192	Yes	T397,T61,T75	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T95,T97,T101	Yes	T95,T96,T97	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T100,*T97,*T163	Yes	T100,T95,T96	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T397,*T61,*T331	Yes	T397,T61,T331	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T397,T61,T75	Yes	T397,T61,T75	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T2,T127,T11	Yes	T2,T127,T11	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T2,T127,T11	Yes	T2,T127,T11	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T88,*T98,*T35	Yes	T88,T98,T35	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T35,T99,T100	Yes	T35,T99,T100	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T2,T75,T127	Yes	T2,T75,T127	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T2,T75,T127	Yes	T2,T75,T127	INPUT
tl_pattgen_i.d_error	Yes	Yes	T95,T96,T101	Yes	T95,T101,T163	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T2,T127,T11	Yes	T2,T127,T11	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T127,T11	Yes	T2,T75,T127	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T2,T127,T11	Yes	T2,T75,T127	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T95,T96,T101	Yes	T95,T96,T101	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	*T163,*T188,*T189	Yes	T95,T96,T162	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T95,T96,T101	Yes	T95,T96,T101	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T2,*T127,*T11	Yes	T2,T127,T11	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T2,T75,T127	Yes	T2,T75,T127	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T33,T69,T137	Yes	T33,T69,T137	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T33,T69,T137	Yes	T33,T69,T137	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T88,*T98,*T35	Yes	T88,T98,T35	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T35,T99,T100	Yes	T35,T99,T100	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T33,T75,T69	Yes	T33,T75,T69	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T33,T75,T69	Yes	T33,T75,T69	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T33,T69,T137	Yes	T33,T69,T137	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T33,T69,T137	Yes	T33,T75,T69	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T33,T69,T137	Yes	T33,T75,T69	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T95,T96,T101	Yes	T96,T97,T101	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	*T68,*T96,*T101	Yes	T68,T95,T96	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T33,*T69,*T137	Yes	T33,T69,T137	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T33,T75,T69	Yes	T33,T75,T69	INPUT
tl_gpio_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T88,*T98,*T35	Yes	T88,T98,T35	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T35,T99,T100	Yes	T35,T99,T100	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_gpio_i.d_error	Yes	Yes	T95,T163,T188	Yes	T95,T163,T188	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T27,T12,T331	Yes	T27,T12,T331	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T27,T12,T331	Yes	T26,T27,T12	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T27,T12,T331	Yes	T26,T27,T12	INPUT
tl_gpio_i.d_sink	Yes	Yes	T97,T162,T163	Yes	T95,T163,T188	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T100,*T95,*T97	Yes	T100,T97,T162	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T95,T97,T162	Yes	T95,T97,T101	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T26,*T27,*T12	Yes	T2,T3,T4	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T13,T12,T9	Yes	T13,T12,T9	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T13,T12,T9	Yes	T13,T12,T9	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T88,*T98,*T35	Yes	T88,T98,T35	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T35,T99,T100	Yes	T35,T99,T100	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T13,T12,T9	Yes	T13,T12,T9	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T13,T12,T9	Yes	T13,T12,T9	INPUT
tl_spi_device_i.d_error	Yes	Yes	T95,T162,T163	Yes	T95,T162,T163	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T13,T9,T10	Yes	T13,T9,T10	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T13,T12,T9	Yes	T13,T12,T9	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T13,T12,T9	Yes	T13,T9,T10	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T95,T96,T162	Yes	T95,T162,T163	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T99,*T95,*T163	Yes	T99,T95,T96	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T95,T101,T162	Yes	T95,T162,T163	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T13,*T12,*T9	Yes	T13,T12,T9	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T13,T12,T9	Yes	T13,T12,T9	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T126,T258,T650	Yes	T126,T258,T650	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T126,T258,T650	Yes	T126,T258,T650	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T88,*T98,*T35	Yes	T88,T98,T35	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T35,T99,T100	Yes	T35,T99,T100	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T126,T258,T75	Yes	T126,T258,T75	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T126,T258,T75	Yes	T126,T258,T75	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T97,T101,T162	Yes	T96,T97,T101	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T126,T258,T650	Yes	T126,T258,T650	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T126,T258,T650	Yes	T126,T258,T75	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T126,T258,T650	Yes	T126,T258,T75	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T95,T97,T101	Yes	T95,T96,T97	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T99,*T97,*T163	Yes	T99,T95,T97	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T97,T101,T162	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T126,*T258,*T650	Yes	T126,T258,T650	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T126,T258,T75	Yes	T126,T258,T75	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T26	Yes	T4,T5,T26	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T26	Yes	T4,T5,T26	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T88,*T98,*T35	Yes	T88,T98,T35	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T35,T99,T100	Yes	T35,T99,T100	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T4,T5,T26	Yes	T4,T5,T26	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T4,T5,T26	Yes	T4,T5,T26	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T95,T96,T97	Yes	T96,T97,T101	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T26	Yes	T4,T5,T26	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T26	Yes	T4,T5,T26	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T4,T5,T26	Yes	T4,T5,T26	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T68,*T96,*T97	Yes	T68,T95,T96	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T96,T97,T101	Yes	T96,T97,T162	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T26	Yes	T4,T5,T26	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T4,T5,T26	Yes	T4,T5,T26	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T88,*T98,*T35	Yes	T88,T98,T35	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T35,T99,T100	Yes	T35,T99,T100	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T95,T101,T162	Yes	T95,T101,T162	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T42,T37,T43	Yes	T2,T3,T4	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T42,T37,T43	Yes	T2,T3,T4	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T95,T97,T101	Yes	T95,T97,T101	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T68,*T97,*T101	Yes	T68,T95,T96	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T96,T97,T101	Yes	T95,T96,T97	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T38,T133,T134	Yes	T38,T133,T134	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T38,T133,T134	Yes	T38,T133,T134	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T88,*T98,*T35	Yes	T88,T98,T35	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T35,T99,T100	Yes	T35,T99,T100	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T95,T97,T101	Yes	T95,T97,T101	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T38,T133,T134	Yes	T38,T133,T134	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T38,T133,T42	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T38,T133,T42	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T97,T101,T163	Yes	T95,T96,T97	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T95,*T97,*T101	Yes	T88,T185,T186	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T101	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T38,*T133,*T134	Yes	T38,T133,T134	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T88,*T98,*T35	Yes	T88,T98,T35	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T35,T99,T100	Yes	T35,T99,T100	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T95,T96,T101	Yes	T95,T96,T101	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T95,T96,T101	Yes	T95,T96,T101	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T68,*T95,*T101	Yes	T68,T95,T96	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T95,T96,T101	Yes	T95,T96,T101	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T88,*T98,*T35	Yes	T88,T98,T35	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T35,T99,T100	Yes	T35,T99,T100	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T95,T96,T101	Yes	T95,T96,T97	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T95,T96,T101	Yes	T95,T96,T97	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T88,*T185,*T186	Yes	T88,T185,T186	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T95,T96,T162	Yes	T95,T96,T162	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T122,*T187,*T43	Yes	T122,T187,T43	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T88,*T98,*T35	Yes	T88,T98,T35	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T35,T99,T100	Yes	T35,T99,T100	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T1,T2,T3	Yes	T42,T37,T82	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T95,T96,T162	Yes	T95,T97,T162	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T95,T96,T97	Yes	T95,T97,T162	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T42,T37,T82	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	T163,T188,T189	Yes	T95,T96,T101	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T97,T101,T162	Yes	T95,T97,T101	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T42,T37,T82	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T121,T122,T134	Yes	T121,T122,T134	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T121,T122,T134	Yes	T121,T122,T134	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T88,*T98,*T35	Yes	T88,T98,T35	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T35,T99,T100	Yes	T35,T99,T100	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T121,T122,T134	Yes	T121,T122,T134	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T121,T122,T134	Yes	T121,T122,T134	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T95,T96,T162	Yes	T95,T101,T162	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T122,T43,T218	Yes	T121,T122,T43	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T218,T196,T158	Yes	T218,T196,T75	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T122,T43,T218	Yes	T121,T122,T134	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T98,*T323,*T324	Yes	T98,T323,T324	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T97,T162,T163	Yes	T95,T96,T97	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T43,*T218,*T200	Yes	T121,T122,T134	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T121,T122,T134	Yes	T121,T122,T134	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T88,*T98,*T35	Yes	T88,T98,T35	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T35,T99,T100	Yes	T35,T99,T100	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T180,T165,T127	Yes	T180,T165,T127	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T180,T165,T127	Yes	T75,T180,T165	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T42,T37,T43	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T95,T96,T97	Yes	T96,T97,T101	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T99,*T96,*T97	Yes	T99,T95,T96	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T42,*T37,*T43	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T42,T82,T84	Yes	T42,T82,T84	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T42,T82,T84	Yes	T42,T82,T84	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T88,*T98,*T35	Yes	T88,T98,T35	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T35,T99,T100	Yes	T35,T99,T100	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T42,T82,T84	Yes	T42,T82,T84	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T42,T82,T84	Yes	T42,T82,T84	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T95,T97,T101	Yes	T95,T101,T163	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T42,T82,T84	Yes	T42,T82,T84	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T42,T82,T84	Yes	T42,T82,T84	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T42,T82,T84	Yes	T42,T82,T84	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T95,T101,T162	Yes	T95,T96,T101	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T162,*T163,*T188	Yes	T95,T96,T97	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T95,T101,T163	Yes	T95,T97,T101	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T42,*T82,*T84	Yes	T42,T82,T84	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T42,T82,T84	Yes	T42,T82,T84	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T209,T151,T211	Yes	T209,T151,T211	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T209,T151,T211	Yes	T209,T151,T211	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T88,*T98,*T35	Yes	T88,T98,T35	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T35,T99,T100	Yes	T35,T99,T100	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T75,T209,T151	Yes	T75,T209,T151	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T75,T209,T151	Yes	T75,T209,T151	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T96,T101,T162	Yes	T95,T96,T101	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T209,T151,T211	Yes	T209,T151,T211	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T209,T151,T211	Yes	T75,T209,T151	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T209,T151,T211	Yes	T75,T209,T151	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T95,T101,T162	Yes	T96,T97,T101	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T99,*T97,*T101	Yes	T99,T95,T96	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T101,T162,T163	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T209,*T151,*T211	Yes	T209,T151,T211	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T75,T209,T151	Yes	T75,T209,T151	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T5,T42,T82	Yes	T5,T42,T82	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T88,*T98,*T35	Yes	T88,T98,T35	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T35,T99,T100	Yes	T35,T99,T100	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T30,T36,T42	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T5,T42,T82	Yes	T5,T42,T82	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T30,T36	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T42,T82,T84	Yes	T42,T82,T84	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T95,T96,T101	Yes	T96,T97,T101	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T35,*T55,*T231	Yes	T35,T55,T231	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T101,T162,T163	Yes	T101,T163,T188	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T5,T42,T82	Yes	T5,T42,T82	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T5,T42,T82	Yes	T5,T42,T82	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T88,*T98,*T35	Yes	T88,T98,T35	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T35,T99,T100	Yes	T35,T99,T100	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T5,T42,T82	Yes	T5,T42,T82	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T5,T42,T82	Yes	T5,T42,T82	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T96,T97,T101	Yes	T96,T97,T101	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T5,T42,T82	Yes	T5,T42,T82	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T42,T82	Yes	T5,T42,T82	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T5,T42,T82	Yes	T5,T42,T82	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T96,T97,T101	Yes	T96,T97,T101	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T97,*T101,*T163	Yes	T55,T56,T448	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T96,T97,T101	Yes	T96,T97,T101	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T5,*T42,*T82	Yes	T5,T42,T82	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T5,T42,T82	Yes	T5,T42,T82	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T17,T67,T29	Yes	T17,T67,T29	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T17,T67,T29	Yes	T17,T67,T29	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T88,*T98,*T35	Yes	T88,T98,T35	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T35,T99,T100	Yes	T35,T99,T100	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T17,T67,T29	Yes	T17,T67,T29	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T17,T67,T29	Yes	T17,T67,T29	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T95,T96,T101	Yes	T95,T96,T101	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T17,T67,T29	Yes	T17,T67,T29	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T17,T67,T14	Yes	T17,T67,T14	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T17,T67,T29	Yes	T17,T67,T29	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T95,T96,T101	Yes	T95,T96,T101	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T99,*T95,*T162	Yes	T99,T95,T101	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T95,T101,T162	Yes	T95,T101,T162	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T17,*T67,*T14	Yes	T17,T67,T29	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T17,T67,T29	Yes	T17,T67,T29	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T140,T72,T331	Yes	T140,T72,T331	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T140,T72,T331	Yes	T140,T72,T331	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T88,*T98,*T35	Yes	T88,T98,T35	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T35,T99,T100	Yes	T35,T99,T100	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T75,T140,T72	Yes	T75,T140,T72	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T75,T140,T72	Yes	T75,T140,T72	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T95,T97,T101	Yes	T95,T97,T101	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T140,T72,T331	Yes	T140,T72,T331	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T140,T72,T331	Yes	T75,T140,T72	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T140,T72,T123	Yes	T75,T140,T72	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T95,T97,T101	Yes	T95,T96,T101	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T97,*T101,*T163	Yes	T95,T96,T101	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T95,T97,T101	Yes	T95,T97,T101	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T140,*T72,*T331	Yes	T140,T72,T331	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T75,T140,T72	Yes	T75,T140,T72	INPUT
tl_ast_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T88,*T98,*T35	Yes	T88,T98,T35	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T35,T99,T100	Yes	T35,T99,T100	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_ast_i.d_error	Yes	Yes	T95,T96,T97	Yes	T95,T96,T101	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T95,T96,T97	Yes	T95,T101,T162	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T42,T37,T43	Yes	T1,T2,T3	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T42,T37,T43	Yes	T1,T2,T3	INPUT
tl_ast_i.d_sink	Yes	Yes	T95,T96,T97	Yes	T95,T101,T162	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	*T96,*T97,*T101	Yes	T95,T101,T163	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T101	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T95,*T96,*T97	Yes	T95,T96,T101	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range