Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : edn
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.34 99.34

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_edn1 99.02 99.02
tb.dut.top_earlgrey.u_edn0 99.25 99.25


Module Instance : tb.dut.top_earlgrey.u_edn1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.02 99.02


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.02 99.02


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.94 92.47 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_edn0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.25 99.25


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.25 99.25


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.94 92.47 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : edn
TotalCoveredPercent
Totals 78 75 96.15
Total Bits 1210 1202 99.34
Total Bits 0->1 605 602 99.50
Total Bits 1->0 605 600 99.17

Ports 78 75 96.15
Port Bits 1210 1202 99.34
Port Bits 0->1 605 602 99.50
Port Bits 1->0 605 600 99.17

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T30,T36,T42 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T75,T160,T380 Yes T75,T160,T380 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T75,T160,T380 Yes T75,T160,T380 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[6:0] Yes Yes *T95,*T96,*T97 Yes T95,T96,T97 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T100,*T95,*T96 Yes T100,T95,T96 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T95,T96,T97 Yes T95,T96,T97 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T95,T96,T97 Yes T95,T96,T97 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T96,T97,T101 Yes T96,T97,T101 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T160,T380,T157 Yes T160,T380,T157 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T42,T37,T43 Yes T1,T2,T3 OUTPUT
tl_o.d_data[31:0] Yes Yes T42,T37,T43 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Yes Yes T95,T96,T97 Yes T95,T96,T97 OUTPUT
tl_o.d_source[5:0] Yes Yes *T100,*T96,*T97 Yes T100,T95,T96 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T95,T96,T97 Yes T95,T96,T97 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T160,*T380,*T157 Yes T160,T380,T157 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T43,T200,T201 Yes T43,T200,T201 INPUT
edn_i[1].edn_req Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
edn_i[2].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_i[3].edn_req Yes Yes T106,T145,T183 Yes T106,T145,T183 INPUT
edn_i[4].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_i[5].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_i[6].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_i[7].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T43,T200,T201 Yes T43,T200,T201 OUTPUT
edn_o[0].edn_fips Yes Yes T157,T276,T277 Yes T157,T328,T145 OUTPUT
edn_o[0].edn_ack Yes Yes T43,T200,T201 Yes T43,T200,T201 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[1].edn_fips No No Yes T183,T184,T147 OUTPUT
edn_o[1].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T105,T121,T141 Yes T2,T3,T4 OUTPUT
edn_o[2].edn_fips Yes Yes T142,T143,T144 Yes T145,T146,T147 OUTPUT
edn_o[2].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T106,T145,T183 Yes T106,T145,T183 OUTPUT
edn_o[3].edn_fips No No Yes T145,T183,T11 OUTPUT
edn_o[3].edn_ack Yes Yes T106,T145,T183 Yes T106,T145,T183 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T42,T37,T43 Yes T3,T4,T105 OUTPUT
edn_o[4].edn_fips Yes Yes T630,T631 Yes T632,T633,T143 OUTPUT
edn_o[4].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[5].edn_fips Yes Yes T276,T277,T629 Yes T634,T145,T183 OUTPUT
edn_o[5].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[6].edn_fips Yes Yes T157,T276,T277 Yes T157,T328,T145 OUTPUT
edn_o[6].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[7].edn_bus[31:0] Yes Yes T121,T12,T42 Yes T2,T4,T5 OUTPUT
edn_o[7].edn_fips Yes Yes T157,T276,T277 Yes T157,T267,T145 OUTPUT
edn_o[7].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T42,T37,T43 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
csrng_cmd_i.genbits_fips Yes Yes T157,T142,T627 Yes T157,T328,T267 INPUT
csrng_cmd_i.genbits_valid Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T380,T159,T276 Yes T380,T159,T276 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T75,T102,T380 Yes T75,T102,T380 INPUT
alert_rx_i[0].ping_n Yes Yes T102,T103,T104 Yes T102,T103,T104 INPUT
alert_rx_i[0].ping_p Yes Yes T102,T103,T104 Yes T102,T103,T104 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T75,T102,T103 Yes T75,T102,T103 INPUT
alert_rx_i[1].ping_n Yes Yes T102,T103,T104 Yes T102,T103,T104 INPUT
alert_rx_i[1].ping_p Yes Yes T102,T103,T104 Yes T102,T103,T104 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T75,T102,T380 Yes T75,T102,T380 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T75,T102,T103 Yes T75,T102,T103 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T320,T331,T337 Yes T320,T331,T337 OUTPUT
intr_edn_fatal_err_o Yes Yes T331,T332,T333 Yes T331,T332,T333 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn1
TotalCoveredPercent
Totals 50 48 96.00
Total Bits 714 707 99.02
Total Bits 0->1 357 354 99.16
Total Bits 1->0 357 353 98.88

Ports 50 48 96.00
Port Bits 714 707 99.02
Port Bits 0->1 357 354 99.16
Port Bits 1->0 357 353 98.88

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T30,T36,T42 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T30,T36,T42 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T75,T160,T157 Yes T75,T160,T157 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T75,T160,T157 Yes T75,T160,T157 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T75,T160,T157 Yes T75,T160,T157 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T75,T160,T157 Yes T75,T160,T157 INPUT
tl_i.a_mask[3:0] Yes Yes T75,T160,T157 Yes T75,T160,T157 INPUT
tl_i.a_address[6:0] Yes Yes *T96,*T101,*T163 Yes T96,T101,T163 INPUT
tl_i.a_address[18:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:19] Yes Yes T75,T160,T157 Yes T75,T160,T157 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T75,*T160,*T157 Yes T75,T160,T157 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T75,*T160,*T157 Yes T75,T160,T157 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T100,*T95,*T96 Yes T100,T95,T96 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T95,T96,T97 Yes T95,T96,T97 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T96,T101,T162 Yes T96,T101,T162 INPUT
tl_i.a_valid Yes Yes T75,T160,T157 Yes T75,T160,T157 INPUT
tl_o.a_ready Yes Yes T75,T160,T157 Yes T75,T160,T157 OUTPUT
tl_o.d_error Yes Yes T96,T97,T101 Yes T96,T97,T101 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T160,T157,T328 Yes T160,T157,T328 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T157,T328,T267 Yes T75,T160,T157 OUTPUT
tl_o.d_data[31:0] Yes Yes T157,T328,T267 Yes T75,T160,T157 OUTPUT
tl_o.d_sink Yes Yes T95,T96,T97 Yes T95,T96,T97 OUTPUT
tl_o.d_source[5:0] Yes Yes *T100,*T96,*T97 Yes T100,T95,T96 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T95,T96,T97 Yes T95,T96,T97 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T160,*T157,*T328 Yes T160,T157,T328 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T75,T160,T157 Yes T75,T160,T157 OUTPUT
edn_i[0].edn_req Yes Yes T157,T328,T145 Yes T157,T328,T145 INPUT
edn_i[1].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[2].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[3].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[4].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[5].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[6].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[7].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_o[0].edn_bus[31:0] Yes Yes T157,T328,T145 Yes T157,T328,T145 OUTPUT
edn_o[0].edn_fips Yes Yes T157,T276,T277 Yes T157,T328,T145 OUTPUT
edn_o[0].edn_ack Yes Yes T157,T328,T145 Yes T157,T328,T145 OUTPUT
edn_o[1].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
csrng_cmd_o.genbits_ready Yes Yes T157,T328,T267 Yes T157,T328,T267 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T157,T328,T159 Yes T157,T328,T267 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T157,T328,T267 Yes T157,T328,T267 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T157,T328,T145 Yes T157,T328,T267 INPUT
csrng_cmd_i.genbits_fips No No Yes T157,T627,T628 INPUT
csrng_cmd_i.genbits_valid Yes Yes T157,T328,T267 Yes T157,T328,T267 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T157,T328,T267 Yes T157,T328,T267 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T276,T277,T629 Yes T276,T277,T629 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T75,T102,T103 Yes T75,T102,T103 INPUT
alert_rx_i[0].ping_n Yes Yes T102,T103,T104 Yes T102,T103,T104 INPUT
alert_rx_i[0].ping_p Yes Yes T102,T103,T104 Yes T102,T103,T104 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T75,T102,T103 Yes T75,T102,T103 INPUT
alert_rx_i[1].ping_n Yes Yes T102,T103,T104 Yes T102,T103,T104 INPUT
alert_rx_i[1].ping_p Yes Yes T102,T103,T104 Yes T102,T103,T104 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T75,T102,T103 Yes T75,T102,T103 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T75,T102,T103 Yes T75,T102,T103 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T320,T331,T337 Yes T320,T331,T337 OUTPUT
intr_edn_fatal_err_o Yes Yes T331,T332,T333 Yes T331,T332,T333 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn0
TotalCoveredPercent
Totals 78 74 94.87
Total Bits 1208 1199 99.25
Total Bits 0->1 604 601 99.50
Total Bits 1->0 604 598 99.01

Ports 78 74 94.87
Port Bits 1208 1199 99.25
Port Bits 0->1 604 601 99.50
Port Bits 1->0 604 598 99.01

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T30,T36,T42 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T75,T160,T380 Yes T75,T160,T380 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T75,T160,T380 Yes T75,T160,T380 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[6:0] Yes Yes *T95,*T97,*T101 Yes T95,T97,T101 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18:16] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T100,*T95,*T96 Yes T100,T95,T96 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T95,T97,T162 Yes T95,T97,T162 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T95,T96,T97 Yes T95,T96,T97 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T101,T163,T188 Yes T101,T162,T163 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T160,T380,T157 Yes T160,T380,T157 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T42,T37,T43 Yes T1,T2,T3 OUTPUT
tl_o.d_data[31:0] Yes Yes T42,T37,T43 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Yes Yes T96,T97,T101 Yes T96,T97,T101 OUTPUT
tl_o.d_source[5:0] Yes Yes *T100,*T96,*T97 Yes T100,T95,T101 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T95,T96,T101 Yes T95,T96,T97 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T160,*T380,*T157 Yes T160,T380,T157 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T43,T200,T201 Yes T43,T200,T201 INPUT
edn_i[1].edn_req Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
edn_i[2].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_i[3].edn_req Yes Yes T106,T145,T183 Yes T106,T145,T183 INPUT
edn_i[4].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_i[5].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_i[6].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_i[7].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T43,T200,T201 Yes T43,T200,T201 OUTPUT
edn_o[0].edn_fips No No Yes T145,T183,T240 OUTPUT
edn_o[0].edn_ack Yes Yes T43,T200,T201 Yes T43,T200,T201 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[1].edn_fips No No Yes T183,T184,T147 OUTPUT
edn_o[1].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T105,T121,T141 Yes T2,T3,T4 OUTPUT
edn_o[2].edn_fips Yes Yes T142,T143,T144 Yes T145,T146,T147 OUTPUT
edn_o[2].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T106,T145,T183 Yes T106,T145,T183 OUTPUT
edn_o[3].edn_fips No No Yes T145,T183,T11 OUTPUT
edn_o[3].edn_ack Yes Yes T106,T145,T183 Yes T106,T145,T183 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T42,T37,T43 Yes T3,T4,T105 OUTPUT
edn_o[4].edn_fips Yes Yes T630,T631 Yes T632,T633,T143 OUTPUT
edn_o[4].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[5].edn_fips Yes Yes T276,T277,T629 Yes T634,T145,T183 OUTPUT
edn_o[5].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[6].edn_fips Yes Yes T157,T276,T277 Yes T157,T328,T145 OUTPUT
edn_o[6].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[7].edn_bus[31:0] Yes Yes T121,T12,T42 Yes T2,T4,T5 OUTPUT
edn_o[7].edn_fips Yes Yes T157,T276,T277 Yes T157,T267,T145 OUTPUT
edn_o[7].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T42,T37,T43 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
csrng_cmd_i.genbits_fips Yes Yes T157,T142,T627 Yes T157,T328,T267 INPUT
csrng_cmd_i.genbits_valid Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T380,T159,T276 Yes T380,T159,T276 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T75,T102,T380 Yes T75,T102,T380 INPUT
alert_rx_i[0].ping_n Yes Yes T102,T103,T104 Yes T102,T103,T104 INPUT
alert_rx_i[0].ping_p Yes Yes T102,T103,T104 Yes T102,T103,T104 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T75,T102,T103 Yes T75,T102,T103 INPUT
alert_rx_i[1].ping_n Yes Yes T102,T103,T104 Yes T102,T103,T104 INPUT
alert_rx_i[1].ping_p Yes Yes T102,T103,T104 Yes T102,T103,T104 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T75,T102,T380 Yes T75,T102,T380 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T75,T102,T103 Yes T75,T102,T103 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T320,T331,T337 Yes T320,T331,T337 OUTPUT
intr_edn_fatal_err_o Yes Yes T331,T332,T333 Yes T331,T332,T333 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%