Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3817019	1			T94	132		T95	96		T96	106
values[2]	786693	1			T94	57		T95	53		T96	48
values[3]	115601	1			T158	3		T570	13		T279	7
values[4]	60802	1			T570	20		T689	17		T561	1
values[5]	41065	1			T570	18		T689	34		T454	1
values[6]	31167	1			T570	10		T689	21		T454	11
values[7]	25226	1			T570	17		T689	14		T454	10
values[8]	21603	1			T570	5		T689	21		T454	14
values[9]	19398	1			T570	12		T689	19		T454	7
values[10]	17387	1			T570	25		T689	24		T454	4
values[11]	15996	1			T570	13		T689	19		T454	1
values[12]	14984	1			T570	14		T689	26		T454	3
values[13]	14389	1			T570	19		T689	37		T454	7
values[14]	13909	1			T570	17		T689	22		T454	20
values[15]	13298	1			T570	8		T689	17		T454	4
values[16]	12707	1			T570	5		T689	29		T454	4
values[17]	11854	1			T570	7		T689	21		T454	3
values[18]	11344	1			T570	15		T689	19		T454	12
values[19]	11036	1			T570	27		T689	24		T454	21
values[20]	10384	1			T570	23		T689	19		T454	22
values[21]	10112	1			T570	12		T689	34		T454	19
values[22]	10171	1			T570	25		T689	17		T454	9
values[23]	9798	1			T570	23		T689	24		T454	7
values[24]	9538	1			T570	14		T689	21		T454	3
values[25]	8993	1			T570	14		T689	26		T454	9
values[26]	8574	1			T570	11		T689	12		T454	8
values[27]	8286	1			T570	8		T689	16		T454	8
values[28]	7986	1			T570	23		T689	16		T454	1
values[29]	7252	1			T570	5		T689	12		T454	7
values[30]	6734	1			T570	1		T689	12		T454	6
values[31]	6242	1			T570	7		T689	9		T454	5
values[32]	5849	1			T570	4		T689	10		T454	2
values[33]	5304	1			T570	2		T689	18		T454	2
values[34]	4939	1			T689	19		T454	3		T582	23
values[35]	4644	1			T689	9		T454	3		T582	28
values[36]	4257	1			T689	9		T454	4		T582	19
values[37]	4174	1			T689	4		T454	6		T582	20
values[38]	3942	1			T689	4		T454	11		T582	22
values[39]	3601	1			T689	3		T454	1		T582	26
values[40]	3546	1			T689	3		T454	1		T582	20
values[41]	3474	1			T689	4		T454	4		T582	18
values[42]	3425	1			T689	3		T454	3		T582	20
values[43]	3316	1			T689	5		T454	1		T582	13
values[44]	3291	1			T689	8		T454	1		T582	27
values[45]	3289	1			T689	4		T582	15		T571	17
values[46]	3270	1			T689	3		T582	17		T571	22
values[47]	3291	1			T689	2		T582	22		T571	24
values[48]	3087	1			T689	3		T582	21		T571	16
values[49]	3010	1			T689	1		T582	19		T571	28
values[50]	2969	1			T689	2		T582	35		T571	24
values[51]	2933	1			T689	3		T582	21		T571	26
values[52]	2797	1			T689	2		T582	19		T571	19
values[53]	2786	1			T689	4		T582	16		T571	25
values[54]	2704	1			T689	2		T582	14		T571	36
values[55]	2601	1			T689	3		T582	19		T571	19
values[56]	2629	1			T689	2		T582	23		T571	15
values[57]	2488	1			T582	23		T571	12		T470	7
values[58]	2420	1			T582	13		T571	16		T470	5
values[59]	2487	1			T582	19		T571	15		T470	6
values[60]	2488	1			T582	19		T571	11		T470	2
values[61]	2642	1			T582	12		T571	14		T470	4
values[62]	4022	1			T582	33		T571	14		T470	9
values[63]	11006	1			T582	137		T571	127		T470	44
values[64]	223579	1			T582	335		T571	489		T470	149

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4925443	1			T94	103		T95	112		T96	95
values[2]	838279	1			T94	22		T95	46		T96	15
values[3]	87045	1			T94	1		T158	21		T177	2
values[4]	14908	1			T158	1		T279	1		T460	2
values[5]	5513	1			T561	2		T546	2		T562	1
values[6]	3324	1			T561	1		T550	1		T571	25
values[7]	2622	1			T550	1		T571	23		T470	3
values[8]	2158	1			T571	21		T470	4		T462	1
values[9]	1882	1			T571	34		T470	8		T462	1
values[10]	1645	1			T571	14		T470	4		T462	2
values[11]	1626	1			T571	10		T470	2		T462	1
values[12]	1432	1			T571	21		T470	2		T462	4
values[13]	1276	1			T571	37		T470	1		T462	3
values[14]	1193	1			T571	47		T470	1		T462	1
values[15]	1197	1			T571	38		T470	2		T462	1
values[16]	1046	1			T571	19		T470	2		T462	3
values[17]	1052	1			T571	17		T470	3		T462	1
values[18]	970	1			T571	11		T470	5		T462	3
values[19]	921	1			T571	14		T470	2		T462	6
values[20]	786	1			T571	8		T470	1		T462	2
values[21]	797	1			T571	2		T470	3		T462	2
values[22]	763	1			T571	3		T470	1		T462	2
values[23]	683	1			T571	2		T470	1		T462	4
values[24]	744	1			T571	3		T470	5		T462	2
values[25]	727	1			T571	2		T470	3		T462	1
values[26]	716	1			T571	4		T470	1		T462	3
values[27]	635	1			T571	3		T470	2		T462	1
values[28]	632	1			T571	2		T470	1		T462	1
values[29]	613	1			T571	2		T470	1		T462	1
values[30]	640	1			T571	7		T470	1		T462	1
values[31]	591	1			T571	5		T470	1		T462	1
values[32]	619	1			T571	3		T470	3		T462	1
values[33]	629	1			T571	2		T470	1		T462	3
values[34]	627	1			T571	5		T470	1		T462	1
values[35]	601	1			T571	2		T470	1		T462	2
values[36]	561	1			T571	1		T470	1		T462	6
values[37]	567	1			T571	1		T470	4		T462	3
values[38]	539	1			T571	4		T470	1		T462	1
values[39]	521	1			T571	5		T470	1		T462	3
values[40]	475	1			T571	2		T470	1		T462	1
values[41]	473	1			T571	1		T470	1		T462	1
values[42]	494	1			T571	2		T470	1		T462	2
values[43]	460	1			T571	3		T470	2		T462	3
values[44]	470	1			T571	1		T470	4		T462	4
values[45]	435	1			T571	2		T470	1		T462	2
values[46]	454	1			T571	1		T470	1		T462	3
values[47]	469	1			T571	1		T470	1		T462	1
values[48]	456	1			T571	4		T470	1		T462	1
values[49]	423	1			T571	3		T470	1		T462	2
values[50]	409	1			T571	3		T470	1		T462	2
values[51]	409	1			T571	1		T470	6		T462	3
values[52]	433	1			T571	10		T470	5		T462	6
values[53]	429	1			T571	2		T470	4		T462	1
values[54]	397	1			T571	1		T470	3		T462	2
values[55]	363	1			T571	3		T470	2		T462	1
values[56]	402	1			T571	1		T470	3		T462	2
values[57]	393	1			T571	1		T470	1		T462	1
values[58]	405	1			T571	1		T470	1		T462	3
values[59]	370	1			T571	1		T470	2		T462	2
values[60]	369	1			T571	1		T470	1		T462	1
values[61]	412	1			T571	3		T470	1		T462	1
values[62]	742	1			T571	8		T470	3		T462	1
values[63]	2760	1			T571	24		T470	13		T462	10
values[64]	28057	1			T571	80		T470	89		T462	135

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	566851	1			T94	1		T95	1		T96	1
values[2]	2687735	1			T94	109		T95	78		T96	128
values[3]	1268991	1			T94	35		T95	30		T96	58
values[4]	161610	1			T570	15		T241	8		T279	2
values[5]	82761	1			T570	9		T689	35		T561	7
values[6]	53924	1			T570	11		T689	15		T561	1
values[7]	39105	1			T570	12		T689	15		T454	5
values[8]	30358	1			T570	15		T689	23		T454	9
values[9]	25389	1			T570	12		T689	20		T454	2
values[10]	22640	1			T570	30		T689	34		T454	2
values[11]	20789	1			T570	19		T689	23		T454	12
values[12]	19402	1			T570	11		T689	14		T454	17
values[13]	18090	1			T570	16		T689	25		T454	7
values[14]	16712	1			T570	20		T689	33		T454	7
values[15]	15846	1			T570	10		T689	21		T454	8
values[16]	15235	1			T570	17		T689	20		T454	14
values[17]	14587	1			T570	18		T689	21		T454	15
values[18]	13829	1			T570	22		T689	19		T454	8
values[19]	13394	1			T570	8		T689	30		T454	5
values[20]	12973	1			T570	13		T689	16		T454	2
values[21]	12546	1			T570	19		T689	13		T454	1
values[22]	12254	1			T570	12		T689	26		T454	9
values[23]	11611	1			T570	16		T689	16		T454	4
values[24]	11099	1			T570	9		T689	28		T454	4
values[25]	10616	1			T570	16		T689	30		T454	8
values[26]	9978	1			T570	15		T689	31		T454	5
values[27]	9645	1			T570	11		T689	16		T454	3
values[28]	9001	1			T570	26		T689	19		T454	9
values[29]	8201	1			T570	23		T689	22		T454	5
values[30]	7548	1			T570	8		T689	24		T454	10
values[31]	7174	1			T570	2		T689	17		T454	6
values[32]	6505	1			T570	2		T689	11		T454	15
values[33]	5970	1			T570	3		T689	9		T454	25
values[34]	5608	1			T570	5		T689	14		T454	19
values[35]	5156	1			T570	2		T689	2		T454	5
values[36]	4941	1			T570	3		T689	1		T454	9
values[37]	4719	1			T570	6		T689	3		T454	6
values[38]	4627	1			T570	4		T689	2		T454	1
values[39]	4307	1			T570	3		T689	2		T441	1
values[40]	4135	1			T570	6		T689	3		T441	3
values[41]	3988	1			T570	3		T689	2		T441	6
values[42]	3703	1			T570	2		T689	1		T441	2
values[43]	3720	1			T570	3		T689	1		T441	1
values[44]	3757	1			T570	7		T689	3		T441	1
values[45]	3481	1			T570	4		T689	3		T441	2
values[46]	3428	1			T570	8		T689	3		T441	1
values[47]	3415	1			T570	9		T689	2		T441	1
values[48]	3344	1			T570	5		T689	2		T441	3
values[49]	3213	1			T570	2		T689	2		T441	1
values[50]	3255	1			T570	5		T689	3		T441	1
values[51]	3253	1			T570	5		T441	1		T582	18
values[52]	3239	1			T570	2		T441	2		T582	18
values[53]	3082	1			T570	3		T441	4		T582	26
values[54]	3126	1			T570	1		T441	2		T582	32
values[55]	3009	1			T570	8		T441	2		T582	19
values[56]	2875	1			T570	6		T441	2		T582	18
values[57]	2835	1			T570	4		T441	8		T582	15
values[58]	2736	1			T570	2		T441	4		T582	16
values[59]	2672	1			T570	2		T582	12		T571	17
values[60]	2733	1			T570	8		T582	17		T571	18
values[61]	2809	1			T582	28		T571	9		T470	8
values[62]	3769	1			T582	50		T571	25		T470	7
values[63]	9534	1			T582	166		T571	83		T470	43
values[64]	215736	1			T582	421		T571	343		T470	179